Clock tree synthesis Why we are doing the clock tree synthesis? To To minimize the insertion delay delay and skew skew Meet (max tran/cap/fanout) tran/cap/fanout)
Why we minimize the skew? we can minimize the skew w.r.t to HOL if skew is minimum HOL !iolation is "!e slack
Why we are talking insertion delay is minimum ? #f we ha!e insertion dealy $%ns&&&&&&&&&&&&&&&..% 'kew$tcap(max)tlan(min) pply oc! on *+, on clk $ %*++-++ $ ++ #f we ha!e insertion delay $*ns &&&&&&&&&&&&&&&&&&.* 'kew$tcap(max)tlan(min) pply oc! on *+, on clk $ *++%++ $ -++ 0hen compared case % and case * the skew is minimum in insertion delay is less.
Why we are applying the NDR (non-default-routing)? To To a!oid the Crosstalk and and lectromigration!
"or crosstalk 1 increasin2 the space 'hieldin2
"or lectromigration1 increasin2 the width. #ow does u reduce timing $iolation after placement? What is mean %y clock recon$ergence path?
What is mean %y clock insertion delay? Clock network delay? &nsertion delay' the delay from clock source to clock de3nition point. Network delay' the delay from clock de3nition point to clock pin of a 4ip4op &f you increase clock freuency in the design what are the issues you could e*pect? • • •
5ower dissipation is more. 'etup !iolation increases. 6tilization increases.
&f you want to reduce clock network power what do you do?
Clock network is the most power consuming circuit in the design! Can you +ustify why?
What are di,erent low power techniues that you follow to reduce power? (tatic . Dynamic) 5ower 2atin2 7lock 2atin2
What is mean %y clock gating? The purpose of the clock 2atin2 is to minimize the power dissipated inside the 4ip 4op 8y eliminatin2 the clock acti!ity at the 4ip 4op durin2 clock cycles when the 4ip4op input is not acti!e.
What is clock di$ider mean? What is clock %u,er? #ow it is di,erent compared to signal %u,er? 7lock 8u9ers are desi2ned with some special property like hi2h dri!e stren2th and less delay. 7lock 8u9ers are e:ual rise time and fall time. ;ormal 8u9ers are desi2ned with 0/L ratio such that sum of rise time and fall time is minimum. They too are desi2ned for hi2her dri!e stren2th. /&f you ha$e timing $iolations (setup . hold) after C0 how do you decide to go ahead to routing? or go %ack to C0 again?
0o counter 1 issues what do you do on clock nets? #ncreasin2 the width of the clock net
0o a$oid & issues what is the special care you take on clock nets? What is mean %y aggressor . $ictim in &? Why always clock nets are aggressors? 9ectin2 si2nal is termed as aggressor 9ected si2nal is $ictim 7lock net is a hi2h to22lin2 si2nal.
What is mean %y ignal &ntegrity ? Cross talk? Why does it occur? #ow Clock nets e,ect &?
Which layers did you used in your design for clock net routing? Can you +ustify why did you used that layers? ;ext lower layer to the top two metal layers
Why do we need to gi$e more spacing . width to clock nets compared to default foundry gi$en rules? 7lock net are hi2hly to22lin2 networks . What are di,erent non-default rules that we apply on clock nets compared to signal nets? ou8le width dou8le space ou8le width sin2le space 'in2le width dou8le space shieldin2
/What does CR2R will impact timing?
#ow does Derate factor will impact timing? What is 3C4? Why do we need Derate factor? O7= is On 7hip =ariation with respect to 5=T (process> !olta2e> temperature)
What is CR2R? Why do we need it? What is useful skew concept? /&n case you can5t reduce further skew which is causing some timing $iolations what is alternate method to sol$e timing issue?
/&n case if you got new setup $iolations after C0 compared to pre-C0 what could %e the reason how do you sol$e it? 6) /&f you ha$e congestion issue after C0 where as you dint had %efore C0 what would %e the reason how do you sol$e it? /Can you add any num%er of %u,ers to meet skew? #ow does clock %u,ers will impact design? (#ow do you decide the ma* num%er of clock %u,ers in a clock path?) What is mean %y skew group?
#ow do you %alance two asynchronous clocks? What is mean %y clock group?
Will you check hold time %efore C0? Why can5t we check ? 0e won?t check hold 8efore 7T'> why 8ecause clock is not propa2ated so the real skew not comin2 to picture. @@ if we want to try to 3x hold !iolation 8efore 7T' the skew will e9ect 8ecause of addin2 8u9ers implies increases area. &f you ha$e any hold timing $iolations after C0 how will you sol$e it? ddin2 8u9er / #n!erter pairs /delay cells to the data path helps to 3x the hold !iolation. ownsizin2 the cell
What are the di,erent checks you do %efore you take data%ase to C0 stage? What is clock transition $iolation? What is inter clock skew %alancing mean? &f you ha$e met setup timing %efore C0 can you e*pect setup $iolations after C0? &f 7 Why? Aes.we can expect setup !iolation after 7T'.
What are di,erent clock %alancing techniues you followed? /Can you e*pect any congestion increase after C0 compared to %efore C0? & f 7 why congestion may increase after C0? What is mean %y clock tree spec 8le? What does it contain? Where the clock tree info e*ists during - among inputs you take in C0 stage? What are mandatory inputs needed for C0? 7lock Tree spec 3le. 5lacement data8ase (BC) ;etlist Timin2 constraints 3le ('7) .li8 Lef What are other $iolations will you check other than setup timing . congestion after placement? Max transition Max capacitance Max fan out
Will clock freuency will %e same in setup timing report . hold? 9ny comment? 9ssume you ha$e 6:: setup timing $iolations after placement! What is y our ne*t step? Will you go %ack change ;oorplan? or Will you continue to C0? 3r will you 8* setup $iolations using any C3s? or Will you try to sol$e this issue any other way?! #ow do y ou decide e$en with some setup timing $iolations to go forward to C0 or not? #ow can you 8nd the operating clock freuency? #ow do you 8nd uncertainty of the the clock de8ned? . What is uncertainty why do we de8ne that?
&f you gi$e priority to timing!! Does it impact congestion? &f 7 how . why? Will you check #3 clock or 8oth. lack 1 the di9erence 8etween re:uired time and the time that a si2nal arri!es. What was the skew $alue did you see in timing report after placement? Dero 7lock is ideal. What is WN 0N . "ailing end points? Wns' the path ha!in2 the maximum ne2ati!e slack. 0N1 sum of all ne2ati!e slack in the desi2n. What is critical path? #ow do you +ustify it5s a critical path? The path 8etween an input and an output with the maximum delay.
Can you e*pect net delay s in timing report after placement? (& mean if you report using -nets option will you see net delays?! & f 7 how does the net delay is calculated? & f N3 why can5t we report estimated net delay?) Aes .these are approximations. @8ased on trial route.
What is Wireload model? What is =ero Wireload model timing? 0hich calculate the net delay 8ased on the num8er of Canouts of particular 2ate
0hat are the challen2es in lowpower 0hat is adEust #O 0hat are the input 3les re:uired for prime time 0hat is the syntax for '5BC 0hat is the syntax for 'C 0hat are the input 3le fot 5T if we 2i!e 'C 0hat is 2ate count 0hat is the fre:uency of Flowpower proEectG How many re2isters are re:uired for *x% IM # ha!e 8lock # can increase fre:uency from J++Mhz to JKHD so what are the pro8lems we face and what is the e9ect on setup and hold.
#ow do we %alance skew if their multiple clocks 6sin2 interclockdelay 8alancin2.
Why do we need to 8* transition $alues in the design e$en though timing is meeting! #f we don?t 3x the transition the si2nals may 8e prone to noise which may lead to improper functionalty of the chip. What are the C0 targets? kew &nsertion delay "anout 1a*>min capacitance What are the stages of C0?
