4
3
2
1
SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO’S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
BONN-L CPU
:Intel Penryn
Chip Set : Intel Cantiga & ICH9M C
Remarks
: Montevina Platform
C
Model Name : R519 PBA Name
: MAIN
PCB Code
: GCE : NAN : HAN :
B
Dev. Step
: PR
Revision
: 1.2
T.R. Date
: 2009.06.03
Design
CHECK
B
APPROVAL
A
A DRAW
DATE
SY.KIM CHECK
10/10/2008
Signature :
APPROVAL
X
PR
MAIN
1.2
COVER
REV
H.J.KIM MODULECODE
SAMSUNG
BONN-L
DEV. STEP
HK.PARK
Owner : SEC Mobile R & D
TITLE
ELECTRONICS PART NO.
BA41-
LAST EDIT
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FAN
Clocking
PG 8
CK-505
D
EMC2112
Smart Battery Module
Charging Circuit
IMVP-6
Penryn-6M FSB 1067
CPU Thermistor
PG 12
CPU DC/DC
Mobile Processor
DC/DC D
ON BOARD
478pin
PG 8 PG 9-11
L2 Cache : 6/3MB
PG 18,19 Channel A (Standard)
LCD
GMCH-M Cantiga-GM
LCD
GL40
PG 26 CRT
PG 27
VCCP / DC-DC
Termination
FSB 800/1067 MT/S
PG 48
PG 18 DDR II SODIMM 0
DDR II 667/800
DDR II Power
Dual channel Channel B (Reverse)
PG 19 DDR II SODIMM 1
DDR II 667/800
PG 47
1329 FCBGA
CRT
PG 13-17
Direct Media Interface x4, 1.5V
C PG 42, 52
USB 0,2,6
PG 43
C
PCIE x1
RTL103EL
Lane 4
RJ45
PG 34
ANT PG 43
CLINK
USB 0,2,6
USB 5
Bluetooth
Camera
OPTION
USB 8
PCIE x1
ICH9-M
PG 34
52P
Lane 1
ANT
Mini Card 1
PG 37
USB 1
(WLAN) 676 BGA
High Definition Audio PG 20 - 24 PG 31
Aud.
Audio ALC269
AMP
HD Audio PCIE x1
Lane 3
Express Card
USB 7 PG 30 B
PG 35 B
PG 33
PG 25
HP MIC-IN
SPI ROM
USB 4
SPI
GENESIS C P L
2P 2P
PG 38
SATA HDD
PG 53
SATA ODD
SPKR
MMC
PG 36
12P PG 40 3.3V LPC, 33MHz PG 38
MICOM
Touch PAD
MEC1308 TMKBC (TBD)
KBD
PG 39
L
A
80 Port
Touchpad LED
PG 40
PG 40 A
LED DRAW
PG 25
PG 41
DATE
SY.KIM CHECK
APPROVAL
9/23/2008
MODULECODE
ELECTRONICS
MAIN
1.2
BLOCK DIAGRAM
PART NO.
BA41-
LAST EDIT
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2
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PG 36
PG 36
SATA 1
Sub board R
SD
SATA 0
PG 31
SPKR
2 IN 1
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FAN
Clocking
PG 8
CK-505
D
EMC2112
Smart Battery Module
Charging Circuit
IMVP-6
Penryn-6M FSB 1067
CPU Thermistor
PG 12
CPU DC/DC
Mobile Processor
DC/DC D
ON BOARD
478pin
PG 8 PG 9-11
L2 Cache : 6/3MB
PG 18,19 Channel A (Standard)
LCD
GMCH-M Cantiga-GM
LCD
GL40
PG 26 CRT
PG 27
VCCP / DC-DC
Termination
FSB 800/1067 MT/S
PG 48
PG 18 DDR II SODIMM 0
DDR II 667/800
DDR II Power
Dual channel Channel B (Reverse)
PG 19 DDR II SODIMM 1
DDR II 667/800
PG 47
1329 FCBGA
CRT
PG 13-17
Direct Media Interface x4, 1.5V
C PG 42, 52
USB 0,2,6
PG 43
C
PCIE x1
RTL103EL
Lane 4
RJ45
PG 34
ANT PG 43
CLINK
USB 0,2,6
USB 5
Bluetooth
Camera
OPTION
USB 8
PCIE x1
ICH9-M
PG 34
52P
Lane 1
ANT
Mini Card 1
PG 37
USB 1
(WLAN) 676 BGA
High Definition Audio PG 20 - 24 PG 31
Aud.
Audio ALC269
AMP
HD Audio PCIE x1
Lane 3
Express Card
USB 7 PG 30 B
PG 35 B
PG 33
PG 25
HP MIC-IN
SPI ROM
USB 4
SPI
GENESIS C P L
2P 2P
PG 38
SATA HDD
PG 53
SATA ODD
SPKR
MMC
PG 36
12P PG 40 3.3V LPC, 33MHz PG 38
MICOM
Touch PAD
MEC1308 TMKBC (TBD)
KBD
PG 39
L
A
80 Port
Touchpad LED
PG 40
PG 40 A
LED DRAW
PG 25
PG 41
DATE
SY.KIM CHECK
APPROVAL
9/23/2008
MODULECODE
ELECTRONICS
MAIN
1.2
BLOCK DIAGRAM
PART NO.
BA41-
LAST EDIT
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2
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DEV. STEP
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PG 36
PG 36
SATA 1
Sub board R
SD
SATA 0
PG 31
SPKR
2 IN 1
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D
BOARD INFORMATION
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION PCI Devices Devices
IDSEL#
REQ/GNT#
Interrupts
Cardbus
AD25
3
A,B,C
USB
AD29(internal)
-
Hub to PCI LPC bridge/IDE/AC97/SMBU bridge/IDE/AC97/SMBUS S
AD30(internal) AD31(internal)
-
Internal MAC AC Link GLAN
AD24(internal) -
-
Crystal / Oscillator TYPE
FREQUENCY
DEVICE
USAGE
Crystal Crystal Crystal Crystal
32.768KHz 10MHz 14.318MHz 25MHz
ICH9-M MICOM CLOCK-Generator LAN
Real Time Clock HD64F2169/2160 CK-505 RealTek 88E8057
g n l u a a s i t m n a e S f i d d n o C USB2.0 #0 (USB0) : A USB2.0 #1 (USB1) : D USB2.0 #2 (USB4) : C USB2.0 #3 (USB5) : E USB2.0 #4 (EHCI) : H B
E B F
C
D
LCD Pannel Detect Devices
Voltage Rails
(TBD)
Resolution
C
PANNEL_DETECT_0
2
VDC VCC_CORE P1.05V (VCCP) P3.3V_MICOM P1.5V P1.8V P1.8V_AUX P0.9V P3.3V P3.3V_AUX P5.0V P5.0V_AUX P5.0V_ALW
I C / SMB Address
Primary DC system power supply (9 to 20V) Core Voltage for CPU VTT for CPU, Crestline & ICH9-M 3.3V always power rail (for Micom) 1.5V switched power rail (off in S3-S5) 1.8V switched power rail (off in S3-S5) 1.8V power rail for DDR (off in S4-S5) 0.9V power rail for DDR (off in S3-S5) 3.3V switched power rail (off in S3-S5) 3.3V switched on power rail (off in S4-S5) 5.0V switched power rail (off in S3-S5) 5.0V switched on power rail (off in S4-S5) 5.0V always power rail
B
USB PORT Assign PORT # 0 1 2 3 4 5 6 7 8 9
ASSIGNED TO SYSTEM PORT 0 SYSTEM PORT 1 SYSTEM PORT 2 NC NC Bluetooth Mini PCI Express 2 Camera NC NC
Devices
Address
Hex
Bus
ICH9-M CPU Thermal Sensor SODIMM0 SODIMM1 Thermal Sensor on SODIMM0 Thermal Sensor on SODIMM1 CK-505M (Clock Generator)
Master 0111 101x 1010 000x 1010 010x 0011 000x 0011 010x 1101 001x
7Ah A0h A4h 30h 34h D2h
SMBUS Master Thermal Sensor Clock, Unused Clock Output Disable
B
PCI Express Assign PORT # 0 1 2 3 4 5
ASSIGNED TO
REVISION HISTORY
NC Mini Card 1 (WLAN) NC LOM Mini Card 2 (ROBSON or DVB-T) NC
See rev notes for more information.
A
A DRAW
DATE
SY.KIM CHECK
9/23/2008
APPROVAL
MODULE CODE
MAIN
1.2
BOARD INFO
ELECTRONICS PART NO.
BA41-
LAST EDIT
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POWER DIAGRAM KBC3_SUSPWR (CHP3_S4_STATE*)
D
AC Adapter
KBC3_PWRON
VDC
D
(CHP3_SLPS3*)
P1.05V_AUX
Battery DC
Rev 0.1
P1.05V (VCCP)
KBC3_VRON
MEROM CRESTLINE ICH8-M
g n l u a a s i t m n a e S f i d d n o C
VCC_CORE
MEROM
P1.5V_AUX
ICH9-M
P1.5V_AUX
SODIMM (DDR III) Cantiga
P0.9V
DDR III-Termination
PEG GDDR-3 for PEG
P1.8V
DDR II-Termination
P0.9V
OPTION FOR ME
C
ICH8-M FDD CRT MICOM
It should be updated
P3.3V_MICOM
P5.0V
P5V_AUX
MICOM
IGFX_CORE
P3.3V_ALW
P3.3V_AUX
EGFX_CORE
nVidia (TBD)
P3.3V
CRESTLINE ICH8-M SPI PEG MDC
Thermal Sensor SODIMM PCMCIA LEDs
MICOM B
M_PCI LCD
CRESTLINE ICH8-M
P1.25V
P1.2V_LAN
P12.0V_ALW
FAN CIRCUIT AUX DISPLAY
CRESTLINE
CRESTLINE ICH8-M
P5.0V_ALW
HDD M_PCI
PEG
P1.5V
ICH8-M LAN MDC BT
B
C PCMCIA USB HEATSINK MDC
LAN
PEG
P1.8V_LAN P2.5V_LAN
Power On/Off Table by S-state
LAN
Rail State +V*A(LWS) +V*LAN A
+1.8V_AUX +0.9V +V*AUX +V +V* (CORE)
P1.2V
S0
S3
S4
S5
ON
ON
ON
ON
ON
ON
S5-S4
S0
S3
A DRAW
ON
DATE
SY.KIM
ON
CHECK
9/23/2008
APPROVAL
MODULE CODE
3
2
MAIN
1.2
POWER DIAGRAM
PART NO.
BA41-
LAST EDIT
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4
ELECTRONICS
PR REV
H.J.KIM
ON
SAMSUNG
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HK.PARK
ON
TITLE
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POWER RAILS ANALYSIS Rev. 0.6 (060920)
220V
D
D
) ) A Adapter Battery A D D B MICOM 3V ( TBD A ) T B ( T 1.8V ( TBD A ) ( X X U U A A _ _ V V 0 . 3 . 5 3
CPU CORE ( TBD A ) 1.05V ( TBD A ) 1.5V ( TBD A ) 1.25V ( TBD A ) 3.3V ( TBD A ) 5.0V ( TBD A ) 1.8V_AUX ( TBD A ) 0.9V( TBD A ) C
) ) A A ) D D A B T y B D ( T E r e ( B T R t V ( O t a N I O C B I _ C X A C D E G T V P V R
g n l u a s i t m n a e S f i d n o C 1.05V
CPU CORE 1.05V (VCCP) 1.5V
0.1 A (TBD)
41 A (TBD) 4.5 A (TBD) 0.13 A (TBD)
ITP
Penryn-6M ( 35 W )
3.3V
MICOM 3V 3.3V
Thermal Sensor
0.75 A (TBD)
0.08 A (TBD) 0.08 A (TBD)
MICOM 3V
1.05V (MCH CORE) 1.05V (VCCP) 1.5V 1.25V 3.3V 1.8V_AUX
7.7 A (TBD) 4.48 A (TBD) 0.125 A (TBD) 2.43A (TBD) 0.33 A (TBD) 3.79 A (TBD)
Cantiga GMCH (8 - 8.5 W )
3.3V
3.3V
1.05V 1.5V 3.3V 3.3V_AUX 5V 5V_AUX RTC_Battery
1.0V-1.1V (EGFX CORE) 1.8V
1.2V (PEX IO) 3.3V
1.13 A (TBD) 2.4A (TBD) 0.374 A (TBD) 0.209 A (TBD) 0.001 A (TBD) 0.001 A (TBD) 0.006 A (TBD)
ICH9-M
( ~ 2.0 W )
3.3V
3.3V 5V
17.75 A (TBD) 6.53 A (TBD)
3.3V
0.2 A (TBD)
KeyBoard
3.3V_AUX
0.01 A (TBD)
KBD LED
3.3V_AUX
SPI
0.015 A (TBD)
5V
3.3V 3.3V_AUX 1.5V
1.8V_AUX
1.5 A (TBD)
ODD
0.9V
3.1 A (TBD) 1 A (TBD)
DDR-2
(Dual slots)
5V
LAN
0.1 A (TBD)
SD Card
1.5 A (TBD) 0.5 A (TBD) 0.75A (TBD)
Mini Card
SATA
3.3V_AUX
B
0.6 A (TBD)
5V
PEG
1.75 A (TBD) 0.67 A (TBD)
C
3.3V
HD Audio
0.06 A (TBD) 0.07 A (TBD)
PWR LED
1.8V 3.3V
CLOCK
0.25 A (TBD)
0.1 A (TBD)
KBC
0.5 A (TBD)
MDC
B
SATA HDD
0.22 A (TBD)
( ~ 5.0 W )
1.8V
3.1 A (TBD)
GDDR
5V
LCD
5V
3.3V (LCD 3V)
19V (VDC INV)
P3.3V_AUX P1.2V_LAN P1.8V/2.5V_LAN
0.08 A (TBD) 0.29 A (TBD) 0.15 A (TBD)
0.67 A (TBD) 0.5 A (TBD)
5V
LAN (RTL103EL)
5V
FAN
0.16 A (TBD)
Audio AMP
1.5 A (TBD)
USB (x 3)
2 A (TBD)
Touch Pad
0.2 A (TBD)
A
A DRAW
DATE
SY.KIM
Value by Datasheet/Application notes (Value by measurement)
CHECK
9/23/2008
APPROVAL
MODULE CODE
MAIN
1.2
POWER RAILS
ELECTRONICS PART NO.
BA41-
LAST EDIT
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TITLE
June 03, 2009 16:14:25 PM
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SAMSUNG PROPRIETARY Host Boot / ME Off
THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO’S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.
M-1) KBC3_DDR_PWRON (TBD) = 8) KBC3_SUSPWR
X U A _ V 3 . 3 P ) 6
M-2) KBC3_ME_PWRON = 15) KBC3_PWRON Host / ME Boot (SLPS4* = S4_STATE*) > SLPM* > SLPS3*
D
Host S5 / ME Boot
S/W
P L S _ 0 0 1 N A L
10-1) ICH_CORE (P1.05V) 8) CHP3_SLPS5#/4#/3#
4
POWER SEQUENCE
KBC
N E M R V T N I
CK-505
16) CLK3_PWRGD
g n l u a s i t m n a e S f i d n o C 13) KBC3_VRON (Back-up)
DC/DC B’d
18
17) KBC3_PWRGD
PWROK
110ms Delay
(Test Option)
18) CPU1_PWRGDCPU
15)VRM3_CPU_PWRGD
ICH8-M
5) KBC3_SUSPWR 9) KBC3_PWRON
3 r e t p a d A y r e t t a B
P3.3V_MICOM AC_DC / Battery
ICSL6256
2
R W P S U S _ 3 C B K ) 8
13 N O R W P _ 3 C B K ) 9
10-1) P1.5V
Sheet 22-25
20
10-1) P1.05V
10) P5.0V
DDR2 POWER
SC486
5) KBC3_SUSPWR
SC486
10) P1.5V
AP4435
10) P5.0V
6) P1.8V_AUX
6) MEM1_VREF
6
20) CPU1_CPURST*
17) KBC3_PWRGD
PWROK
17) KBC3_PWRGD
10-2) 0.9V
19) PLT3_RST*
CL_PWROK
Sheet 50
GMCH
10
9-1
C
Sheet 10-12
2) VDC
C D V ) 2
2-1) P12.0V_ALW
CL_PWROK
14
19
19) PCI3_RST*
17) KBC3_PWRGD
9
13) KBC3_VRON
C
14) VCC_CORE
CPU
19) PLT3_RST*
5
D
CPU VRM
12)GCORE3_PWRGD (PM-model)
VRMPWRGD
17
15
16-1) Clock Running
Sheet 8
15)VRM3_CPU_PWRGD
17) KBC3_PWRGD
Rev. 0.7
16
7) P1.05V_AUX 7) P1.5V_AUX
7) KBC3_RSMRST#
7
* W S _ R E W O P ) 4
1
PRTC_BAT CHP3_RTCRST#
15) VRM3_CPU_PWRGD PRTC PRTC
(SLPS4* = SLPM*) > S4_STATE* > SLPS3*
8
POWER
RTC Battery
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*)
2) VDC
6) P1.8V_AUX
10) P1.1
9) KBC3_PWRON
ISL6227
10) P1.05V (IGFX_CORE) PM-model only
10) P1.05V
10-1) P3.3V
Sheet 15-19
9-1) KBC3_PWRON_INV#
11-1) GFX_CORE
B
3
P3.3V_AUX & P5V_AUX
TPS51120
P5.0V_ALW
P3.3V_MICOM
11) VCCP3_PWRGD
6) P5.0V_AUX
6
9
6) P3.3V_AUX
AP6680A
9) KBC3_PWRON
X U A _ V 3 . 3 P ) 6
10-1) P3.3V
10-1) P3.3V
SC471
10-1) P1.8V
12)GCORE_PWRGD
11
10) P1.5V
12
PCIe Devices
B
19
Sheet 40
10-1) P1.2V
6) P1.8V_AUX
11) VCCP3_PWRGD
AP6680A
Sheet 40
11-1) P1.8V
2) VDC
6) P1.8V_AUX
DDR3 Memory
10-2) P0.9V
10-1) P3.3V
PEG
Sheet 20-21
10-1) P3.3V 10-1) P1.8V
A
LOM Marvell
6-1) P1.2V_LAN
10) P1.5V
BCP69
19) PCI3_RST*
A
6-1) P1.8V/P2.5V_LAN
Sheet 46
DRAW
Sheet 46-47
DATE
SY.KIM CHECK
APPROVAL
9/23/2008
MODULECODE
ELECTRONICS
MAIN
1.2
POWER SEQUENCE
PART NO.
BA41-
LAST EDIT
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PCI Devices
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P3.3V
CLOCK DISTRIBUTION FS(2:0)
D
266 MHz
1
CLK3_PWRGD*
CLK0_HOST_CPU/CPU*
D
BSEL
CPU
FSB
X U M
ITP_EN
667/800 MHz 333/400 MHz
CPU_STP*
266 MHz
Main PLL SSC
CLK0_HOST_GMCH/GMCH*
X U M
B
SS(96/100) SEL
PLL3 SSC
) C D S S & * ) Q 5 E 0 r R 3 K 1 L 5 C P / S w 8 ( G M L 5 S 0 x 5 K C
HPLL MPLL
CLK1_MCLK0/0#
g n l u a s i t m n a e S f i d n o C
100 MHz (SRC0)
C
Rev. 0.1
CLK1_PEG/PEG*
PCI Express Gfx MCH3_CLKREQ*
100 MHz (SRC4)
Cantiga MCH
PEG
CLK1_MCH3GPLL/3GPLL*
333/400 MHz
CLK1_MCLK1/1#
333/400 MHz
CLK1_MCLK3/3#
333/400 MHz
CLK1_MCLK4/4#
PCIE PLL
96 MHz
CLK1_DREFCLK/CLK*
100 MHz
CLK1_DREFSSC/SSC*
SODIMM #0
SODIMM #1
DPLLA DPLLB
C
MIN3_CLKREQ*
100 MHz (SRC 6)
CLK1_MINIPCIE/PCIE*
DMI
100 MHz (SRC 6,8,9,10)
ITM3_CLKREQ*
100 MHz (SRC 8)
100 MHz (SRC 3)
CLK1_PCIEICH/ICH*
48 MHz
CLK3_USB48
PCIEPLL
48MHz PLL X U M
33 MHz Buffer
MINI PCIE CARD 2
LOM3_CLKREQ*
ICH9-M
100 MHz (SRC 9)
CLK1_PCIELOM/LOM*
PCIE LAN (Marvell)
USBPLL
25 MHz
CHP3_SATACLKREQ*
100 MHz (SRC 2)
CLK1_SATA/SATA*
14.318 MHz
CLK3_ICH14
33 MHz
CLK3_PCLKICH
EXP3_CLKREQ*
SATAPLL
CLK1_EXPCARD#
32.768 KHz OSC
AUD3_BCLK
HD 24 MHz
PCI_STP*
CLK1_MINI2PCIE/PCIE*
MINI PCIE CARD 1
33 MHz
CLK3_PCLKMICOM
KBC
10 MHz
MDC3_BCLK
RTC Clock 32.768 KHz
EXPRESS CARD
B
HD Audio MDC
17.86 MHz
SPI3_CLK
33 MHz
CLK3_PCLKPORT80
SPI
PORT 80
14 MHz OSC
A
A
14.318 MHz
DRAW
DATE
SY.KIM
Page 8
CHECK
9/23/2008
APPROVAL
MODULE CODE
MAIN
1.2
CLOCK DIAGRAM
PART NO.
BA41-
LAST EDIT
undefined
2
ELECTRONICS
PR REV
H.J.KIM
3
SAMSUNG
BONN-L
DEV. STEP
HK.PARK
4
TITLE
June 03, 2009 16:14:25 PM
PAGE
7
OF
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