Pcm Principles

PCM Principles, Digital multiplexing hierarchy, Principles of MUX and Higher order MUX

PCM Principles, Digital MUX & Higher Order MUX

PCM PRINCIPLES 1.0 INTRODUCTION 1.1

A long distance or local telephone conversation between two persons could be provided by using a pair of open wire lines or underground cable as early as early as mid of 19th century. However, due to fast industrial development and an increased telephone awareness, demand for trunk and local traffic went on increasing at a rapid rate. To cater to the increased demand of traffic between two stations or between two subscribers at the same station we resorted to the use of an increased number of pairs on either the open wire alignment, or in underground cable. This could solve the problem for some time only as there is a limit to the number of open wire pairs that can be installed on one alignment due to headway consideration and maintenance problems. Similarly increasing the number of open wire pairs that can be installed on one alignment due to headway consideration and maintenance problems. Similarly increasing the number of pairs to the underground cable is uneconomical and leads to maintenance problems.

1.2

It, therefore, became imperative to think of new technical innovations which could exploit the available bandwidth of transmission media such as open wire lines or underground cables to provide more number of circuits on one pair. The technique used to provide a number of circuits using a single transmission link is called Multiplexing.

2.0 MULTIPLEXING TECHNIQUES 2.1

There are basically two types of multiplexing techniques i.

Frequency Division Multiplexing (FDM)

ii

Time Division Multiplexing (TDM)

BRBRAITT, Jabalpur,

2


2.2

Frequency Division Multiplexing Techniques (FDM) The FDM techniques is the process of translating individual speech circuits (300-3400 Hz) into pre-assigned frequency slots within the bandwidth of the transmission medium. The frequency translation is done by amplitude modulation of the audio frequency with an appropriate carrier frequency. At the output of the modulator a filter network is connected to select either a lower or an upper side band. Since the intelligence is carried in either side band, single side band suppressed carrier mode of AM is used. This results in substantial saving of bandwidth mid also permits the use of low power amplifiers. Please refer Fig. 1.

FDM techniques usually find their application in analogue transmission systems. An analogue transmission system is one which is used for transmitting continuously varying signals. 2.3

Time Division Multiplexing

2.3.1 Basically, time division multiplexing involves nothing more than sharing a transmission medium by a number of circuits in time domain by

BRBRAITT, Jabalpur,

3


establishing a sequence of time slots during which individual channels (circuits) can be transmitted. Thus the entire bandwidth is periodically available to each channel. Normally all time slots1 are equal in length. Each channel is assigned a time slot with a specific common repetition period called a frame interval. This is illustrated in Fig. 2. 2.3.2 Each channel is sampled at a specified rate and transmitted for a fixed duration. All channels are sampled one by, the cycle is repeated again and again. The channels are connected to individual gates which are opened one by one in a fixed sequence. At the receiving end also similar gates are opened in unision with the gates at the transmitting end. 2.3.3 The signal received at the receiving end will be in the form of discrete samples and these are combined to reproduce the original signal. Thus, at a given instant of time, onty one channel is transmitted through the medium, and by sequential sampling a number of channels can be staggered in time as opposed to transmitting all the channel at the same time as in EDM systems. This staggering of channels in time sequence for transmission over a common medium is called Time Division Multiplexing (TDM).

BRBRAITT, Jabalpur,

4


3.0 PULSE CODE MODULATION SYSTEM 3.1

It was only in 1938, Mr. A.M. Reaves (USA) developed a Pulse Code Modulation (PCM) system to transmit the spoken word in digital form. Since then digital speech transmission has become an alternative to the analogue systems.

3.2

PCM systems use TDM technique to provide a number of circuits on the same transmission medium viz open wire or underground cable pair or a channel provided by carrier, coaxial, microwave or satellite system.

3.3

Basic Requirements For PCM System To develop a PCM signal from several analogue signals, the following processing steps are required

BRBRAITT, Jabalpur,

5


•

Filtering

•

Sampling

•

Quantisation

•

Encoding

•

Line Coding

4.0 FILTERING 4.1

Filters are used to limit the speech signal to the frequency band 3003400 Hz.

5.0 SAMPLING 5.1

It is the most basic requirement for TDM. Suppose we have an analogue signal Fig. 3 (b), which is applied across a resistor R through a switch S as shown in Fig. 3 (a) . Whenever switch S is closed, an output appears across R. The rate at which S is closed is called the sampling frequency because during the make periods of S, the samples of the analogue modulating signal appear across R. Fig. 3(d) is a stream of samples of the input signal which appear across R. The amplitude of the sample is depend upon the amplitude of the input signal at the instant of sampling. The duration of these sampled pulses is equal to the duration for which the switch S is closed. Minimum number of samples are to be sent for any band limited signal to get a good approximation of the original analogue signal and the same is defined by the sampling Theorem.

BRBRAITT, Jabalpur,

6


FIG. 3 : SAMPLING PROCESS 5.3

Sampling Theorem

5.3.1 A complex signal such as human speech has a wide range of frequency components with the amplitude of the signal being different at different frequencies. To put it in a different way, a complex signal will have certain amplitudes for all frequency components of which the signal is made. Let us say that these frequency components occupy a certain bandwidth B. If a signal does not have any value beyond this bandwidth B, then it is said to be band limited. The extent of B is determined by the highest frequency components of the signal. 5.3.2 Sampling Theorem States "If a band limited signal is sampled at regular intervals of time and at a rate equal to or more than twice the highest signal frequency in the band, then the sample contains all the information of the original signal." Mathematically, if fH is the highest frequency in the signal to be sampled then the sampling frequency Fs needs to be greater than 2 fH. i.e. Fs>2fH 5.3.3 Let us say our voice signals are band limited to 4 KHz and let sampling frequency be 8 KHz.

BRBRAITT, Jabalpur,

7


Time period of sampling Ts =

1 sec 8000

or Ts = 125 micro seconds If we have just one channel, then this can be sampled every 125 microseconds and the resultant samples will represent the original signal. But, if we are to sample N channels one by one at the rate specified by the sampling theorem, then the time available for sampling each channel would be equal to Ts/N microseconds. 5.3.4

Fig. .4 shows how a number of channels can

be

sampled

and

combined. The channel gates (a, b ... n) correspond to the switch S in Fig. 3. These gates are opened by a series of pulses called "Clock pulses". These are called gates because, when closed these actually connect the channels to the transmission medium during the clock period and isolate them during the OFF periods of the clock pulses. The clock pulses are staggered so that only one pair of gates is open at any given instant and, therefore, only one channel is connected to the transmission medium. The time intervals during which the common transmission medium is allocated to a particular channel is called the Time Slot for that channel. The width of.this time slot will depend, as stated above, upon the number of channels to be combined and the clock pulse frequency i.e. the sampling frequency.

BRBRAITT, Jabalpur,

8


FIG. 4: SAMPLING & COMBINING CHANNELS 5.3

In a 30

channel PCM system. TS i.e. 125 microseconds are divided into

32 parts. That is 30 time slots are used for 30 speech signals, one time slot for signalling

of

all the

30

chls,

and

one

time

slot for

synchronization between Transmitter & Receiver. The time available per channel would be Ts/N = 125/32 = 3.9 microseconds Thus in a 30 channel PCM system, time slot is 3.9 microseconds and time period of sampling i.e..the interval between 2 consecutive samples of a channel is 125 microseconds. This duration i.e. 125 microseconds is called Time Frame. 5.4 The signals on the common medium (also called the common highway) of a TDM system will consist of a series of pulses, the amplitudes of which are proportional to the amplitudes of the individual channels at their respective sampling instants. This is illustrated in Fig. 5 BRBRAITT, Jabalpur,

9


i FIG 5 : PAM OUTPUT SIGNALS 5.5 The original signal for each channel can be recovered at the receive end by applying gate pulses at appropriate instants and passing the signals through low pass filters. (Refer Fig. 6)

Fig. 6 : RECONSTRUCTION OF ORIGINAL SIGNAL

BRBRAITT, Jabalpur,

10


6.0 QUANTISATION 6.1

In FDM systems we convey the speech signals in their analogue electrical form. But in PCM, we convey the speech in discrete form. The sampler selects a number of points on the analogue speech signal (by sampling process) and measures their instant values. The output of the sampler is a PAM signal as shown in Fig. 3; The transmission of PAM signal will require linear amplifiers at trans and receive ends to recover distortion less signals. This type of transmission is susceptible to all the disadvantages of AM signal transmission. Therefore, in PCM systems, PAM signals are converted into digital form by using Quantization Principles. The discrete level of each sampled signal is quantified with reference to a certain specified level on an amplitude scale.

6.2

The process of measuring the numerical values of the samples and giving them a table value in a suitable scale is called "Quantising". Of course, the scales and the number of points should be so chosen that the signal could be effectively reconstructed after demodulation.

6.3

Quantising, in other words, can be defined as a process of breaking down a continuous amplitude range into a finite number of amplitude values or steps.

6.4

A sampled signal exists only at discrete times but its amplitude is drawn from a continuous range of amplitudes of an analogue signal. On this basis, an infinite number of amplitude values is possible. A suitable finite number of discrete values can be used to get an. approximation of the infinite set. The discrete value of a sample is measured by comparing it with a scale having a finite number of intervals and identifying the interval in which the sample falls. The finite number of amplitude intervals is called the "quantizing interval". Thus, quantizing means to divide the analogue signal's total amplitude range into a number of quantizing intervals and assigning a level to each intervals. For example, a 1 volt signal can be divided into 10mV ranges like 1020mV, 30-40mV and so on. The interval 10-20 mV, may be designated as level 1, 20-30 mV as level 2 etc. For the purpose of transmission,

BRBRAITT, Jabalpur,

11


these levels are given a binary code. This is called encoding. In practical systems-quantizing and encoding are a combined process. For the sake of understanding, these are treated separately. 6.5

Quantizing Process

6.5.1 Suppose we have a signal as shown in Fig. 7 which is sampled at instants a, b, c, d and e. For the sake of explanation, let us suppose that the signal has maximum amplitude of 7 volts. In order to quantize these five samples taken of the signal, let us say the total amplitude is divided into eight ranges or intervals as shown in Fig. 7. Sample (a) lies in the 5th range. Accordingly, the quantizing process will assign a binary code corresponding to this i.e. 101, Similarly codes are assigned for other samples also. Here the quantizing intervals are of the same size. This is called Linear Quantizing.

FIG. 7 : QUANTIZING-POSITIVE SIGNAL 6.5.2 Assigning an interval of 5 for sample 1, 7 for 2 etc. is the quantizing process. Giving, the assigned levels of samples, the binary code is called coding of the quantized samples. 6.5.3 Quantizing is done for both positive and negative swings. As shown in Fig.

6,

eight quantizing levels are used for each

direction

of the

analogue signal. To indicate whether a sample is negative with reference to zero or is positive with reference zero, an extra digit is BRBRAITT, Jabalpur,

12


added to the binary code. This extra digit is called the "sign bit". In Fig. 8. positive values have a sign bit of ' 1 ' and negative values have sign bit of'0'.

FIG. 8 : QUANTIZING - SIGNAL WITH + Ve & - Ve VALUES 6.6

Relation between Binary Codes and Number of levels.

6.1 Because the quantized samples are coded in binary form, the quantization intervals will be in powers of 2. If we have a 4 bit code, then we can have 2" = 16 levels. Practical PCM systems use an eight bit code with the first bit as sign bit. It means we can have 2" = 256 (128 levels in the positive direction and 128 levels in the negative direction) intervals for quantizing. 6.7

Quantization Distortion Practically in quantization we assign lower value of each interval to a sample falling in any particular interval and this value is given as

BRBRAITT, Jabalpur,

13


Table-1 : Illustration of Quantization Distortion Analogue

SignalQuantizing Interval Quantizing Level

Amplitude Range (mid value) 0-10 mv 5 mv 10-20mv 15mv 20-30 mv 25 mv 30-40 mv 35 mv 40-50 mv 45 mv

0 1 2 3 4

Binary Code 1000 1001 1010 1011 1100

If a sample has an amplitude of say 23 mv or 28 mv, in either case it will be assigned \he \eve\ "2". This Is represented in binary code 1010. When this is decoded at the receiving end, the decoder circuit on receiving a 1010 code will convert this into an analogue signal of amplitude 25 mv only. Thus the process' of quantization leads to an approximation of the input signal with the detected signal having some deviations in amplitude from the actual values. This deviation between the amplitude of samples at the transmitter and receiving ends (i.e. the difference between the actual value & the reconstructed value) gives rise to quantization distortion. 6.7.2

If V represent the step size and 'e' represents the difference in

amplitude fe' must exists between - V/2 & + V/2) between the actual signal level and its quantized equivalent then it can be proved that mean square quantizing error is equal to (V2). Thus, we see that the error depends upon the size of the step. 6.7.3

12

In linear quantization, equal step means equal degree of error for all

input amplitudes. In other words, the signal to noise ratio for weaker signals will be poorer. 6.7.4

To reduce error, we, therefore, need to reduce step size or in other

words, increase th,e number of steps in the given amplitude range. This would however, increase the transmission bandwidth because bandwidth B = fm log L. where L is the number of quantum steps and fm is the highest signal frequency. But as we knows from speech statistics that the probability of occurrence of a small amplitude is much greater than large one, it seems appropriate to provide more quantum levels (V = low value) in the small amplitude region and only a few (V = high value) in the region of higher amplitudes. In this case, provided the total number of specified levels remains unchanged, no increase in transmission bandwidth will BRBRAITT, Jabalpur,

14


be required. This will also try to bring about uniformity in signal to noise ratio at all levels

of

input

signal.

This

type

of

quantization is called non-uniform quantization. 6.7.5 In practice, non-uniform quantization is achieved using segmented quantization (also called companding). This is shown in Fig. 9 (a). In fact, there are equal number of segments for both positive and negative excursions. In order to specify the location of a sample value it is necessary to know the following : 1.

The sign of the sample (positive or negative excursion)

2.

The segment number

3.

The quantum level within the segment

As seen in Fig. 9 (b), the first two segment in each polarity are collinear, (i.e. the slope is the same in the central region) they are considered as one segment. Thus the total number of segment appear to be 13. However, for purpose of analysis all the 16 segments will be taken into account. 7.0 ENCODING BRBRAITT, Jabalpur,

15


7.1 Conversion of quantised analogue levels to binary signal is called encoding. To represent 256 steps, 8 level code is required. The eight bit code is also called an eight bit "word". The 8 bit word appears in the form P

ABC

WXYZ

Polarity bit ‘1’ Segment Code Linear encoding for + ve 'O' for - ve. in the segment The first bit gives the sign of the voltage to be coded. Next 3 bits gives the segment number. There are 8 segments for the positive voltages and 8 for negative voltages. Last 4 bits give the position in the segment. Each segment contains 16 positions. Referring to Fig. 9(b), voltage Vc will be encoded as 1 1 1 1 0101.

FIG. 9 (b) : ENCODING CURVE WITH COMPRESSION 8 BIT CODE

BRBRAITT, Jabalpur,

16


7.2

The quantization and encoding are done by a circuit called coder. The coder

converts PAM signals (i.e. after sampling) into a 8 bit binary signal. The coding is done as per Fig. 9 which shows a relationship between voltage V to be coded and equivalent binary number N. The function N = f(v) is not linear. The curve has the following characteristics. It is symmetrical about the origins. Zero level corresponds to zero voltage to be encoded. It is logarithmatic function approximated by 13 straight segments numbered 0 to 7 in positive direction and 'O' to 7 in the negative direction. However 4 segments 0, 1, 0, 1 lying between levels + vm/64 -vm/64 being colinear are taken as one segment. The voltage to be encoded corresponding to 2 ends of successive segments are in the ratio of 2. That is vm, vm/2, vm/4, vm/8, vm/16, vm/32, vm/64, vm/128 (vm being the maximum voltage). There are 128 quantification levels in the positive part of the curve and 128 in the negative part of the curve. 7.3 In a PCM system the channels are sampled one by one by applying the sampling pulsqs to the sampling gates. Refer Fig. 10. The gates open only when a pulse is applied to them and pass the analogue signals through them for the duration for which the gates remain open. Since only one gate will be activated at a given instant, a common encoding circuit is used for all channels. Here the samples are quantized and encoded. The encoded samples of all the channels and signals etc are combined in the digital combiner and transmitted.

BRBRAITT, Jabalpur,

17


7.4 The reverse process is carried out at the receiving end to retreive the original analogue signals. The digital combiner combines the encoded samples in the form of "frames". The digital separator decombines the incoming digital streams into individual frames. These frames are decoded to give the PAM (Pulse Amplitude Modulated) samples. The samples corresponding to individual channels are separated by operating the receive sample gates in the same sequence i.e. in synchronism with the transmit sample gates.

BRBRAITT, Jabalpur,

18


8.0 CONCEPT OF FRAME 8.1 In Fig. 10, the sampling pulse has a repetition rate of Ts sees and a pulse width of "St". When a sampling pulse arrives, the sampling gate remains opened during the time "St" and remains closed till the next pulse arrives. It means that a channel is activated for the duration "St". This duration, which is the width of the sampling puse, is called the "time slot" for a given channel. 8.2. Since Ts is much larger as compared to St. a number of channels can be sampled each for a duration of St within the time Ts. With reference to Fig. 10, the first sample of the first channel is taken by pulse 'a', encoded and is passed on the combiner. Then the first sample of the second channel is taken by pulse 'b' which is also encoded and passed on to the combiner, Likewise the remaining channels are also sampled sequentially and are encoded before being fed to the combiner. After the first sample of the Nth channel is taken and processed, the second sample of the first channel is taken, this process is repeated for all channels. One full set of samples for all channel taken within the duration Ts is called a "frame". Thus the set of all first samples of all channels is one frame; the set of all second samples is another frame and so on. 8.3

As already said in para 5.3.5, Ts in a 30 channel PCM system is 125

microseconds and the signalling information of all the channels is transmitted through a separate time slot. To maintain synchronization between

transmit and

receive ends, the synchronization data is transmitted through another time slot. Thus for a 30 chl PCM system, we have 32 time slots. Thus the time available per channel would be 3.9 microsecs. Thus for a 30 chl PCM system, Frame = 125 microseconds Time slot per chl = 3.9 microseconds. 8.4

Structure of Frame

8.4.1 A frame of 125 microseconds duration has 32 time slots. These slots are numbered Ts 0 to Ts 31.

BRBRAITT, Jabalpur,

19


Information for providing synchronization between trans and receive ends is passed through a separate time slot. Usually the slot Ts 0 caries the synchronizsation signals. This slot is also called Frame alignment word (FAW). The signalling informatiori is transmitted through time slot Ts 16. Ts 1 to Ts 15 are utilized for voltage signal of channels 1 to 15 respectively. Ts 17 to Ts 31 are utilized for voltage signal of channels 16 to 30 respectively. 9.0 SYNCHRONIZATION 9.1

The output of a PCM terminal will be a continuous stream of bits. At

the receiving end, the receiver has to receive the incoming stream of bits and discriminate between frames and separate channels from these. That is, the receiver has to recognise the start of each frame correctly. This operation is called frame alignment or Synchronization and is achieved by inserting a fixed digital pattern called a "Frame Alignment Word (FAW)" into the transmitted bit stream at regular intervals. The receiver looks for FAW and once it is detected, it knows that in next time slot, information for channel one will be there and so on. 9.2

The digits or bits of FAW occupy seven out of eight bits of Ts 0 in

the following pattern. Bit position of Ts 0 FAW digit value 9.3

B1 X

B2 0

0

B3 1

B4 1

B5 0

B6 1

B7

B8

1

The bit position B1 can be either ' 1 ' or '0'. However, when the

PCM system is to be linked to an international network, the B1 position is fixed at '1 ' . The FAW is transmitted in the Ts O of every alternate frame. Frame which do not contain the FAW, are used for transmitting supervisory and alarm signals. To distinguish the Ts 0 of frame carrying supervisory/alarm signals from those carrying the FAW, the B2 bit position of the former are fixed at T. The FAW and alarm signals are transmitted alternatively as shown in Table - 2.

BRBRAITT, Jabalpur,

20


TA B L E -2 Frame Numbers FO F1 F2 F3 etc

Remark B1 X X X X

B2 0 1 0 1

B3 0 Y 0 Y

B4 1 Y 1 Y

B5 1 Y 1 Y

B6 0 1 0 1

B7 1 1 1 1

B8 1 1 1 1

FAW ALARM FAW ALARM

In frames 1, 3, 5, etc, the bits B3, B4, B5 denote various types of alarms. For example, in B3 position, if Y = 1, it indicate Frame synchronisation alarm. If Y = 1 in B4, it indicates high error density alarm. When there is no alarm condition, bits B3 B4 B5 are set 0. An urgent alarm is indicated by transmitting "all ones". The code word for an urgent alarm would be of the form. X 111 1111 10.0 SIGNALLING IN PGM SYSTEMS 10.1 In a telephone network,-the signalling information is used for proper routing of a call between two subscribers, for providing certain status information like dial tone, busy tone, ring back. NU tone, metering pulses, trunk offering signal etc. All these functions are grouped under the general terms "signalling" in PCM systems. The signaling information can be transmitted in the form of DC pulses (as in step by step exchange) or multifrequency pulses (as in cross bar systems) etc. 10.2 The signalling pulses retain their amplitude for a much longer period than

the

pulses carrying speech information. It means that the signalling information is a slow varying signal in time compared to the speech signal which is fast changing in the time domain. Therefore, a signalling channel can be digitized with less number of bits than a voice channel. 10.3 In a 30 chl PCM system, time slot Ts 16 in each frame is allocated for carrying signalling information. 10.4 The

time

slot

16

of

each

frame

carries

the

signalling

data

corresponding to two VF channels only. Therefore, to cater for 30 channels, we must transmit 15 frames, each having 125 microseconds duration.

For

carrying synchronization data for all frames, one additional frame is used. Thus a group of 16 frames (each of 125 microseconds) is formed to make a

BRBRAITT, Jabalpur,

21


"multiframe". The duration of a multiframe is 2 milliseconds. The multiframe has 16 major time slots of 125 microseconds duration. Each of these (slots) frames has 32 time slots carrying, the encoded samples of all channels plus the signaling and synchronization data. Each sample has eight bits of duration 0.400 microseconds (3.9/8 = 0.488) each. The relationship between the bit duration frame and multiframe is illustrated in Fig. 11 (a) & 11 (b).

BRBRAITT, Jabalpur,

22


FIG. 11 (B) 2.048 Mb/s PCM MULTIFRAME 10.4 We have 32 time slots in a frame, each slot carries an 8 bit word. The total number of bits per frame = 32 x 8 = 256 The total number of frames per seconds is 8000 The total number of bits per second are 256 x 8000 = 2048 K/bits. Thus, a 30 chP PCM system has 2048 K bits. 10.6

Multiframe Structure

10.6.1 In the time slot 16 of FO, the first four bits (positions 1 to 4) contain the multiframe alignment signal which enables the receiver to identify a multiframe. The other four bits (no. 5 to 8) are spare. These may be used for carrying alarm signals. Time slots 16 of frames F1 to FT5 are used for carrying the signalling information. Each frame carries signalling, data for two VF channels. For instance, time slot Ts 16 of frame F1 carries the signal data for VF channel 1 in the first four bits. The next four bits are used for carrying signalling information for channel 16. Similarly, time slot Ts16 of F2 carries signalling data of chls 2 .and 17. BRBRAITT, Jabalpur,

23


Thus in multiframe structure, four signalling bits are provided for each VF channels. As each multiframe includes 16 frames, each with a sacnqtoq per sec.,.the.signalling of each channel will occur at a rate of 500 per sec.

BRBRAITT, Jabalpur,

24


DEFINITION AND DESCRIPTION OF DIGITAL HIERARCHIES 1.0

INTRODUCTION AND DEFINITION

The term “digital hierarchy” has been created when developing digital transmission systems. It was laid down when by multiplexing a certain number of PCM primary multiplexers were combined to form digital multiplexers of higher order (e.g. second-order multiplex equipments). Consequently, a digital hierarchy comprises a number of levels. Each level is assigned a specific bit rate which is formed by multiplexing digital signals, each having the bit rate of the next lower level. In CCITT Rec. G.702, the term “digital multiplex hierarchy” is defined as follows : “A series of digital multiplexes graded according to capability so that multiplexing at one level combines a defined number of digital signals, each having the digit rate prescribed for the next lower order, into a digital signal having a prescribed digit rate which is then available for further combination with other digital signals of the same rate in a digital multiplex of the next higher order”. 2.0 WHY HIERARCHIES ? 2.1

Before considering in detail the digital hierarchies under discussion we are going to recapitulate in brief, why there are several digital hierarchies instead of one only. It has always been pointed out that as far as the analogue FDM technique is concerned, the C.C.I.T.T. recommends the world wide use of the 12-channel group (secondary group). Relevant C.C.I.T.T. Recommendation exists also for channel assemblies with more than 60 channels so that with certain exceptions – there is only one world-wide hierarchy for the FDM system (although the term “hierarchy” is not used in the FDM technique).

2.2

In the digital transmission technique it was unfortunately not possible to draw up a world-wide digital hierarchy. In practice, equipment as specified in C.C.I.T.T. Recommendation G.732 and 733, they do not only differ completely in their bit rates, but also in the frame structures, in signalling, frame alignment, etc. Needless to say that, as a consequence, the higher order digital multiplexers derived from the two different PCM primary multiplexers and thus the digital hierarchies differ as well.

BRBRAITT, Jabalpur,

25


2.3

Since these two PCM primary multiplexers are available, two digital heirarchies only would have to be expected. In reality, however, two digital hierarchies with several variants are under discussion because the choice of the fundamental parameters of a digital hierarchy depends not only on the PCM primary multiplex, which forms the basic arrangement in that hierarchy, but on many other factors such as : (a)

the bit rate of the principal signal sources.

(b)

traffic demand, network topology, operational features, flexibility of the network.

(c)

time division and multiplexing plant requirements.

(d)

compatibility with analog equipment.

(e)

characteristics of the transmission media to be used at the bit rates for the various levels of the hierarchies.

Since today these factors which are essential for forming digital hierarchies vary from country to country, it is no wonder that we now have to consider more than two proposals for digital hierarchies. 3.0

DIGITAL HIERARCHIES BASED ON THE 1544 KBIT/S PCM PRIMARY MULTIPLEX EQUIPMENT

It was around 1968 that Bell labs. proposed a digital hierarchy based on the 24-channel PCM primary multiplex at the various levels of the hierarchy : Level in hierarchy

Bit rate

Trans. line

First level

1544 kbit/s

T1

Second level

6312 kbit/s

T2

Third level

46304 kbit/s

L5 (Jumbo Grp)

Fourth level

280000 kbit/s

WT4 (Wave guide)

Fifth level

568000 kbit/s

T5

BRBRAITT, Jabalpur,

26


This proposal was modified during the following years. At the end of the study period 1968/72, the following digital network hierarchy was finally proposed as given in Fig.1.

Fig. 1 Encoded FDM (Master Group) USA & Canada 3.1

For the various bit rates at the higher levels of the two proposals, different reasons have been indicated. The bit rate of 44736 kbit/s was selected to provide a flexibility point for circuit interconnection and because it was a suitable coding level for the 600 channel FDM mastergroup.

3.2

It is also an appropriate bit rate for inter-connection to radio-relay links planned for use at various frequencies.

3.3

At the same time, N.T.T. published its PCM hierarchy are concerned (1554 and 6112 kbit/s, respectively), these two proposals are identical. They differ, however, in the higher levels as shown in Fig.2.

BRBRAITT, Jabalpur,

27


Fig. 2 Encoded TDM (Japanese)

4.0

3.4

In the N.T.T. proposal the bit rate of 32064 kbit/s at the third level of the proposed hierarchy might be considered a suitable bit rate to be used on international satellite links perhaps for administrations operating different PCM primary multiplex equipments. It is also a convenient bit rate for encoding the standardized 300-channel FDM mastergroup. Delta modulation and differential PCM for 4 MHz visual telephone are also suitable for this bit rate. Transmission of 32064 kbit/s via a special symmetrical cable of new design is also possible.

3.5

The above fact shows that the differing bit rates of the third level indicated in the two hierarchy proposals can, therefore, be justified by technical arguments. As far as the differing bit rates of the fourth level are concerned, only a few technical reasons are included in the two proposal. In both cases coaxial cables are used as a transmission medium so that the medium does not call for different bit rates.

3.6

Moreover, it seems that at present the specifications of the fourth level (and higher ones) in the two proposed hierarchies is not yet considered so urgent. For the time being the third level seems to be more important.

3.7

The C.C.I.T.T. faced with this situation has reached finally the solution which is covered by CCITT recommendation G.752 as one can see from this recommendation, two different hierarchical levels are existing in the third level of this hierarchy, namely 32064 kbits/s and 44736 kbit/s respectively. Higher level have not been specified so far. DIGITAL HIERARCHY BASED ON THE 2048 KBIT/S PCM PRIMARY MULTIPLEX EQUIPMENT For this digital hierarchy, two specifications have at present been laid down only for the first level at 2048 kbit/s and for the second level at 8448 kbit/s. As for the higher levels, the situation is just contrary to that existing in the case of digital hierarchies derived from 1544 kbit/s primary multiplex, i.e. general agreement has more or less been reached on the fourth level having a bit rate of 139264 kbit/s. 5th order system where bit rate of 565 Mb/s have also been planned now.

4.1

The critical point in this hierarchy is whether or not the third level at 34368 kbit/s should exist.

BRBRAITT, Jabalpur,

28


4.2

The C.C.I.T.T. has agreed after long discussions on the following (Recommendation G.751) “that there should be a 4th order bit rate of 139264 kbit/s in the digital hierarchy which is based on the 2nd order bit rate of 8448 kbit/s”. There should be two methods of achieving the 4th order bit rate : Method 1 by using a 3rd order bit rate of 34368 kbit/s in the digital hierarchy. Method 2 by directly multiplexing sixteen digital signals at 8448 kbit/s. The digital signals at the bit rate of 139264 kbit/s obtained by these two methods should be identical. The existence of the above two methods implies that the use of the bit rate of 34368 kbit/s should not be imposed on an Administration that does not wish to realize the corresponding equipment.

4.3

In accordance with the above two methods the following realizations of digital multiplex equipments using positive justification are recommended : Method 1 : Realization by separate digital multiplex equipments : one type which operates at 34368 kbit/s and multiplexes four digital signals at 8448 kbit/s; the other type which operates at 139264 kbit/s and multiplexes four digital signals at 34368 kbit/s. Method 2 : Realization by a single digital multiplex equipment which operates at 139264 kbit/s and multiplexes sixteen digital signals at 8448 kbit/s. Method 1 has been put into practice.

4.4

Where the fifth level is concerned, some preliminary proposals (e.g. 565148 kbit/s) have been submitted which were not discussed in detail. Therefore, the present structure of this digital hierarchy is as given in Fig.3.

139.264

Fig. 3 Encoded TDM (European) BRBRAITT, Jabalpur,

29


5.0

Most of the administrations favour the specification of a third level at 34368 kbit/s, mainly as a suitable flexibility point for the operation of the network and as an adequate bit rate for digital line systems which are to be set up either on new cables (screened symmetrical or micro-coaxial cables) or an radiorelay links. Other administrations do not consider the specification of a third level to be advantageous for their networks. On the contrary they regard it to be more economical to go directly from the second level at 8448 kbit/s so the fourth level at 139264 kbit/s, is also achieved by multiplexing four digital signals at 34368 kbit/s, each of which is obtained by multiplexing first four digital signals at 8448 kbit/s. However, this is a matter of internal multiplexing only, i.e. digital multiplex equipment of this type has no external input or output at 34368 kbit/s. All administrations interested in the third level at 34368 kbit/s would thus be offered the possibility of using this level. Their digital multiplex equipment which multiplexes in the same way each of the four digital signals at 8448 kbit/s has to provide external outputs for the resulting signal at 34368 kbit/s. The digital multiplex equipment which multiplexes each of the four digital signals at 34368 kbit/s has to provide four inputs for these bit rates and one output for the resulting bit rate of 139264 kbit/s.

5.1

Outlook The above context indicates that at the moment the discussion of digital hierarchies is still underway and is mainly concentrated on the third and fourth levels. Although certain trends are evident the specification of these and higher levels will take some time. In the interest of a comprehensive specification of the digital hierarchies to be drawn up as soon as possible, it is to be hoped that all parties concerned perform their studies with high priority. All digital multiplexes and hierarchies proposed till date are operating in an asynchronous mode (positive justification, “positive stuffing”, bit-interleaved). It is likely that in the future, synchronous digital multiplex equipment has to be considered when setting up digital hierarchies. For various digital line systems being developed in many countries non-hierarchical bit rates have provisionally been adopted with due regard to the characteristics of the transmission media used. These non-hierarchical bit rates for digital line systems have also to be born in mind when defining the digital hierarchies and may affect the hierarchical bit rates.

BRBRAITT, Jabalpur,

30


DIGITAL MULTIPLEXING HIERARCHY 1. INTRODUCTION The functions of digital multiplex equipment are to combine a defined integral number of digital input signals (called tributaries) at a defined digit rate by time division multiplexing and also to carry out the reverse process (demultiplexing). In analogue system, multiplex equipment uses F.D.M. to assemble individual channels into groups, super group etc. Similarly, in digital systems, hierarchical levels have been defined using T.D.M. and are identified by their digit rate measured in bit/sec. Bit rate Mbit/sec. 2.048 8.448 34.368 139.264 2.0 MULTIPLEXING OF DIGITAL SIGNALS

No. of channels 30 120 480 1920

The digital signals which are to be multiplexed may be synchronous to one clock (called master clock) or they may not be synchronous (called asynchronous signals). 3.0

MULTIPLEXING OF SYNCHRONOUS DIGITAL SIGNALS

The various tributary bit streams are synchronous and operate at the same rate defined as T bit/sec. To multiplex ‘n’ such tributaries the rate of multiplex output should be nT bit/s. The method adopted for multiplexing such n signals into one stream may be as follows : (i)

Block interleaving :

Bunch of information taken at a time from each tributary and fed to main multiplex output stream. The memory required will be very large. (ii)

Bit interleaving :

A bit of information taken at time from each tributary and fed to main multiplex output stream in cyclic order, a very small memory is required. At the demultiplex end, it is necessary to recognise which bit of information belongs to which tributary. This could be achieved by transmitting a fixed code after a fixed number of information bits called “frame”. The fixed code is called frame

BRBRAITT, Jabalpur,

31


alignment signal. It is recognised first and received frame of information is aligned to this fixed code. This method of multiplexing is easy but not reliable. If any deviation in nominal bit rate of a tributary occurs, it will cause loss of time slot and hence loss of information.

BRBRAITT, Jabalpur,

32


4.0

MULTIPLEXING OF ASYNCHRONOUS SIGNAL Here, various tributaries operate at different bit rates.

Two signals are asynchronous at their corresponding significant instant occur at nominally the same rate, any variation in rate being constrained within specified limits. When nominal bit rate of tributaries are within specified limit. It is necessary to synchronize the tributary signal with a common nominal bit rate of multiplexer derived from timing generator of multiplexer. The synchronization is done in such a way that there is no loss of information. The process adopted for such synchronization is called “Pulse stuffing” or justification. Justification is a process of changing the rate of digital signals in a controlled manner. There are three types of justification processes : (a) Positive justification : Common synchronization bit rate offered at each tributary is higher than the bit rate of individual tributary. (b) Positive-negative justification : Common synchronization bit rate offers is equal to the nominal value. (c) Negative justification : Common synchronization bit rate offered is less than the nominal value. Fig. 1(a) shows a configuration where the outputs of two PCM transmitters A&B are to be multiplexed in the combiner. If A and B are synchronous, they can be easily multiplexed by the combiner as shown in Fig. 1(b). Generally, however, A&B are clocked by separate clock sources of asynchronous. In this case multiplexing is not successively accomplished simply by the use of combiner owing to the occurrence of pulse phase fluctuations and/or pulse amplitude superposition as can be seen in Fig.1(c). 5.0 RETIMING ASYNCHRONOUS SIGNALS BY JUSTIFICATION Figure 2 shows a system for explaining the principle of the multiplexer for successfully multiplexing plural asynchronous signals. The waveforms appearing at various points in Fig.2 are shown in Fig.3. An asynch. input pulse train A is written into MEM I comprising several elements. The writing pulse train C whose bit rate is f is extracted from A at a clock extraction (CLK EXT I). On the other hand, the written information is read out of MEM I with a sufficient phase lag with respect to time of writing in. Through an inhibit gate (INH GATE I), the reading pulse train D is obtained by dividing the output bit rate nf (1+ Δ) of a common clock generator (CLK GEN) at a bit rate divider (DIV 1). n Δ

-

BRBRAITT, Jabalpur,

no. of asynch. signals to be multiplexed. clock increase rate.

33


As the bit rate of the reading pulse train D is set at (f+ Δ f) which is higher than any value of f, the time of read out (D) gradually approaches that of write in ©. The phase difference between C&D is monitored by a phase comparator of COMP I and just before the difference reaches zero, a pulse is applied to the inhibit input of INH GATE I from a control circuit (CONT I) to inhibit the gate. At this moment, with one bit of the reading pulse train D being removed, the reading operation pauses and an information less pulse (or justification pulse) is inserted into the read out pulse train E. the time of read out (D) at the same time is again set to a sufficient lag with respect to time write in (G). As all the signals read out of the respective memories are now retimed by timing pulses derived from the common CLK GEN, they are now easily multiplexed as F in Fig.3 at the combiner (COMB). The information pulses inserted into E (those hatched in Fig. 3) and this sort of retiming method are respectively called “justification pulses” and “justification”. The information whether or not justification has been performed, is inserted into F and COMB and transmitted to the receiving side. 6.0

RECOVERING ORIGINAL SIGNALS BY DEJUSTIFICATION

The justification pulses have to be removed at the receiving side to perfectly recover the original signals. This operation is called “dejustification”. The transmitted pulse train F from the line is received and demultiplexed at distributor (DIST). One of the demultiplexed signal E that corresponds to A, is written into memory MEM 2. The writing pulse train G whose bit rate is Δis obtained through an ingibit grate (INH GATE 2) by dividing the output bit rate nf(1+ Δ f) of clock extractor (CLK EXT2). On the other hand, the written information is read out of MEM 2 with a slight phase lag with respect to the time of write in. The reading pulse train H, whose bit rate is f, is applied from voltage controlled oscillator (VCO). As the bit rate of the reading pulse train H is lower than that of the writing pulse train G, the time of read out (H) gradually drifts away from that of write in (G). Just before a justification pulse in E (ONE of these hatched in Fig.3) is written into MEM 2, the information, telling that the justification has been performed is applied from DIST to a control circuit (CONT 2). Then a pulse is applied to the inhibiting input of INH GATE 2 from CONT 2 to inhibit the gate.

BRBRAITT, Jabalpur,

34


At this moment, with one bit of the writing pulse train G being removed, the writing operation pauses and the justification pulse is removed or dejustified. At the same time, the time of read out (H) again set to be very close to the time of write in (G). As the reading operation does not pause, the original signal is recovered as ‘A’. The phase difference between G and H is monitored by a phase comparator (COMP 2), and the low frequency components of the output voltage of COMP 2 are applied to VCO through a low pass filter (LPF). Thus, the jitter introduced due to dejustification into the read out pulse train ‘A’ is sufficiently suppressed. The loop formed by VCO, COMP and LPF is called a “Phase controlled loop”. Figure 4 gives the frame structure for 34 Mbits/sec system. 7.0

JUSTIFICATION CONTROL SIGNAL

Justification control signal indicates at demultiplexer the presence of justifiable bit in the frame. To avoid errors present in the justification control bit, more than one bit is transmitted as control bit and majority decision is taken at demultiplexer. Normally 3 or 5 bits (3 bits in case of 8 and 34 Mbits systems and 5 bits in 140M bits system) are transmitted per tributary per frame as justification control bits and 2 or 3 bits present at demultiplexer out of 3 or 5 bits transmitted are taken as majority decision and it is assumed that justifiable bit is present in the frame. These 3 or 5 bits of justification control bits per tributary per frame are distributed in the frame. Two or three digital errors are required to cause false information of justification (loss of one digit or addition of one digit) which results in a loss of frame alignment in lower hierarchical levels.

BRBRAITT, Jabalpur,

35

FIG. 4


HIGHER ORDER MULTIPLEXING INTRODUCTION Time Division Multiplexing (TDM) is essentially a process that collects the information of a number of sources and transmits this information via a common transmission medium to an equal number of destination. Broadly distinguishing "Primary" TDM systems - 30 channel PCM from "Higher Order" TDM systems, it is seen that in primary TDM systems, the information sources to be multiplexed are "Analog". The values of their power vary continuously and before multiplexing they are brought in binary form by means of a sampling and coding process. In higher order TDM systems, to be discussed in this handout. The input signals are already in the binary form.

TIME DIVISION MULTIPLEXING In Time Division Multiplexing, first the message signals are reduced to a digital format, then they are multiplexed with other digital signals by interleaving them in the time domain.

The Interleaving Process Generally, a Digital Multiplexer can be considered as a parallel to serial converter. It accepts a set of inputs (or messages often called tributaries) applied in parallel and interfaces the inputs into a single output signal having specific time intervals allocated serially to each message. As we know that the channel messages in the case of PCM signals, occur as a sequence of fixed-length code words. This gives rise to two different multiplexing procedures, namely, (i) Word interleaved, (ii) Bit interleaved. If the channel Time Slot is long enough to accommodate one complete code word (a group of bits), the multiplexed output signal is termed word interleaved. Alternatively, each channel code may be scanned one binary digit (bit) at a time to produce Bit Interleaved multiplexed signal. BRBRAITT, Jabalpur,

36


Part of Fig. 1

Fig. 1 BRBRAITT, Jabalpur,

37

PCM Principles, Digital MUX & Higher Order MUX The Basic Principles of Time Division Multiplexing

BRBRAITT, Jabalpur,

38


Timing of all operations within a multiplexer is controlled by a highly stable oscillator called the Master Clock. Typically, the frequency reference used within the oscillator is a quartz crystal of tolerance in the range 10 to

50 ppm.

If all the channel signals are derived from the Same Master Clock, there will be a fixed phase relationship between them, and they are termed Synchronous Multiplexing . Such signals are straight forward. For example, in the case of word interleaving, since the channel word rate always remains equivalent to the information time-slot rate, no allowance for clock tolerances need be made. In case different clocks are involved in deriving the various channel signals, the multiplexer is said to be Asynchronous. As illustrated in Fig. 3 the multiplex process in Higher Order systems can be represented by a rotating switch. During one rotation of the switch from every source, one bit is collected and consequently transmitted (Bit inerleaving). Of course, in doing so we can only transmit a part of the original bit-period. But with adequate retiming circuits at the receiver side. We can easily re-establish the original durations. One complete cycle of the rotating switch is called a Time Frame. A frame consists of a sequence of bits in a constant repeating tributary order. Three pertinent questions arise at this stage : 1st question : How can I make both switches run at the same speed ? Because if they do not run in the same speed, it is impossible to distribute the received data to any destination, let alone the right one. Answer : Synchronisation of Multiplexer and Demultiplexer. 2nd question : If both switches run at the same speed, how can I force the Multiplexer and Demultiplexer to assume the same position constantly, because if the two switches select different tributaries at both the side, the confusion will be complete. Answer : Frame alignment.

BRBRAITT, Jabalpur,

39


Fig. 2 Word & Bit interleaving

Fig. 3 Time Division Multiplexing in Higher Order System BRBRAITT, Jabalpur,

40


3rd question : If the multiplexer and demultiplexer are in synchronism and if there is frame alignment how can one achieve a correct time matching between the tributaries and the multiplexer/demultiplexer ? Because it is very unlikely that the bit rate of the tributaries are exactly the same as the selecting speed of the switches. Moreover, even in the case of same bit rates there might be a variation. Plesiochronous Signals Signals whose clock can vary independent of one another but the range of variation is restricted within certain specified limits. At Delhi, the 4 incoming tributaries are to be multiplexed. Here, the clock speed is 2.048 MHz but the variation is restricted within + or +/- 50 ppm.

Fig. 4

HIGHER ORDER MULTIPLEX SYSTEMS Fig. 5 gives the digital hierarchy for higher order multiplex system as suggested by CCITT.

BRBRAITT, Jabalpur,

41


The Fig. 6 depicts the formation of plesiochronous second order TDM that combines 4 plesiochronous channels each of bit rate = 2.048 Mb/s (+ or +/- 30 ppm).

BRBRAITT, Jabalpur,

42


Fig. 5 Digital Hierarchy Suggested by CCITT

Fig. 6

BRBRAITT, Jabalpur,

43


A frame format can be defined such that 2.048 Mb/s of information digits, plus some control digits, including those allocated for frame alignment purposes, may be contained within the 2.112 Mb/s stream (8.448/4). In this case, provided that the channel and Multiplex clocks are absolutely accurate, or are synchronized to each other, the ratio of the information-to-control digits 'n' is given by n 

2.048  32.1 2.112  2.048

Frame Alignment How MUX and DEMUX select the same tributary at any moment ? The solution to this problem could be found in adding one extra selector position that can be used to transmit a "Position Mark" as shown in Fig. 7. This Position Mark to be injected at the multiplexer side should be a signal that can easily be detected at the demultiplexer side. In TDM systems, where already binary signals are multiplexed, this "Pilot Signal" has the shape of a binary bit pattern of a well-defined length. This bit pattern consists of a sequence of ones and zeros designed such that the demultiplexer easily can recognize it out of the incoming bit stream. As a custom, this "Pilot Signal" is injected at the beginning of a new cycle, or in other words : at the beginning of a new Time Frame. Because of its job to tell the demultiplexer about the start of a new Time Frame, the "Pilot Signal" is called "Frame Alignment Signal". Bunched words (first 10 bits in second order multiplex frame) is preferred to distributed bits to prevent imitation by any other bit sequence. The probability of imitation is 2m, where m is the number of bits in frame alignment word. The sequence used in Second and Third Order MUX is 1111010000. Justification In general, incoming tributaries have independent clocks. In that case, it is inevitable that clock rate of a tributary and the (divided) clock rate of the multiplexer BRBRAITT, Jabalpur,

44


(in second order TDM, it is 8448/4 = 2112 KHz) are not the same. Without any precautions, the result will be Slip. The effect of the slip is illustrated in Fig. 9.

BRBRAITT, Jabalpur,

45


Fig. 7 The Frame Alignment Principle

BRBRAITT, Jabalpur,

46

PCM Principles, Digital MUX & Higher Order MUX Fig. 8

848

Example of a Higher Order TDM Time Frame

Fig. 9 Non-Synchronized Information

BRBRAITT, Jabalpur,

47


If the incoming tributary bit rate is higher than multiplexer clock rate, some bits are not transmitted [Fig. 9(A)]. If the incoming bit-rate is lower than multiplexer clock rate, some bits are selected twice [Fig. 9(B)]. Is it possible to avoid Slip and yet be able to multiplex non-synchronized tributaries ? Yes. In the higher order TDM systems recommended by CCITT, precautions have been taken that there will be no loss of information, neither there will be any bit transmitted two times.

Fig. 9(A) Incoming Bit Rate Too High

Fig. 9(B) Incoming Bit Rate Too Low

BRBRAITT, Jabalpur,

48


In these systems, there will be introduced some occasional phase-distortion called jitter. But this jitter will be kept within very low limits and will hardly be of any influence on the quality of the demultiplexed signals. The problems of slip can be solved by a process called "Justification" or "Bitstuffing". The justification process covers three actions. These actions are described with the help of a functional diagram : the action (A), (B) and (C) of Fig. 10. Note : Fig. 10 is an example of a second order TDM system. Four bit stream of 2048 Kb/s are multiplexed. The resulting bit stream of 8448 Kb/s can be thought of being composed as follows :- Per tributary Nominal bit rate

:

Justification digits

:

Justification control digits :

2048 Kb/s 4 Kb/s used to allow overspeed 30 Kb/s

Sub total

:

2082 Kb/s

Four tributaries

:

4 x 2082 Kb/s

=

8328 Kb/s

Frame alignment information

120 Kb/s

Outgoing bit rate (Total) :

8448 Kb/s

Action A : Expanding the transmission capacity. The transmission capacity per tributary in the outgoing signal (which is the same for all tributaries) is made higher than the maximum tolerated bit rate. In doing so, you would expect a slip phenomenon because some bits should be transmitted twice. But the extra time slots are only used, if necessary. Instead of transmitting twice, the extra bits called justifying Digits are "used" or are kept "idle". Of course, we also must tell the demultiplexer whether the justifying digits are "used" or are "idle". So, we also add some time slots for transmitting "Justification Information" called the Justification Control Bits. BRBRAITT, Jabalpur,

49


Fig. 10 Equipment Functions of the Justification Process (2nd Order TDM System)

BRBRAITT, Jabalpur,

50


Action B : At the demultiplexer side, the received bit-rate is reduced to the original bit rate. The contents of the justifying digits have to be restituted when they contain "real" information. When the time slot for tributary information contain "idle" bits, these bits are dropped. This is the real justification process, whether the justifying digits contain real or idle information is analysed in the receiver by observing the justification control bits. Action C : To compensate the "lack of time" when the demultiplexer drops justification time slots, the received tributary bit rate is averaged in time. Instead of sudden phase jumps, the clock of the receiver tributary is gradually adopted to the real number of bits available per unit of time. Because of the "uncertainty" of the justification moments, some small jitter is introduced. Now, we will explain successively the three justification actions A, B and C from Fig. 10. Action (A) is the circuitry that provides the extra transmission capacity. The need for justification is monitored constantly and the test results used for the justification control. At the same time, test results is transmitted to the distant station to inform the demultiplexer whether justification has taken place or not. In the practical TDM system of Fig. 10, a rotating switch is used with 848 positions. Per tributary we have 212 position in one complete cycle to transmit the information. Per cycle one justification digit with a well-defined position is reserved. This position chosen is 161 at about three quarters of a cycle as illustrated in Fig. 11(a). To inform the demux tributary about Justification Decisions, we need also extra capacity for justification control. 3 control digits (Justification control bits) are provided per tributary input to indicate the Demux whether the justifiable digit slot in that frame carries information or can be ignored. As illustrated in Fig. 11(b), the time slots 54, 107 and 160 are used for this. Majority decision is followed in case of BRBRAITT, Jabalpur,

51


justification control digits to decide whether the justifiable digits slot carries information or dummy bit results based on majority decision are given below in the Table.

Fig. 11(a) Position of the Justifying Digit in a Tributary Cycle (2nd Order)

Fig. 11(b) Position of the Justification Control Bit in a Tributary Cycle

Justification control bit Majority : Decision of the justification control monitor

54

107

160

Result analysis

54

1 1 1 0

1 1 0 1

1 0 1 1

Position 161 is idle

0 0 0 1

107 160 0 0 1 0

0 1 0 0

Result analysis Position 161 contains information

Justification control bit (JCBs) are distributed across the frame because (i)

Separating these bits as much as possible, errors in redundant stuffing JCBs are more likely to be independent. If the JCBs are too close

BRBRAITT, Jabalpur,

52


(ii)

together and digital burst errors are prevalent, the redundant encoding is of little use. Distributing JCBs, the irregularity of information flow is minimised and clock recovery is simplified.

BRBRAITT, Jabalpur,

53

Pcm Principles

Recommend Documents