Lead Lag Handout

EE 3CL4, §6 1/63 Tim Davidson Compensators Lead compensation Design via Root Locus Lead Compensator example

Cascade compensation and steady-state errors Lag Compensation Design via Root Locus Lag compensator example

EE3CL4: Introduction to Linear Control Systems Section 6: Design of Lead and Lag Controllers using Root Locus Tim Davidson McMaster University University

Prop. vs Lead vs Lag Concluding Insights

Winter 2015

EE 3CL4, §6 2/63

Outline

Tim Davidson Compensators Lead compensation Design via Root Locus Lead Compensator example



1 Compensators 2 Lead compensation

Design via Root Locus Lead Compensator example steady-state errors 3 Cascade compensation and steady-state 4 Lag Compensation

Design via Root Locus Lag compensator example Prop.. vs Lead Lead vs Lag Lag 5 Prop 6 Concluding Insights

EE 3CL4, §6 4/63

Compensators

Tim Davidson Compensators Lead compensation

•

Design via Root Locus Lead Compensator example

Cascade compensation and steady-state errors

•

Early in the course we provided provided some useful guidelines guidelines regarding the relationships between the pole positions of a system and certain aspects of its performance Using root locus techniques, we have seen how the pole positions of a closed loop can be adjusted by varying a parameter

Lag Compensation Design via Root Locus Lag compensator example

Prop. vs Lead vs Lag

• What happens if we are unable to obtain that performance that we want by doing this? •

Concluding Insights •

•

Ask ourselves ourselves whether this is really really the performance performance that we want Ask whether we can change the system, say by buying different components seek to compensate compensate for for the undesirab undesirable le aspects of the process

EE 3CL4, §6 5/63

Cascade compensation



• Usually, the plant is a physical process • If commands and measurements are made electrically, •


compensator is often an electric circuit General form of the compensator is

M K c + z i i ) c i =1 (s + G c c (s ) = n + p j ) j =1 (s +

Concluding Insights

• Therefore, the cascade compensator adds open loop •

poles and open loop zeros These will change the shape of the root locus

EE 3CL4, §6 6/63

Compensator Compe nsator design




•

Where should should we put new poles and zeros to achieve achieve desired performance?

• That is the art of compensator design • We will consider first order compensator compensators s of the form

˜c c (1 + s /z ) K c K + z ) c (s + ˜c c = K c c z /p G c = , where K c (s ) = (s + + p ) (1 + s /p ) • •

with the pole p in in the left half plane and the zero, z in in the left half plane, too

− −

• For reasons that will soon become clear when |z | < |p |: phase lead network •

EE 3CL4, §6 8/63

Lead compensation



K c (s + z ) G c (s ) = (s + p ) with z < p . That is, zero closer to origin than pole

|| ||



Let p = 1/τ p and z = 1 /(αlead τ p ). Since z < p , αlead > 1. ˜c = K c z /p = K c /αlead . Then Define K

˜c (1 + αlead τ p s ) K K c (s + z ) = G c (s ) = (s + p ) (1 + τ p s )



Lead compensation ˜

With z < p , α lead > 1, G c (s ) =

|| ||

K c (s +z ) (s +p )

=

K c (1+αlead τ p s ) (1+τ p s )

• Frequency response:

˜c (1 + j ω αlead τ p ) K G c ( j ω ) = (1 + j ωτ p )

• Bode diagram (in the figure, K 1 = K ˜c )



• Between ω = z and ω = p , |G c ( j ω)| ≈ K ˜c ωαlead τ p • What kind of operator has a frequency response with magnitude proportional to ω ? Differentiator

EE 3CL4, §6 10/63 Tim Davidson

A passive phase lead network

Compensators Lead compensation Design via Root Locus Lead Compensator example



Homework: Show that characteristic

V 2 (s ) has V 1 (s )

the phase lead


Active lead and lag networks




Here’s an example of an active network architecture.

EE 3CL4, §6 12/63

Principles of Lead design via Root Locus


Cascade compensation and steady-state errors Lag Compensation Design via Root Locus

• The compensator adds poles and zeros to the P (s ) in the root locus procedure.

• Hence we can change the shape of the root locus. • If we can capture desirable performance in terms of •

positions of closed loop poles then compensator design problem reduces to: •

Lag compensator example

Prop. vs Lead vs Lag •

Concluding Insights

changing the shape of the root locus so that these desired closed-loop pole positions appear on the root locus finding the gain that places the closed-loop pole positions at their desired positions

• What tools do we have to do this? • Phase criterion and magnitude criterion, respectively

EE 3CL4, §6 13/63

Root Locus Principles



• The point s is on the root locus of P (s ) if 1 + KP (s ) = 0. Q • In first order compensator design with G (s ) = Q ( (++) ) 0

0

and G c =

K c (s +z ) (s +p ) ,

we have P (s ) =

QM (s +z ) Qi =1 (s +z i ) (s +p ) j n =1 (s +p j )

n j =1

s z i s p j

and

K = K c K G . We will restrict attention to the case of K > 0

• Phase cond. s is on root locus if ∠P (s ) = 180 0

M 

(angle from

i =1

0

−z to s ) −

+ (angle from


M i =1

K G

i

0

n 

(angle from

j =1

◦

+ k 360 : ◦

−p to s ) j

0

−z to s ) − (angle from −p to s ) 0

0

◦

= 180 + k 360

◦

• Mag. cond. If s satisfies phase condition, the gain that puts a closed-loop pole at s is K = 1 /|P (s )|:  (dist from −p to s ) = (dist from −p to s ) K =  × (dist from −z to s ) (dist from −z to s ) 0

0

n j 1 M i 1

0

j

0

0

i

0

0

EE 3CL4, §6 14/63

RL design: Basic procedure

Tim Davidson

1

Translate design specifications into desired positions of dominant poles

2

Sketch root locus of uncompensated system to see if desired positions can be achieved


3

If not, choose the positions of the pole and zero of the compensator so that the desired positions lie on the root locus (phase criterion), if that is possible

Lag Compensation

4

Evaluate the gain required to put the poles there (magnitude criterion)

5

Evaluate the total system gain so that the steady-state error constants can be determined

6

If the steady state error constants are not satisfactory, repeat


Design via Root Locus Lag compensator example


This procedure enables relatively straightforward design of systems with specifications in terms of rise time, settling time, and overshoot; i.e., the transient response. For systems with steady-state error specifications, Bode (and

EE 3CL4, §6 15/63

Lead Comp. example




Consider a case with G (s ) = s (s 1+2) and H (s ) = 1. Design a lead compensator to achieve:

• damping coefficient ζ ≈ 0.45 and • velocity error constant K = lim sG (s )G (s ) > 20 • swift transient response (small settling time) v

s →0

c

What to do?

• Can we achieve this with proportional control? • If not we will attempt lead control

EE 3CL4, §6 16/63

Attempt prop. control




1 s s 2

• Sketch root locus of ( + ) • Sketch rays of angle cos (0.45) ≈ 60 to neg. real axis • Are there intersections? Yes • If so, what is the corresponding value of K = K K ? 1

−

◦

P G

• •

K = d 1 d 2 = 5 Does that K generate a large enough velocity error const.? No, K v = 2 .5 :( Do the closed-loop poles have responses that decay




Prop. control, step response

EE 3CL4, §6 18/63

Lead compensated design




• Plot poles of G (s ). • • • •

Where should the closed-loop poles be? cos 1 (0.45) 60 Note that the settling time is not specified; it only needs to be small. This provides design flexibility. However, we need a large K v which will require large gain. Need desired positions far from open loop poles. Let’s start with desired roots at 4 j 8 This pair has T s = 1s and ω n = 42 + 82 8.9 −

−√ ±

≈

≈

◦


Lead Comp. example




• Now where to put the zero and pole? (Centroid denoted c ) • Rule of thumb: put zero under desired root, or just to the left • Determine position of the pole using angle criterion   angles from OL zeros − angles from OL poles = 180 ∼ 90 − (116 + 104 + θ ) = 180 =⇒ θ ≈ 50 a

p

p

◦


Lead Comp. example




• Gain of compensated system:

d 1 d 2 d p Prod. dist. from open-loop poles = d z Prod. dist. from open-loop zeros 8.94(8.25)(10.54) 8

≈

≈ 97.1

• Hence compensated open loop: G (s )G (s ) = ( + .)(( ++ ). • Velocity constant: K = lim sG (s )G (s ) ≈ 17.9 :( c

v

s →0

c

97 1 s 4 s s 2 s 10 86)

EE 3CL4, §6 21/63

What to do now?




• We tried hard, but did not achieve the design specs • Let’s go back and re-examine our choices • Zero position of compensator was chosen via rule of thumb

• Can we do better?

Yes, but two parameter design becomes trickier.

• What were other choices that we made? • We chose desired poles to be of magnitude ωn ≈ 8.9 • We could choose them to be further away (faster transient response)

• By how much? • Show that when desired poles have ωn = 10 as well as the required ζ 0.45, then the choice of z 4.47, p 12.5 and K C 125 results in K v 22.3

≈

≈

≈

≈

≈


Root Locus, new lead comp.




Centroid denoted c a

EE 3CL4, §6 23/63

New lead comp.

Tim Davidson

Prop.-contr.

Lead contr.

5

125(s +4.47) (s +12.5)

OL TF, G C (s )G (s )

5 s (s +2)

125(s +4.47) 1 (s +12.5) s (s +2)

Y (s ) R (s )

5 s (s +2)+5

125(s +4.47) s (s +2)(s +12.5)+125(s +4.47)

−1 ± j 2 ∞, ∞

−4.47 ± j 8.94, −5.59 −4.47, ∞, ∞ ( + . ) . − + . + . +




Controller, G C (s )

CL TF,

CL poles CL zeros CL TF, again

5 s 2 +2s +5

131 1 0 013s s 2 8 94s 100

1 71 s 5 59

• Complex conjugate poles still dominate • Closed-loop zero at -4.47 (which is also an open-loop

zero) reduces impact of closed-loop pole at -5.59; see also slide 48 of Section 3: Fundamentals of Feedback




New lead comp., ramp response




New lead comp., ramp response, detail


New lead comp., step response




Note faster settling time than prop. controlled loop, However, the CL zero has increased the overshoot a little Perhaps we should go back and re-design for ζ

≈ 0.40

EE 3CL4, §6 27/63

Outcomes

Tim Davidson Compensators

• Root locus approach to phase lead design was

reasonably successful in terms of putting dominant poles in desired positions; e.g., in terms of ζ and ω n

Lead compensation Design via Root Locus Lead Compensator example

Cascade compensation and steady-state errors Lag Compensation

• We did this by positioning the pole and zero of the lead compensator so as to change the shape of the root locus

• However, root locus approach does not provide

independent control over steady-state error constants (details upcoming)



•

That said, since lead compensators reduce the DC gain (they resemble differentiators), they are not normally used to control steady-state error.

• The goal of our lag compensator design will be to

increase the steady-state error constants, without moving the other poles too far

EE 3CL4, §6 29/63

Cascade compensation



•

Throughout this lecture, and all the discussion on cascade compensation, we will consider the case in which H (s ) = 1.

•

We will consider first order compensators of the form K (s + z ) G c (s ) = (s + p )


−p , and the zero, −z , both in the left half plane • when |z | < |p |: phase lead network • when |z | > |p |: phase lag network with the pole,

EE 3CL4, §6 30/63

Steady-state errors




If closed loop stable, steady state error for input R (s ): R (s ) e ss = lim e (t ) = lim s t s 0 1 + G C (s )G (s ) →∞

Let G (s ) =

Q K G i (s +z i ) Q j (s +p j )

→

and consider G C (s ) =

K C (s +z ) (s +p )

• Consider the case in which G (s ) is a type-0 system. •

Steady state error due to a step r (t ) = Au (t ): A e ss = 1+K , where posn

 K C z K G i z i  K posn = G C (0)G (0) =

Concluding Insights

p

j p j

• Note that for a lead compensator, z /p < 1, • So lead compensation may degrade steady-state error performance

EE 3CL4, §6 31/63

Steady-state error




• Now, consider the case in which G (s ) is a type-1 Q system, G (s ) =

K G Q i (s +z i ) s j (s +p j )

• Steady-state error due to a ramp r (t ) = At : e ss = A/K v , where the velocity constant is K v =

 K C z K G i z i  lim sG c (s )G (s ) =

s →0

p

j p j

• Once again, lead compensation may degrade steady-state error performance

• Is there a way to increase the value of these error constants while leaving the closed loop poles in essentially the same place as they were in an uncompensated system? Perhaps z > p ?

|| ||

EE 3CL4, §6 33/63

Lag compensation



K c (s + z ) G c (s ) = (s + p ) with z > p . That is, pole closer to origin than zero

|| ||



Let z = 1/τ z and p = 1/(αlag τ z ). Since z > p , αlag > 1. ˜c = K c z /p = K c αlag . Then Define K

˜c (1 + τ z s ) K c (s + z ) K G c (s ) = = (s + p ) (1 + τ s )

EE 3CL4, §6 34/63

Frequency response

Tim Davidson Compensators

˜C (1 + j ωτ z ) K G c ( j ω ) = (1 + j ωα lag τ z )




Magnitude

• Low frequency gain: K ˜C • Corner freq. in denominator at ωp = p = 1/(αlagτ z ) • Corner freq. in numerator at ωz = z = 1/τ z • ωp < ωz • High frequency gain: K ˜C /αlag = K C

Phase

• φ(ω) = atan(ωτ z ) − atan(αlagωτ z ) • At low frequency: φ(ω) = 0 • At high frequency: φ(ω) = 0 • In between: negative, with max. lag at ω = √ zp


˜c = 1 Bode Diagram, with K




Note integrative characteristic




A passive phase lag network


Active lead and lag networks




Here’s an example of an active network architecture.

EE 3CL4, §6 38/63

Lag compensator design

Tim Davidson Compensators Lead compensation Design via Root Locus

• Lag compensator: G (s ) = K ++ . with |z | > |p |. • Recall position error constant for compensated type-0

system and velocity error constant for compensated type-1 system:

Lead Compensator example

 K C z K G i z i  , K posn =


p

Design via Root Locus


j p j

 K C z K G i z i  K v = p

j p j

where in the latter case the product in the denominator is over the non-zero poles.

Lag Compensation

Lag compensator example

s z c s p

c

Design Principles

• •

We don’t try to reshape the uncompensated root locus.

•

Reshaping was the goal of lead compensator design

We just try to increase the value of the desired error constant by a factor α lag = z /p without moving the poles (well not much)

EE 3CL4, §6 39/63

Lag compensator design


Design principles: Don’t reshape the root locus

•

•



•

•

Adding the open loop pole and zero from the compensator should only result in a small change to the angle criterion for any point on the uncompensated root locus Angles from compensator pole and zero to any point on the locus must be similar Pole and zero must be close together

• Increase value of error constant: • • •

Want to have a large value for α lag = z /p . How can that happen if z and p are close together? Only if z and p are both small, i.e., close to the origin

EE 3CL4, §6 40/63

Lag comp. design via Root Locus

Tim Davidson Compensators Lead compensation Design via Root Locus

1 2

Lead Compensator example


3

Lag Compensation

5

4



6

Obtain the root locus of uncompensated system From transient performance specs, locate suitable dominant pole positions on that locus Obtain the loop gain for these points, K = K P K G ; hence the (closed-loop) steady-state error constant Calculate the necessary increase. Hence α lag = z /p Place pole and zero close to the origin (with respect to desired pole positions), with z = α lag p . Typically, choose z and p so that their angles to desired poles differ by less than 1 ◦ . Set K C = K P

What if there is nothing suitable at step 2? Perhaps do lead compensation first, then lag compensation on lead compensated plant. i.e., design a lead-lag compensator

• •

EE 3CL4, §6 41/63

Example




Let’s consider, again, the case with G (s ) = s (s 1+2) . Design a lag compensator to achieve damping coefficient ζ 0.45 and velocity error constant K v > 20

≈

Note: we will get a different closed loop from our lead design.

First step, obtain uncompensated root locus, and locate desired dominant pole locations

EE 3CL4, §6 42/63

Example




• Gain required to put closed loop poles in desired position = prod. distances from open loop poles 2

• That is, K = 2.24 = 5. Therefore K = K /K = 5 • Velocity error const: K , = lim sK G (s ) = K /2 = 2.5 • The increase required is 20/2.5 = 8 • That implies must choose p = z /8, where z is chosen to be P

v unc

s →0

G

P

close to the origin with respect to dominant closed-loop poles


Example




Let’s choose z = 0.1. Hence, p = 1/80.


Example




Root locus of lag comp’d system with G C (s ) =

K C (s +0.1) (s +1/80)

• ’s: closed-loop poles for prop.-control with K = 5 • ×’s: open-loop poles of lag comp’d system • ◦: OL zero of lag comp’d system; also a CL zero P

EE 3CL4, §6 45/63

Example

Tim Davidson

Prop.-contr.

Lag contr.

5

5(s +0.1) (s +1/80)

OL TF, G C (s )G (s )

5 s (s +2)

5(s +0.1) 1 (s +1/80) s (s +2)

Y (s ) R (s )

5 s (s +2)+5

5(s +0.1) s (s +2)(s +1/80)+5(s +0.1)

−1 ± j 2 ∞, ∞

−0.955 ± j 1.979, −0.104 −0.1, ∞, ∞

Compensators Lead compensation

Controller, G C (s )



CL TF,

CL poles CL zeros CL TF, again

5 2 s +2s +5

4.999(1+7×10−4 s ) s 2 +1.909s +4.827

+

−0.004 s +0.104


• Complex conjugate poles still dominate • Closed-loop zero at -0.1 (which is also an open-loop

zero) reduces impact of closed-loop pole at -0.104; see also slide 48 of Section 3: Fundamentals of Feedback




Ramp response




Ramp response, detail


Step response




Note longer settling time of lag controlled loop, and slight increase in overshoot, due to CL zero

EE 3CL4, §6 50/63

Design Comparisons

Tim Davidson Compensators Lead compensation

For given example: G (s ) =



≈ 0.45, K v ≥ 20.

Prop.-contr.

Lead contr.

Lag contr.

5

125(s +4.47) (s +12.5)

5(s +0.1) (s +1/80)

Y (s ) R (s )

5 2 s +2s +5

131(1+0.013s ) 1.71 − 2 5.59 + s s +8.94s +100

4.999(1+7×10−4 s ) s 2 +1.909s +4.827

CL poles

−1 ± j 2

−4.47 ± j 8.94, −5.59

−0.955 ± j 1.979, −0.104

CL zeros

∞, ∞

−4.47, ∞, ∞

−0.1, ∞, ∞

0.4

0.045

0.05


1 , ζ s (s +2)

G C (s )

1/K v

•

+

−0.004 s +0.104

Lag design retains similar CL poles to prop. design, plus a “slow” pole

• CL poles of lead design quite different • Lead and lag meet K v specification (1/K v = e ss,ramp )




Ramp response




Ramp response, detail




Step response




Step response, detail




Anything else to consider?

EE 3CL4, §6 56/63

Anything else to consider?


Cascade compensation and steady-state errors Lag Compensation

With H (s ) = 1, Y (s ) =


−


G c (s )G (s ) G (s ) R (s ) + T d (s ) 1 + G c (s )G (s ) 1 + G c (s )G (s ) G c (s )G (s ) N (s ) 1 + G c (s )G (s )

E (s ) =

1 R (s ) 1 + G c (s )G (s )

− 1 + G G ((s s ))G (s ) T (s ) c

d

G c (s )G (s ) N (s ) + 1 + G c (s )G (s )




Response to step disturbance




Response to step disturbance, detail early

EE 3CL4, §6 59/63 Tim Davidson Compensators

Response to step disturbance, detail late




Homework: Show that e ss for a step disturbance is 0.2, 0.0225 and 0.025 for prop., lead, lag, resp.




Error due to Gaussian sensor noise




Bode diagram of G C (s )G (s )/(1 + G C (s )G (s ))

Lead Lag Handout

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