33 PCI BUS OPERATIONS
CONT CO NTEN ENTS TS AT A GL GLAN ANCE CE PCI Bus Configuration Configuration and Signals PCI Bus layou layoutt Knowing Knowi ng the PCI signa signals ls
General Bus Troubleshooting Further Study
32-bit CPUs and graphics-intensive graphics-intensive operating By the late 1980s, the proliferation of 32-bit systems made it painfully obvious that the 8.33MHz ISA bus was no longer satisfactory. The PC industry began to develop alternative alternative architectures for improved performance. Two architectures architectures are now prominent: VL and PCI. Although the VL bus seems ideal, some serious limitations limitations must be overcome. Perhaps most important is the VL bus dependence on CPU speed—fast computers must use wait states with the VL bus, and the VL bus only supports one or two slots slots (maximum). Another problem is that the VL standard is voluntary, and not all manufacturers adhere to VESA specifications completely. In mid-1992, Intel Corporation Corporation and a comprehensive consortium of manufacturers introduced the Peripheral the Peripheral Component Interconnect (PCI) bus. bus . Where the VL bus was designed specifically to enhance PC video systems, the 188-pin PCI bus looks to the future of CPUs (and PCs in general) by providing a bus architecture that also supports peripherals, peripherals, such as hard drives, networks, etc. This chapter shows you the layout and operations of the PCI bus.
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PCI BUS CONFIGUR CONFIGURATI ATION ON AND SIGNALS SIGNALS
1049 104 9
PCI Bus Configuration and Signals The PCI architecture is capable of transferring data at 132MB/sec—a great improvement over the 5MB/sec transfer rate of the standard ISA bus. Another key advantage of the PCI bus is that it will have automatic configuration capabilities for switchless/jumperless switchless/jumperless peripherals. Auto-configuration (the (the heart of Plug and Play) will take care of all addresses, addresses, interrupt requests, and DMA used by a PCI peripheral. Table 33-1 lists the features for a PCI bus. The PCI bus supports linear bursts, bursts, which is a method of transferring data that ensures that the bus is continually continually filled with data. The peripheral devices expect expect to receive data from the system main memory memory in a linear address order. This means that large amounts amounts of data is read from or written to a single address, which is then incremented for the next byte in the stream. The linear burst is one of the the unique aspects of the PCI bus because because it will perform both burst reads and burst writes. writes. In short, it will transfer data data on the bus every clock cycle—this doubles the PCI throughput compared to buses without linear burst ca pabilities. The devices designed to support PCI have low access latency, reducing the time required for a peripheral to be granted control of the bus after requesting requesting access. For example, an Ethernet controller card connected to a LAN has large data files from the network coming into into its buffer. Waiting for access access to the bus, the Ethernet is unable unable to transfer the data to the CPU quickly enough to avoid a buffer overflow—forcing it to tem porarily store the file’s contents contents in extra RAM. Because PCI-compliant PCI-compliant devices support faster access times, the Ethernet card can promptly send data to the CPU. T AB AB LE LE 3 33- 1 F EA EA TU TU RE RE S O F A PCI BUS ARCHITECTURE Performance features include: s
Data bursting as normal operating mode—both read and write
s
Linear burst ordering
s
Concurrency support (deadlock, buffering solutions)
s
Low latency guarantees for real-time devices
s
Access-oriented arbitration (not time slice)
s
Supports multiple loads (PCI boards) at 33MHz
s
Error detection and reporting
s
Multimaster; peer-to-peer communication
s
32-bit multiplexed, processor independent
s
Synchronous, 8–33MHz (132MB/sec) operation
s
Variable length, linear bursting (both read and write)
s
Parity on address, data, command signals
s
Concurrency/pipelining support
s
Initialization hooks for auto-configuration
s
Arbitration supported
s
64-bit extension transparently compatible with 32-bit
s
CMOS drivers; TTL voltage levels
s
5-V and 3.3-V compatible
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The PCI bus supports bus mastering, which allows one of a number of intelligent peripherals to take control of the bus to accelerate a high-throughput, high-priority high-priority task. PCI architecture also supports concurrency—a technique that ensures that the microprocessor operates simultaneously simultaneously with these masters, instead of waiting waiting for them. As one example, concurrency allows the CPU to perform floating-point calculations on a spreadsheet while an Ethernet card and the LAN have control control of the bus. Finally, PCI was developed developed as a dual-voltage architecture. architecture. Normally, the bus is is a +5-Vdc system, like like other busses. However, the bus can also operate in a +3.3-Vdc (low-voltage) mode. PCI BUS LAYOUT
The layout for a PCI bus slot is shown in Fig. 33-1. Notice that there are two major segments to the +5-Vdc connector. A +3.3-Vdc connector adds a key in the 12/13 positions to prevent accidental insertion of a +5-Vdc PCI board into a +3.3-Vdc slot. Similarly, the +5-Vdc slot is keyed in the 50/51 position to prevent placing a +3.3-Vdc board into a +5-Vdc slot. The pinout for a PCI bus is shown in Table 33-2. A1
A49 A52 A62 A63
A94 5 volt
B1
A1
A11
B49 B52 B62 B63
B94
A62 A63
A94
A14
3.3 volt B1
B11
B14
FIGURE FIG URE 3333-1 1
B62 B63
B94
PCI local bus diagrams.
TABLE TABL E 33-2 PCI BUS BUS PINOUT— PINOUT—5 5 VOLT VOLT AND 3.3 3.3 VOLT VOLT (REV. (REV. 2.0) 2.0)
5 VOLT
3.3 VOLT
PI N
TCK
TCK
B2
A2
+12 Vdc
+12 Vdc
Ground
Ground
B3
A3
TMS
TMS
TDO
TDO
B4
A4
TDI
TDI
+5 Vdc
+5 Vdc
B5
A5
+5 Vdc
+5 Vdc
+5 Vdc
+5 Vdc
B6
A6
–INTA
–INTA
–INTB –INTD
B7 B8
A7 A8
–TRST
5 VOLT
–12 Vdc
–INTB
A1
3.3 VOLT
–12 Vdc
–INTD
B1
PI N
–INTC +5 Vdc
–TRST
–INTC +5 Vdc
–PRSNT1
–PRSNT1
B9
A9
Reserved
Reserved
Reserved
Reserved
B10
A10
+3.3 Vdc (I/O)
+5 Vdc
–PRSNT2
–PRSNT2
B11
A11
Reserved
Reserved
Ground
Key
B12
A12
Key
Ground
Ground
Key
B13
A13
Key
Ground
PCI BUS CONFIGUR CONFIGURATI ATION ON AND SIGNALS SIGNALS
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TABLE TAB LE 33-2 PCI BUS BUS PINOUT PINOUT—5 —5 VOLT VOLT AND AND 3.3 VOLT VOLT (REV. (REV. 2.0) 2.0) (CONTINUED)
5 VOLT
3.3 VOLT
PI N
PI N
3.3 VOLT
5 VOLT
Reserved
Reserved
B14
A14
Reserved
Reserved
Ground
Ground
B15
A15
–RST
–RST
Clock
Clock
B16
A16
+3.3 Vdc
+5 Vdc
Ground
Ground
B17
A17
–GNT
–GNT
–REQ
–REQ
B18
A18
Ground
Ground
+5 Vdc
+3.3 Vdc
B19
A19
Reserved
Reserved
Adr/Dat 31
Adr/Dat 31
B20
A20
Adr/Dat 30
Adr/Dat 30
Adr/Dat 29
Adr/Dat 29
B21
A21
+3.3 Vdc
+5 Vdc
Ground
Ground
B22
A22
Adr/Dat 28
Adr/Dat 28
Adr/Dat 27
Adr/Dat 27
B23
A23
Adr/Dat 26
Adr/Dat 26
Adr/Dat 25
Adr/Dat 25
B24
A24
Ground
Ground
+5 Vdc
+3.3 Vdc
B25
A25
Adr/Dat 24
Adr/Dat 24
C/ –BE3
C/ –BE3
B26
A26
IDSEL
IDSEL
Adr/Dat 23
Adr/Dat 23
B27
A27
+3.3 Vdc
+5 Vdc
Ground
Ground
B28
A28
Adr/Dat 22
Adr/Dat 22
Adr/Dat 21
Adr/Dat 21
B29
A29
Adr/Dat 20
Adr/Dat 20
Adr/Dat 19
Adr/Dat 19
B30
A30
Ground
Ground
+5 Vdc
+3.3 Vdc
B31
A31
Adr/Dat 18
Adr/Dat 18
Adr/Dat 17
Adr/Dat 17
B32
A32
Adr/Dat 16
Adr/Dat 16
C/ –BE2
C/ –BE2
B33
A33
+3.3 Vdc
+5 Vdc
Ground
Ground
B34
A34
–FRAME
–FRAME
–IRDY
–IRDY
B35
A35
Ground
Ground
+5 Vdc
+3.3 Vdc
B36
A36
–TRDY
–TRDY
–DEVSEL
–DEVSEL
B37
A37
Ground
Ground
Ground
Ground
B38
A38
–STOP
–STOP
–LOCK
–LOCK
B39
A39
+3.3 Vdc
+5 Vdc
–PERR
–PERR
B40
A40
SDONE
SDONE
+5 Vdc
+3.3 Vdc
B41
A41
–SBO
–SBO
–SERR
–SERR
B42
A42
Ground
Ground
+5 Vdc
+3.3 Vdc
B43
A43
PAR
PAR
C/ –BE1
C/ –BE1
B44
A44
Adr/Dat 15
Adr/Dat 15
Adr/Dat 14
Adr/Dat 14
B45
A45
+3.3 Vdc
+5 Vdc
Ground
Ground
B46
A46
Adr/Dat 13
Adr/Dat 13
Adr/Dat 12
Adr/Dat 12
B47
A47
Adr/Dat 11
Adr/Dat 11
Adr/Dat 10
Adr/Dat 10
B48
A48
Ground
Ground
Ground
Ground
B49
A49
Adr/Dat 9
Adr/Dat 9
Key
Ground
B50
A50
Ground
Key
Key
Ground
B51
A51
Ground
Key
Adr/Dat 8
Adr/Dat 8
B52
A52
C/ –BE0
C/ –BE0
Adr/Dat 7
Adr/Dat 7
B53
A53
+3.3 Vdc
+5 Vdc
+5 Vdc
+3.3 Vdc
B54
A54
Adr/Dat 6
Adr/Dat 6
Adr/Dat 5
Adr/Dat 5
B55
A55
Adr/Dat 4
Adr/Dat 4
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TABLE TAB LE 33-2 PCI BUS BUS PINOUT PINOUT—5 —5 VOLT VOLT AND AND 3.3 VOLT VOLT (REV. (REV. 2.0) 2.0) (CONTINUED)
5 VOLT
3.3 VOLT
PI N
PI N
3.3 VOLT
5 VOLT
Adr/Dat 3
Adr/Dat 3
B56
A56
Ground
Ground
Ground
Ground
B57
A57
Adr/Dat 2
Adr/Dat 2
Adr/Dat 1
Adr/Dat 1
B58
A58
Adr/Dat 0
Adr/Dat 0
+5 Vdc
+3.3 Vdc
B59
A59
+3.3 Vdc
+5 Vdc
–ACK64
–ACK64
B60
A60
–REQ64
–REQ64
+5 Vdc
+5 Vdc
B61
A61
+5 Vdc
+5 Vdc
+5 Vdc
+5 Vdc
B62
A62
+5 Vdc
+5 Vdc
Key
Key
Key
Key
Key
Key
Key
Key
Key
Key
Key
Key
Reserved
Reserved
B63
A63
Ground
Ground
Ground
Ground
B64
A64
C/ –BE7
C/ –BE7
C/ –BE6
C/ –BE6
B65
A65
C/ –BE5
C/ –BE5
C/ –BE4
C/ –BE4
B66
A66
+3.3 Vdc
+5 Vdc
Ground
Ground
B67
A67
PAR64
PAR64
Adr/Dat 63
Adr/Dat 63
B68
A68
Adr/Dat 62
Adr/Dat 62
Adr/Dat 61
Adr/Dat 61
B69
A69
Ground
Ground
+5 Vdc
+3.3 Vdc
B70
A70
Adr/Dat 60
Adr/Dat 60
Adr/Dat 59
Adr/Dat 59
B71
A71
Adr/Dat 58
Adr/Dat 58
Adr/Dat 57
Adr/Dat 57
B72
A72
Ground
Ground
Ground
Ground
B73
A73
Adr/Dat 56
Adr/Dat 56
Adr/Dat 55
Adr/Dat 55
B74
A74
Adr/Dat 54
Adr/Dat 54
Adr/Dat 53
Adr/Dat 53
B75
A75
+3.3 Vdc
+5 Vdc
Ground
Ground
B76
A76
Adr/Dat 52
Adr/Dat 52
Adr/Dat 51
Adr/Dat 51
B77
A77
Adr/Dat 50
Adr/Dat 50
Adr/Dat 49
Adr/Dat 49
B78
A78
Ground
Ground
+5 Vdc
+3.3 Vdc
B79
A79
Adr/Dat 48
Adr/Dat 48
Adr/Dat 47
Adr/Dat 47
B80
A80
Adr/Dat 46
Adr/Dat 46
Adr/Dat 45
Adr/Dat 45
B81
A81
Ground
Ground
Ground
Ground
B82
A82
Adr/Dat 44
Adr/Dat 44
Adr/Dat 43
Adr/Dat 43
B83
A83
Adr/Dat 42
Adr/Dat 42
Adr/Dat 41
Adr/Dat 41
B84
A84
+3.3 Vdc
+5 Vdc
Ground
Ground
B85
A85
Adr/Dat 40
Adr/Dat 40
Adr/Dat 39
Adr/Dat 39
B86
A86
Adr/Dat 38
Adr/Dat 38
Adr/Dat 37
Adr/Dat 37
B87
A87
Ground
Ground
+5 Vdc
+3.3 Vdc
B88
A88
Adr/Dat 36
Adr/Dat 36
Adr/Dat 35
Adr/Dat 35
B89
A89
Adr/Dat 34
Adr/Dat 34
Adr/Dat 33
Adr/Dat 33
B90
A90
Ground
Ground
Ground
Ground
B91
A91
Adr/Dat 32
Adr/Dat 32
Reserved
Reserved
B92
A92
Reserved
Reserved
Reserved
Reserved
B93
A93
Ground
Ground
Ground
Ground
B94
A94
Reserved
Reserved
GENERAL GENERAL BUS TROUBLE TROUBLESHOO SHOOTING TING
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KNOWING THE PCI SIGNALS
To reduce the number of pins needed in the PCI bus, data and address lines are multiplexed together (Adr./Dat 0 to Adr./Dat Adr./Dat 63). It is also interesting to note that PCI is the first bus standard designed to support a low-voltage (+3.3 Vdc) Vdc) logic implementation. On inspection, you will see that +5-Vdc and +3.3-Vdc implementations of the PCI bus place their physical key slots in different places so that the two implementations are not interchangeable. The Clock (CLOCK) signal provides timing for the PCI bus only, and can be adjusted from dc (0Hz) to 33MHz. Asserting the –Reset the –Reset (–RST) signal will reset all PCI devices. Because the 64-bit data path uses eight bytes, the Command/ –Byte Enable Enable (C/ –BE0 to C/ –BE7) signals define which bytes are transferred. Parity across the Address/Data and Byte Enable lines is represented with a Parity a Parity (PAR) or 64-Bit or 64-Bit Parity (PAR64) signal. Bus mastering is initiated by the –Request the –Request (–REQ) line and granted after approval using the –Grant the –Grant (–GNT) line. When a valid PCI bus cycle is in progress, the –Frame the –Frame (–FRAME) signal is true. If the PCI bus cycle is in its final phase, –Frame –Frame will be released. The –Target The –Target Ready (–TRDY) line is true when an addressed device is able to complete the data phase of its bus cycle. An –Initiator An –Initiator Ready (–IRDY) signal indicates that valid data is present on the bus (or the bus is ready to accept data). The –FRAME, –TARGET READY, and –INITIATOR READY signals signals are all used used together. A –Stop (–STOP) signal is asserted by a target asking a master to halt the current data data transfer. The The ID Select (IDSEL) signal is used as a chip-select signal during board configuration configuration read and write cycles. The –Device The –Device Select (–DEVSEL) line is both an input and an output. As an input, –DEVSEL –DEVSEL indicates if a device has assumed control of the current bus transfer. As an output, –DEVSEL shows that a device has identified itself as the target for the current bus transfer. The four interrupt lines are labeled –INTA to –INTD. When the full 64-bit data mode is being used, an expansion device will initiate a –64-Bit a –64-Bit Bus Request (–REQ 64) and await a –64-Bit Bus Acknowledge (–ACK64) signal from from the bus controller. controller. The –Bus Lock (–LOCK) signal is an interface control used to ensure use of the bus by a selected expansion device. Error reporting reporting is performed performed by –Primary by –Primary Error (–PERR) and –Secondary –Secondary Error (–SERR) lines. Cache memory and JTAG JTAG support are also provided on the PCI PCI bus.
General Bus Troubleshooting Troubleshooting In most cases, you will not be troubleshooting a bus—after all, the bus is little more than a passive connector. However, the major signals that exist on an PCI bus can provide you with im portant clues about the system’s system’s operation. The most effective effective bus troubleshooting troubleshooting tool available to you is a POST board board (such as the ones covered in Chapter 15). Many POST boards are equipped with a number of LEDs that display power status, along with important timing and control signals. If one or more of those LEDs is missing, a fault has likely occurred somewhere on the motherboard. motherboard. Remember that the vast vast majority of POST POST boards are designed for the ISA bus. You can plug a POST board (with (with a built-in logic probe capable capable of 33MHz operation) into an ISA connector, connector, then use the logic probe to test key signals. Because the signals on a PCI bus are quite different than those on an ISA bus, try the following signals: s
Voltage Use your multimeter and check each voltage level on the PCI bus. You should be able to find –12 Vdc and +5 Vdc, regardless of whether the bus is standard or low-voltage.
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For a low-voltage low-voltage bus, you should also also be able to find a +3.3-Vdc +3.3-Vdc supply. If any of these supply levels are low or are absent, troubleshoot or replace the power supply. s CLOCK (pin B16) The Clock signal provides timing signals for the expansion device. It can be adjusted between between DC (0Hz) and 33MHz. If this signal is absent, absent, the expansion board will probably not run. run. Check the clock-generating clock-generating circuitry on the mother board or replace the motherboard outright. s RST (pin B18) The Reset line can be used to re-initialize the PCI expansion device. This line should not be active for more than a few moments after power is applied or after a warm reset is initiated. PCI busses are highly dependent on a myriad of settings in the CMOS setup. Always check for proper CMOS configuration whenever you encounter trouble with PCI devices or bus performance.
Another point to consider consider is that bus connectors connectors are mechanical devices. devices. As a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal “fingers” providing contact will wear, resulting in unreliable unreliable connections. connections. Similarly, inserting a board board improperly (or (or with excessive force) can break the connector. In extreme cases, even the motherboard motherboard can be damaged. The first rule of board replacement replacement is: always remove and re-insert re-insert the suspect board. It is not uncommon for oxides to develop on board and slot slot contacts that may eventually degrade signal quality. quality. By removing the board and re-inserting re-inserting it, you can wipe off any oxides or dust and possibly improve the connections. The second rule of board replacement is: always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before before suffering the expense of a new board. Keep in mind that many current PCI motherboards motherboards have only one or two PCI slots—the remainder are ISA slots. slots. If a bus slot is defective, a technician can do little, except:
1 Block the slot and inform the customer that it is damaged and should not be used. 2 Replace the damaged bus slot connector (a tedious and time-consuming task) and pass the labor expense on to the customer. 3 Replace the motherboard outright (also a rather expensive option).
Further Study That’s it for Chapter Chapter 33. Be sure to review the glossary glossary and chapter questions on the the accompanying CD. If you have access to the Internet, Internet, take a look at some of these various various PCI resources: PCI Special Interest Group Home Page: http://www.pcisig.com/ PC2 Consulting: http://www.pc2.com/ CompactPCI Home Page: http://www.compactpci.com/ Small PCI: http://www.pcisig.com/current/smallpci/
