Vlsi Lab Manual Final

Ed t on 2011 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Laboratory Manual

VLSI LAB

Prepared by: ASHISH SHARMA ASSTT. PROFESSOR ECE DEPARTMENT NIET,JAIPUR

DEPT OF E C, C, NIET. NIET. VLSI LAB MANUAL

1

EXPERIMENT 1 : STATIC CHARACTERISTICS OF INVERTER IN SCHEMATIC AIM : Design a CMOS inverter in schematic and simulate for Transient Characteristics. PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the one pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Out1= NOT(a)

DEPT OF E C NIET, VLSI LAB MANUAL

2

EXPERIMENT 2 : STATIC CHARACTERISTICS OF TWO INPUT NAND GATE, TWO INPUT NOR GATE, TWO INPUT AND GATE, TWO INPUT OR GATE IN SCHEMATIC AIM : Design a CMOS two input NAND gate, Two input NOR gate, Two input AND gate and Two input OR gate in schematic and simulate for Transient Characteristics. PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Two Input NOR gate

F= NOT(A+B)

Two Input NAND gate

OUT1=NOT(IN1 AND IN2)


3

Two Input AND gate

OUT=A AND B

Two Input OR gate

OUT= A OR B


4

EXPERIMENT 3 : STATIC CHARACTERISTICS OF INVERTER IN LAYOUT AIM : Design the layout of a CMOS Inverter and simulate for DC(Transfer) and Transient characteristics. PROCEDURE :

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout diagram. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal. Label for input and outputs. Assign appropriate Clock input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics.


5

EXPERIMENT 4 : TRANSFER AND TRANSIENT CHARACTERISTICS OF TWO INPUT NAND GATE, TWO INPUT OR GATE, TWO INPUT AND GATE AND TWO INPUT AND GATE IN LAYOUT AIM : Design the layout for two input NANDgate, three input OR gate, two input AND gate and two input AND gate.and simulatelate for DC(Transfer) and Transient characteristics. PROCEDURE :

Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout diagram. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal. Label for input and outputs. Assign appropriate Clock input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics.


6


7


8

EXPERIMENT 5 : REALISE A 2 INPUT EXOR GATE AIM : Realise a two input EXOR gate in schematic and draw its layout and simulate PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout diagram. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal. Label for input and outputs. Assign appropriate Clock input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics. OUT = NOT ( A B + AB)


9


10

EXPERIMENT 6 : REALISE A 1 BIT FULL ADDER IN CMOS SCHEMATIC AND SIMULTATE. GENERATE LAYOUT USING TOOL OPTION AND SIMULATE AIM : TO realise a 1 bit full adder in CMOS schematic and simultate. generate layout using tool option and simulate PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. SUM = A ⊕ B ⊕ C CARRY=AB+BC+CA


11

Wave forms of one bit Full adder

Layout of one Bit Full adder


12

EXPERIMENT 7: REALISE A BOOLEAN EXPRESSION Y=NOT((A+B)(C+D)E) IN SCHEMATIC AND DRAW ITS LAYOUT AND SIMULATE AIM : TO realise a Boolean expression Y=Not((A+B)(C+D)E) in schematic and draw its layout and simulate. PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout diagram. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal. Label for input and outputs. Assign appropriate Clock input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics.


13


14

EXPERIMENT 8 : 4 X 1 MUX USING TRANSMISSION GATES AIM : To Realize a 4 X 1 MUX using transmission gates in schematic and layout and simulate. PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output.

Theory : CMOS transmission gate is created by connecting an nFET and pFET in Parallel as shown. If sel=0 nFET is OFF and pFET is OFF and TG acts as Open switch. When sel=1 then TG acts as closed switch. It does not have threshold voltage drop problems. It can be used as for transmitting any voltage (0,Vdd) from left to right and vice versa.. A 4X1 Multiplexer can be designed using transmission gates as shown in Fig. below. The schematic works as per the truth table given below: S1 S0 OUT 0 0 I0 0 1 I1 1 0 I2 1 1 I3


15


16

EXPERIMENT 9: D FLIP FLOP, JK FLIPFLOP AND T FLIP FLOP IN CMOS SCHEMATIC AND LAYOUT

AIM : To Realsie D FLIPFLOP, JK FLIPFLOP and T FLIPFLOP in CMOS schematic and layout and simulate

PROCEDURE :

Run the VLSI software for schematic entry. From the tool bar drag and drop the required number of pMOS and one nMOS transistor models. Using the wire form the tool bar connect the transistors as shown in the schematic circuit. Give a Clock as the input and simulate for the output. Run the VLSI software for layout entry. Paint Ndiffussion with proper design rules. Paint Nwell. Put Pdiffusion. Draw POLY over the diffusions as shown in the layout diagram. Put the appropriate diffusion contacts and do connections for VDD and GND. Connect the output contacts using the metal. Label for input and outputs. Assign appropriate Clock input and simulate for the output. Click appropriate option for DC characteristics and observe the DC (Transfer) characteristics.


17

For T flip-flop short J and K.


18

EXPERIMENT 10: FOUR BIT ASYNCHRONOUS COUNTER USING T FLIPFLOP AS A CELL IN SCHEMATIC. AIM : To Realsie a four bit asynchronous counter using T flipflop as a cell in schematic PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the T flip flop cells and connect them as shown in schematic. Give a Clock and Input and simulate for the output.


19

EXPERIMENT 11: FOUR BIT SYNCHRONOUS FLIPFLOP AS A CELL IN SCHEMATIC.

COUNTER

USING

T

AIM : To Realsie a four bit synchronous counter using T flipflop as a cell in schematic PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the T flip flop cells and connect them as shown in schematic. Give a Clock and Input and simulate for the output.


20

EXPERIMENT 12: FOUR BIT SHIFT REGISTER USING D FLIPFLOP AS A CELL IN SCHEMATIC. AIM : To Realsie a four bit shift register using D flipflop as a cell in schematic PROCEDURE :

Run the VLSI software for schematic entry. From the library drag the D flip flop cells and connect them as shown in schematic. Give a Clock and Input and simulate for the output.


21

EXPERIMENT 13: DESIGN OF SCHMITT TRIGGER AIM : Design a Schmitt trigger for the ratio ( β1/ β3)=6) and (β4/ β6)=3) in layout. Calculate UTP and LTP and verify the values by simulation. Assume Vdd=1.2v, Vtn=0.4vand |Vtp|=0.5v. Show the hysterisis curve. PROCEDURE : Calculate the required W and L from the given parameters. Draw the layout as shown in the layout. Give a sine wave signal as input and simulate. Use the tool option to observe the hysterisis curve. Theory : The Schematic of Schmitt Trigger is shown below. M1 and M2 are in series and are driven by in1. When in1=0 Vout =Vdd and M3 is ON which acts as feedback path. As in1 is increased it keeps M2 off even after M1 is turned on. The UTP is given by UTP = (Vdd + β 1 / β 3 Vt,n) /(1+ β 1 / β 3 )

β 1 / β 3 = (W / L)1 /(W / L)3 Similarly M6 is feedback resistor for pFET group. The LTP is given by

LTP = ( β 4 / β 6 (Vdd − | Vt , p |) /(1+ β 4 / β 6 )

β 4 / β 6 = (W / L)4 /(W / L)6 Design example : Let UTP =1.45V and LTP= 1.67 V UTP:

β 1 / β 3 = (Vdd − UTP) /(UTP − Vt , n) = 2.44 β 1 / β 3 = 6 and (W/L)1/(W/L)3 = 6 M1 width = 6 x width of M3

LTP:

β 4 / β 6 = ( LTP /(Vdd − | Vt , p | − LTP ) = 2

β 4 / β 6 = 4 and (W/L)4/(W/L)6 = 4 M4width = 4 x width of M6


22


23


24

Hysterisis Characteristics


25


26

Vlsi Lab Manual Final

Recommend Documents