UNIT – 1 VLSI Design (ECE – 401 E) THE INTEGRATED CIRCUIT (IC) ERA The silicon integrated circuit has an extremely rapid growth in the number of transistors (as a measure of complexity) being integrated into circuits on a single silicon chip. In less than three decades, this number has risen from tens to millions as can be seen in Figure 1.
Note ! signifies a multiplier of 1"#$ and % a m ult Note ltii plier plier of 1, 1,"$& "$&,,' '.. Figure 1. Transistors Integrated on a single s ingle chip. *uch has been the impact of this re+olutionary growth that I technology now affects almost e+ery aspect of our li+es. li+es. %ore is still to come since we ha+e not yet reached the limits of miniaturi-ation and there is no doubt that tens of millions of transistors will be readily integrated onto a single chip in the future . This e+olutionary process is reflected in Table 1. Truly the 1"s , the 1&"s and now the 1"s may well be described as the integrated circuit era. era. Table Table 1. %icroelectronics %icroele ctronics /+olution Technolog y **I %*I 2*I 92*I ;2*I
A!o"# N$%&e! o' T! T!nsiso!s nsiso!s
1" 1" 4 1""" 1""" 4 #",""" #",""" 4 1,""",""" 1,""",""" 4 1",""","""
3*I
< 1",""","""
Tyicl Tyicl *!o+$cs
0lanar e+ices, 2ogic 3ates, Flip 4 Flops ounters, %ulitplexers, 5dders & 4 6it %icroprocessors, 78%, 75% 1 5nd :# 4 6it %icroprocessors, 75% *pecial 0rocessors, 9irtual 7eality %achines, *mart *ensors
,ASIC -ETAL ./IDE SE-IC.NDUCT.R (-.S) TRANSIST.R n%8* de+ices de+ices are formed in a p= p =type substrate of moderate doping le+el. The source and drain regions are formed form ed by dif diffus fusing ing n 4 ty type pe imp impuri uritie tiess thr throug ough h sui suitab table le mas mas>s >s into these areas to gi+ gi+ee the desired desired n= impurity concentration and gi+e rise to depletion regions which extend ma inly in the more lightly doped p= region as shown. Thus, source and drain are isolated from one another by two diodes. onnections to the source and drain are made by a deposited metal layer . In order to ma>e a useful de+ice, there must be the capability for es establishing and controlling a current between source and drain, and .this is commonly achie+ed in one of two ways, gi+ing rise to the enhancement mode and depletion mode transistors.
Figure #. %8* Transistor. onsider the enhancement mode de+ice first, first , shown in Figure #(a). #(a) . 5 polysilicon gate is deposited on a layer of insulation o+er the region between source and drain . Figure #(a) shows a basic enhancement mode de+ice in which the channel is not established establis hed and the de+ice is in a non=conducting condition, 9 ? 9* ? 9gs ? ". If this gate is connected to a suitable positi+e +oltage with respect to the source, source , then the electric field established between the gate and the substrate gi+es rise to a charge in+ersion region in the substrate under the gate insulation and a conducting path or channel is formed between source and drain. The channel may also be establi established shed so that it is present under the condition condition 9gs ? " by implanting suitable impurities in the region between source and drain during manufacture and prior to depositing the insulation and the gate. gate. This arrangement is shown in Figure #(b). ;nder these circumstances, source and drain are
connected by a conducting channel, but the channel may now be closed by applying a suitab le negati+e +oltage to the gate. gate . In both cases, cases, +ariations of the gate +oltage allow control of any curr ent flow between source and drain. drain . Figure #(c) shows the basic p%8* transistor structur e structur e for an enhancement mode de+ice. de+ice . In this case the substrate is of n=type materia materi al and the source sourc e and dr ain diffus diffusion ionss are conse@uently p=type. p=type . In the figure, figure, the conditions shown are those for an unbiased de+iceA de+ice A howe+er , the app applic licatio ation n of a neg negati+ ati+ee +oltage +oltage of suitable magnitude (
ENHANCE-ENT -.DE TRANSIST.R ACTI.N The enhancement mode de+ de +ice ice,, as in Figure :, has three sets of conditions. conditions . It must first be recogni-ed that tha t in in order to establish the channel in the first place a minimum +oltage le+el of threshold +o +ollta tag ge 9t must be established between gate and source (and of course between gate and subs tr ate ate as a result). Figure :(a) then indicates the conditions pre+ pre +ailing with the chann channel el establ establiished but no curren currentt flowing between source and drain dra in (9ds ? ") ").. Now consider the cond condiitions pre+ailing when current flows in the channel by applying a +oltage 9ds between drain and source source.. There must, of course, be a corresponding I7 drop ? 9 ds along the channel. channe l. This results in the +oltage between gate and channel +arying with distance along the channel with the +oltage being being a maxim maximum um of 9 gs at the source end. end. *ince the effecti+e gate +oltage is 9g ? 9 gs 4 9t (no current flows when 9gs E 9t) there will be +oltage a+ailable to in+ert the channel at the drain end so long as 9gs 4 9t 9ds. The limiting condition comes when 9ds ? 9 gs 4 9 t. For all +oltages 9ds E 9gs 4 9t, the de+ice is in the non=saturated regi region on of operation which is the condition shown in Figure :(b) . onsider now now what happens when 9ds is increased to a le+el greater than 9gs 4 9 t. In this case, case, an I7 drop ? 9gs 4 9 t ta>es place o+ o+er les less than the whole length of the channel so that o+er part of the channel , near the drain, there is insufficient electric field a+ a +ailable to gi+e rise to an in+ersion layer to create the channel. The channel is, is, therefore therefore,, pinched off as indicated in Figure :(c) :(c).. iffusion current completes the path from source to drain in this case, case , causing the channel to exhibit a high resistance and beha+e as a constan t current source.. This region, >nown as saturat source saturation ion,, is characteri-ed characteri-ed by almost constant current current for increas increasee of 9ds abo+e 9ds ? 9gs 4 9t. In all cases, the channel will cease to exist and no current will flow when 9 gs E 9t. Typically, Ty pically, for enhancement mode de+ices, 9t ? 1 +olt for 9 ? ' 9 or , in general terms, 9t ? ".# 9.
Figure :. /nhancement %ode Transistor 5ction. 5ction.
DE*LETI.N -.DE TRANSIST.R ACTI.N For depletion mode de+ices the channel is established, due to the implant , e+en when 9gs ? ", and to to cause the channel to cease to exi exist a negati+ negati+e +oltage 9td must be applied between gate and source . 9td is typically E =". =" .& 9 , depending on the implant and substrate bias , but but,, threshold +oltage differences apart, the action is similar to that of the enhancement mode transistor.
N-.S A,RICATI.N A,RICATI.N *R.CESS 5n n%8* process is illustrated in Figure $ and may be outlined as follows 1. 0rocessing is carried out on a thin wafer cut from a single crystal of silicon of high high purity purity into which the re@uired p=impurities are introduced as the crystal is grown. *uch wafers are typically ' to 1'" mm in diameter and ".$ mm thic> and are doped with, say, s ay, boron boron to impurity concentrations of 1"1' Gcm: to 1" 1 Gcm:, gi+ing resisti+ity resisti+ity in the approximate range #' ohm cm to # ohm cm . #. 5 layer of silicon dioxide (*i8 #), typically typically 1 Cm thi thic>, c>, is grown all o+er the sur surface face of the the wafer to protect the surface, act as a barrier to dopants during processing processing,, and pro+ide a generally insulating substrate on to which other layers may be deposited and patterned . :. Th Thee surface surface is now now co+er co+ered ed with with a photo photoresi resist st which is deposited onto the wafer and spun to achie+e an e+en distribution of the re@uired thic>ness. $. The photoresist layer is then exposed to ultra+iolet light through a mas> which defines those regions into which diffusion is to ta>e place together with transistor channels. channels. 5ssume, for example, that those areas exposed to ultra+iolet radiation are polymeri-ed (hardened), but that the areas re@uired for diffusion are shielded by shielded by the mas> and remain unaffected. unaffected. '. These areas are subse@uently readily etched away together with the underlying silicon dioxide so that the wafer surface is exposed in the window defined by the mas> . mas> . . Th Thee remainin remaining g photor photoresis esistt is remo+ed remo+ed and and a thin layer layer of *i8# (" ("..1 Cm typica typical) l) is grown o+er the entire chip surface and then polysilicon is deposited on top of this to form the gate structure . The polysilicon
layer con layer consist sistss of hea hea+ily +ily doped pol polysi ysilic licon on dep deposi osited ted by che chemic mical al +a +apo porr deposition (9). (9). In the fabrication of fine pattern de+ices, precise control of thic>ness, impurity concentration, and resisti+ity is necessary. . Further photoresist coating and mas>ing allows the polysilicon to be patterned (as shown in *tep ) and then the thin oxide is remo+ed to expose areas into which n=type impurities are to be diffused to form the source and drain as shown. shown . iffusion is achie+ed by heating the wafer to a high temperature and passing a gas contai containing the desired n=type impurity (for example, phosphorus) o+er the surface as ind ica catted in Figure $. $. Note that the polysilicon with underlying thin oxide oxide act as mas ma s>s during diffusion 4 the process is self=aligning. &. Thic> oxide (*i8 (*i8#) is grown o+er all again and is then mas>ed with photoresist and etched to expose selected areas of the polysilicon gate and the drain and source areas where connections (i.e . contact cuts) are to be made. made. . Th Thee whole chip then then has met metal al (aluminu (aluminum) m) deposit deposited ed o+er its surface surface to a thic thic>ne >ness ss typically typically of I Cm. This metal layer is then mas>ed and etched to form the re@uired interconnection pattern.
Figure $. N%8* Fabrication 0rocess. It will be seen that the process re+ol+es around the formation or deposition and patterning of three layers, separated by silicon dioxide insulation. The layers are diffusion within the substrate, polysilicon on oxide on the substrate, and metal insulated again by oxide. To form depletion mode de+ices it is only necessary to introduce a mas>ed ion implantation step between steps 5 and or and in Figure $. 5gain, the thic> oxide acts as a mas> and this process stage is also self=aligning. onsideration of the processing steps will re+eal that relati+ely few mas>s are needed and the self=aligning aspects of the mas>ing processes greatly ease the problems of mas> registration . In practice, some extra process steps are necessary, including the o+erglassing of the whole wafer, except where contacts to the outside world are re@uired.
S$%%!y o' -ss o' N-.S &!icion *!ocess2
•
0rocessing ta>es place on a p=doped silicon crystal wafer on which is grown a Hthic>H layer of *i8 #. %as> 1=0attern *i8# to expose the silicon surface in areas where paths in the diffusion layer or gate areas
•
of transistors transistors are re@uired. eposit eposit thin oxide o+er all. For this reason, this mas> is often >nown as the HthinoxH mas>. %as> #=0attern the ion implantation within the thinox region where depletion mode de+ices are to be
•
•
produced=self=aligning. %as> :=eposit polysilicon o+er all (1.' Cm thic> typically), then pattern using %as> :. ;sing the same
•
mas>, remo+e thin oxide layer where it is not co+ered by polysilicon. iffuse n regions into areas where thin oxide has been remo+ed. Transistor drains and sources are thus
• • •
self=aligning with respect to the gate structureJ. %as> $=3row thic> oxide o+er all and then etch for contact cuts. %as> '=eposit metal and pattern with %as> '. %as> =Kould =Kould be re@uired for the o+erglassing process step.
C-.S A,RICATI.N A,RICATI.N *R.CESS There are a number of approaches to %8* fabrication, including the p=well, the n=well, the twin=tub processes.. processes
* – 3ELL A,RICATI.N A,RICATI.N *R.CESS 5 brief o+er+iew of the fabrication steps may be obtained with reference to Figure ' , notin noting g that the basic processing steps are of the same nature as those used for n%8*. n%8*. In primiti+e terms, the structure consists of an n=type substrate in which p=de+ices may be formed by suitable mas>ing and diffusion and, in order to accommodate n=type de+ices , a deep p=well is diffused into the n=type substrate as shown. shown .
Figure '. %8* 0 4 Kell Kell 0rocess *teps.
Figure . %8* 0 4 Kell Kell In+erter showing 9 and 9 ** substrate connections. This diffusion must be carried out with special care since the p=well doping concentration and depth will affect the threshold +oltages as well as the brea>down +oltages of the n=transistors. n=transistors . To achie+e low threshold
+oltages (". to 1." 9) we need either deep=well diffusion or high=well resisti+ity. resisti+ity . Lowe+er, deep wells re@uire larger spacing between the n= and p=type transistors and wires due to lateral diffusion and therefore a larger chip area. area. The p=wells. p=wells.act as substr substrates ates for then= then=de+ice de+icess within the parent n=sub n=substrate, strate, and, pro+ pro+ided ided that +oltage polarity restrictions are obser+ed, the two areas are electrically isolated. isolated . Lowe+er , since there are now in effect two substrates, two substrate connections (9 and 9**) are re@uired, as shown in Figure . In all other respects 4 mas>ing, patterning, and diffusion=the process is similar to N%8* fabrication. In summary, typical typical processing steps ste ps are • •
%as> 1 = defines the areas in which the deep p=well diffusions are to ta>e place . %as> # = defines the thinox regions, namely those areas where the thic> oxide is to be stripped and thin
•
oxide grown to accommodate p 4 and n 4 transistors and wires . %as> : = used to pattern the polysilicon layer which is deposited after the thin oxide . %as> %as > $ = 5 p=plus mas> is now used (to be in effect M5ndedM with %as> #) to define all areas where p=
•
diffusion is to ta>e place. place. %as> ' = This is usual usually ly performed using the negati+e form of the p=plu p=pluss mas> and defines those areas
•
•
where n=type diffusion is to ta>e place. %as> = ontact cuts are now defined. %as> = The metal layer pattern is defined by this mas>.
•
%as> & = 5n o+erall passi+ation (o+erglass) layer is now applied and %as> & is needed to define the
•
openings for access to bonding pads.
N – 3ELL A,RICATI.N *R.CESS The p=well process is widely used, n=well fabrication has also gained wide acceptance, initially as a retrofit to n%8* lines. N= N =well %8* circuits are also superior to p=well because of the lower substrate bias effects on transistor threshold +oltage and inherently lower parasitic capacitances associated with source and drain regions.
Figure . %ain *teps in typical N 4 Kell 0rocess. Typical n=well fabrication steps are illustrated in Figure . The first mas> defines the n=well regions. This is followed by a low dose phosphorus implant dri+en in in by by a high temperature diffusion step to form the n= wells. wel ls. The wel welll dep depth th is opt optimi imi-ed -ed to ensu ensure re aga against inst p=substra p=substrate te to p diffu diffusion sion brea>d brea>down own witho without ut compromising then 4 well to n mas> separat separation ion.. The next steps are to define the de+ices and diffusion paths, grow field oxide, deposit and patt pattern ern th thee pol polys ysilicon, ilicon, carry out the diffusions, ma>e contact cuts, and finally metali-e metali-e.. 8wing 8win g to di diff ffere erenc nces es in cha charg rgee carr carrier ier mob mobil iliities ties,, the n=w n=well ell pro process cess crea creates tes non non==optim optimum um p=chan p=channel nel characteristics.. Lowe+er , in man characteristics many y %8 %8* * desi designs gns,, thi thiss is rela relati+ ti+ely ely uni unimp mporta ortant nt sin since ce they contain contain a preponderance of n=channel de+ices. Thus the n=channel transistors are mainly those used to form logic elements,, pro+iding speed and high density elements density of elements.
Figure &. ross 4 *ectional 9iew of %8* N 4 Kell Kell In+erter.
T3IN – TU, A,RICATI.N *R.CESS
5 logical extension of the p=well and n=well approaches is the twin=tub fabrication process. Lere we start with a substrate of high resisti+ity n=type material and then create both n=well and p=well regions . Through thiss pro thi process cess it is pos possibl siblee to pre preser+ ser+ee the per perfor forman mance ce of n=t n=tran ransist sistors ors wit withou houtt com compro prom mising the p= transistors.. transistors oping control is more readily achie+ed and some relaxation in manufacturing tolerances results. This is particularly important as far as latch=up is concerned. In general, the twin=tub process allows separate optimi-ation of the n= and p=transistors. p=transistors . The arrangement of an in+erter is illustrated in Figure .
Figure . Twin 4 Tub *tructure.
THER-AL AS*ECTS . A,RICATI.N A,RICATI.N *R.CESSING *R.CE SSING The processes in+ol+ed in ma>ing n%8* and %8* de+ices ha+e differing high temperature se@uences as indicated in Figure 1". The %8* p=well process, for example, has a high temperature p=well diffusion process (11"" to 1#'"), 1#'"), the n%8* process ha+ing no no such re@uirement. 6ecause of the simplicity, simplicity, ease of fabrication, and high density per unit area of n%8* circuits, many of the earlier I designs, still in current use, use, ha+e been fabricated using n%8* technology and it is li>ely that n%8* and %8* system designs will continue to co=exist for some time to come.
Figure 1". Thermal *e@uence ifference between N%8* and %8* 0rocesses.
DRAIN T. S.URCE CURRENT AND I+s VERSU VERSUS S V.L V.LTAGE V+s RELATI.NSHI* The whole concept of the %8* transistor e+ol+es from the use of a +oltage on the gate to induce a charge in the channel between source and drain, drain, which may then be caused to mo+e from source to drain under the influe inf luence nce of an elec electric tric field created created by +oltage +oltage 9ds applied between drain and source. *ince the charge induced is dependent on the gate to source +oltage 9 gs, then Ids is dependent on both 9 gs and 9dsD
Figure 11. N%8* Transistor *tructure. onsider a structure, as in Figure 11, in which electrons will flow source to drain
I ds =− I sd =
Charge Induced ∈Channel ( Qc ) Electron Electron Transit Time ( τ )
First Transit Time
τ sd=
Lengthof Length of Channel ( L ) Velocity ( v )
6ut 9elocity
v = μ E ds Khere C ? /lectron or Lole %obility (surface) /ds ? /lectric Field (drain to source) Now
E ds=
*o that
V ds L
O..(#.1)
μ V ds v= L Thus 2
L τ sd = μ V ds
O..(#.#)
Typical +alues of C at room temperature areA Cn ? '" cm#G9 sec (surface) C p ? #$" cm#G9 sec (surface)
The Non – S$!e+ Region harge induced in channel due to gate +oltage is due to the +oltage difference between the gate and the channel, channe l, 9gs (assum (assuming ing substrate connected connected to source source). ). Now note that the +olta +oltage ge along the channel +aries linearly with distance P from the source due to the I7 drop in the channel and assuming that the de+ice is not saturated then the a+erage +alue is 9dsG#. Furthermore, the effecti+e gate +oltage 9g ? 9 gs 4 9 t where 9t, is the threshold +oltage needed to in+ert the charge under the gate and establish the channel. Note that the charge G unit area ?
E g ε ins ε 0
. Thus induced charge
Q c = E g ε ins ε 0 WL Khere, /g ? a+erage electric field gate to channel ε ins ? relati+e permitti+ity of insulation between gate and channel
ε0
? permitti+ity of free space
(Note
ε0
? &.&' x 1" =1$ F cm=1A
ε ins
Now
? $." for silicon dioxide)
E g
(=
( V gs−V t ) −
)
V ds 2
D
Khere ? oxide thic>ness.
Qc =
Thus
W L ε ins ε 0 D
(
( V gs−V t ) −
)
V ds 2
Now, combining e@uations (#.#) and (#.:) (#.:) in e@uation (#.1), we ha+e
I ds=
(
)
ε ins ε 0 μ W V ds V gs−V t ) − V ds ( 2 D L
O..(#.:)
8r
(
)
2
V W I ds = K V gs−V t ) V ds − ds ( L 2
O..(#.$)
In the non 4 saturated or resisti+e region where 9 ds E 9gs 4 9t and
K =
ε ins ε 0 μ D
The factor KG2 is contributed by the geometry it is common practice to write
W = K L so that
(
)
2
I ds= ( V gs− V t ) V ds−
V ds 2
O..(#.$a)
Khich is an alternati+e form of e@uation (#.$). Noting that gate Gchannel capacitance
C g=
ε ins ε 0 W L (parallel plate)
D
Ke also ha+e
K =
C g μ WL
*o that
I ds =
((
C g μ L
2
)
2
V gs−V t ) V ds−
V ds 2
O..(#.$b)
Khich is a further alternati+e form of e@uation (#.$). *ometimes it is con+enient to use gate capacitance per unit area " rather than g in this and other expressions. Noting that
C g=C 0 WL Ke may also write
(
)
2
V W I ds =C 0 μ V gs−V t ) V ds− ds ( L 2
O..(#.$c)
The S$!e+ Region *aturation begins when 9 ds ? 9gs = 9, since at this point the I7 drop in the channel e@uals the effecti+e gate to channel +oltage +oltage at the drain and we may assume that the current remains fairly constant constant as 9ds increases further. Thus
W ( V gs−V t ) I ds= K L 2
2
O..(#.')
8r we may write
2 I ds= ( V gs−V t )
O..(#.'a)
2
8r
I ds =
C g μ 2 L
2
( V gs−V t )
2
O..(#.'b)
Ke may also write
I ds =C 0 μ
W 2 V gs−V t ) ( 2 L
O..(#.'c)
The expressions deri+ed for I ds hold for both enhancement mode and depletion mode de+ices, but it should be noted that the threshold +oltage for the N%8* depletion depletion mode de+ice is negati+e.
-.S TRANSIST.R IGURE . -ERIT (0) 5n indication of fre@uency response may be obtained from the parameter Q " where
!0 =
gm C g
( )
= μ (V gs−V t ) ¿ 2
L
1
τ sd
This shows that switching speed depends on gate +oltage abo+e threshold and on carrier mobility and in+ersely as the s@uare of channel length. 5 fast circuit re@uires that gm be as high as possible. /lectron mobil /lectron mobility ity on a (1"" (1"")) orient oriented ed n=type in+ersion layer surface (Cn) is la larg rger er th than an that on a ( 11 111) 1) oriented surface, and is in fact about three times as large as hole mobility on a (111) oriented p=type in+ersion layer . *urface mobility is also dependent on the effecti+e gate +oltage (9gs 4 9t). For faster n%8* circuits, then, one would choose a (1"") oriented p=type substrate in which the in+ersion layer will ha+e a surface carrier mobility Cn ? '" cm#G9 sec at room temperature.
ompare this with the typical bul> mobilities Cn ? 1#'" cm#G9 sec C p ? $&" cm#G9 sec from which it will be seen that Cs G C ? ".' (where C s ? surface mobility and C ? bul> mobility).
*ASS *ASS TRANSIST.R TRANS IST.R ACTI.N ;nli>e bipolar transistors, the isolated nature of the gate allows %8* transistors to be used as switches in series with lines carrying logic le+els in a way that is similar to the use of relay contacts . This application of the %8* de+ice is called the pass transistor and switching logic arrays arrays can be formed=for formed=for example, an 5nd array as in Figure 1#. 1# .
" = # $ % $ C $ ( Logic 1=V DD −V t ) ´ =& "
Figure 1#. 0ass Transistor 5nd 5nd 3ate.
THE N-.S INVERTER 5 basi basic re@ui re@uirement for producing a complete range of logic circuits is the in+erter. This is needed for restoring logic le+els, le+els, for N5N and N87 gates, gates , and for se@uential and memory circuits of +arious forms. forms . The basic in+erter circuit re@uires a transi transistor stor with source connected to ground and a load resistor of some sort connected from the drain to the positi+e supply rail 9 D The output output is ta> ta>en en from the dra drain in and the input applied between gate and ground. ground . 7esistors are not con+eniently produced on the silicon substrateA substrate A e+en modest +alues occupy excessi+ely large areas so that some other form of load resistance is re@uired . 5 con+enient way to sol+e this problem is to use a depletion mode transistor as the load , as shown in Figure 1:. 1:. Now •
Kith no current drawn from the output, the currents I ds for both transistors must be e@ual. For the depletion mode transistor, the gate is connected to the source so it is alwa ys on and only the
•
characteristic cur+e 9gs ? " is rele+ant. In this configuration the depletion mode de+ice is called the pull=up (p .u.) and the enhancement enhancement mode
•
de+ice the pull=down (p. (p.d.) transistor . To obtain obtain the in+er in+erter ter transfe transferr charact characteristic eristic we superi superimpose mpose the 9gs ? " depletion mode characteristic
•
cur+e on the family of cur+es for the enhancement mode de+ice, noting that maximum +oltage acros s the enhancement mode de+ice corresponds to minimum +oltage across the depletion mode transistor. The points of intersection of the cur+es as in Figure 1$ gi+e points on the transfer characteristic, characteristic , which is
•
of the form shown in Figure 1'. Note that as 9in (?9gs p.d p.d.. transistor) exceeds the p.d. threshold +oltage current begins to flow . The
•
output +oltage 9out thus decreases and the subse@uent increases in 9in will cause the p. p.d. transistor to come out of saturation and become resisti+e. Note that the p .u. transistor is initially resisti+e resisti+e as the p.d. p.d. turns on. on.
•
uring transition, the slope of the transfer characteristic determines the gain ( V out 'ain = ( V ¿
•
The point at which 9 out ? 9in is denoted as 9in+ and it will be noted that the transfer characteristics characteristics and 9in+ can be shifted by +ariation of the ratio of pull=up to pull=down resistances (denoted R p.u.GR p.d. where R is determined by the length to width ratio of the transistor in @uestion) .
Figure 1:. N%8* In+erter
Figure 1$. eri+ation of N%8* In+erter Transfer haracteristics.
Figure 1'. N%8* In+erter Transfer haracteristics.
DETER-INATI.N . *ULL5U* T. *ULL5D.3N RATI. (6#$#76#+#) .R AN N-.S INVERTER DRIVEN ,8 AN.THER N-.S INVERTER onsider the arrangement in Figure 1 in which an in+erter is dri+en from the output of another similar in+erter. onsider the depletion mode transistor for which 9 gs ? " unde underr all conditions, conditions, and further assume that in order to cascade in+erters without degradation of le+els we are aiming to meet the re@uirement
V ¿ =V out =V inv
Figure 1. N%8* In+erter ri+en irectly ire ctly by 5nother In+erter. For e@ual margins around the in+erter threshold, we set 9 in+ ? ".' 9. 5t this point both transistors are in saturation and W ( V gs−V t ) I ds = K L 2
2
In the depletion mode
2
I ds= K
W ) $ u $ (−V td ) L ) $u $
*ince *ince V gs =0
2
5nd in the enhancement mode
I ds= K
W ) $ d $ ( V inv−V t ) L ) $d $
2
2
*ince *ince V gs =V inv
/@uating (since the currents are same) we ha+e
W ) $d $ L )$ d $
2
W
( V inv −V t ) = L )$ u $ ( −V td )
2
) $u $
Khere K p.d., 2 p.d., K p.u., 2 p.u. are the widths and lengths of the pull 4 down and pull 4 up transistors respecti+ely. Now write
+ ) $ d $ =
L ) $d $ W )$d$
, + ) $ u $=
L ) $u $ W ) $ u$
Ke ha+e 1
+ ) $d $
1
( V inv −V t ) = + (−V td ) 2
2
) $u $
Lence
V inv=V t −
V td + ) $u $ / + ) $d $ √ +
Now we can substitute typical +alues as follows 9t ? ".# 9
9td ? =". 9 9in+ ? ".' 9 (for e@ual margins)
Thus from e@uation (#.) 0.5= 0.2+
0.6
√ + ) $ u $ / + ) $ d $
Lence
+ ) $u $ / + ) $d $= 2 √ + 5nd thus
+ ) $ u$ / + ) $ d $ =4 / 1
O.. (#.)
For an in+erter directly dri+en by an in+erter.
*UL ULL5 L5U* U* T. *UL ULL5 L5D. D.3N 3N RA RAT TI. . .R R AN NN-.S .S IN INVE VER RTER DRIVEN THR.UGH .NE .R -.RE *ASS TRANSIST.RS Now consider the arrangement of Figure 1 in which the input to in+erter # comes from the output of in+e in +erte rterr 1 bu butt pa passe ssess th thro roug ugh h on onee or mo more re n% n%8* 8* tra trans nsis isto tors rs us used ed as sw swit itch ches es in ser serie iess (c (cal alled led pa pass ss transistors).. transistors)
Figure 1. 0ull=up to 0ull=down 7atios for In+erting 2ogic oupled by 0ass Transistors. Ke are concerned that connection of pass transistors in series will degrade the logic 1 le+el into in+erter # so that the output will not be a proper logic " le+el. The critical condition is when point 5 is at " +olts and 6 is thuss at 9, but the +oltage into in+erter # at point is now reduced from 9 by the threshold +oltage of thu the series pass transistor . Ki Kith th all pass transistor transistor gates conn connected ected to 9, there is a loss of 9 tp, howe howe+er +er many are connected in series, since no static current flows through them and there can be no +oltage drop in the channels. channels. Therefore Therefore,, the input +oltage to in+erter # is
V inv 2=V DD−V t) where 9tp ? threshold +oltage for a pass transistor. Ke must now ensure that for this input +oltage we get out the same +oltage as would be the case for in+erter 1 dri+en with input ? 9D
Figure 1&. /@ui+alent ircuits of In+erter 1 and #. onsider in+erter 1 (Figure 1&(a)) with input ? 9D If the inpu onsider inputt is at 9, then the the p.d. transistor T# is conducting but with a low +oltage across itA therefore, it is in its resisti+e region represented by 7 1 in Figure 1&.. %eanwhile, the p.u. transistor T 1 is in saturation and is represented as a current source. 1& For the p.d. transistors
(
2
W V I ds = K ) $ d .1 ( V DD−V t ) V ds 1− ds 1 L ) $d .1 2
)
O..(from #.$)
Therefore
-1=
V ds 1 1 L ) $d .1 = I ds K W ) $ d .1
(
1
V DD −V t −
)
V ds 1 2
Note that 9ds1 is small and 9 ds1G# may be ignored. Thus
-1 ≑
1
K
+ ) $d .1
(
1
V DD −V t
)
Now, for depletion mode p.u. in saturation with 9 gs ? "
I 1 ¿ I ds= K
The product
W ) $ u .1 ( −V td ) L ) $u .1
2
2
O..(From #.')
I 1 -1=V out 1 Thus
(
+ ) $d .1
V out 1 ¿ I 1 -1 =
1
+ ) $u .1 V DD−V t
)
2
( V td ) 2
onsider in+erter # (Figure 1& (b)) when input ? 9 = 9tp. 5s for in+erter 1
-2 ≑
1
K
I 2 = K
+ ) $d .2
((
1
V DD −V t) )−V t
)
2
1
(−V td )
+ ) $ u .2
2
Lence
V out 2 ¿ I 2 - 2=
+ ) $d .2
(
1
+ ) $u .2 V DD −V t)−V t
)
(−V td )
2
2
If in+erter # is to ha+e the same output +oltage under these conditions then 9 out1 ? 9out#. That is
I 1 -1= I 2 -2
Therefore
+ ) $u .2 + ) $d .2
=
( V DD−V t )
+ ) $u .1
+ ) $d .1 ( V DD −V t)−V t )
Ta>ing Ta>ing typical +alues 9t ? ".# 9
+ ) $u .2 + ) $d .2
=
9tp ? ".: 9
+ ) $u .1
0.8
+ ) $d .1
0.5
Therefore
+ ) $u .2 + ) $d .2
≑2
+ ) $u .1 + )$ d .1
=
8 1
*ummari-ing for an N%8* in+erter •
5n in+erter dri+en directly from the output of another should ha+e a R p.u. G R p.d. ratio of S $G1.
•
5n in+erter dri+en through one or more pass transistors should ha+e a R p.u. G R p.d. ratio of S &G1.
THE C-.S INVERTER The general arrangement and characteristics are illustrated in Figure 1. Ke ha+e seen (e@uation #.$ and #.') that the current G +oltage relationships for the %8* transistor may be written in the resisti+e region
(
)
2
V W I ds= K V gs−V t ) V ds − ds ( 2 L
In the saturation region
W ( V gs−V t ) I ds= K L 2
2
In both cases the factor ! is a technology 4 dependent parameter such that
K =
ε ins ε 0 μ D
The factor KG2 is contributed by the geometry and it is common practice to write
W = K L so that in saturation
2 I ds = ( V gs− V t ) 2
Figure 1. omplementary Transistor 0ull=up (%8*). Khere may be applied to both N%8* and 0%8* transistors as follow
n=
)=
ε ins ε 0 μn W n D
Ln
ε ins ε 0 μ ) W ) D
L )
where Kn, 2n, K p and 2 p are the n and p transistor dimensions where dimensions respecti+ely respecti+ely.. Kith regard to Figures 1 (b) and ( c), it may be seen that the %8* in+erter has fi+e distinct regions of operation .
onsidering the static conditions first, it may be *een that in region 1 for wh ich 9in ? logic ", we ha+e the p 4 transistor fully turned on while the n 4 transistor is fully turned off . Thus no current flows through the in+erter and the output is directly connected to 9 through the p 4 transistor . 5 good logic 1 output +oltage is thus present at the output. In region ' 9in ? logic 1, the n 4 transistor is fully on while the p=transistor is fully off . off . 5gain, no current flows and a good logic " appears at the output. In region # the input +oltage has increased to a le+el which Uust exceeds the threshold +oltage of the n 4 transistor. The n 4 transistor conducts and has a large +oltage between source and drainA so it is in saturation. The p 4 transistor is also conducting but with only a small +oltage across it, it operates in the unsaturated resisti+e region. 5 small current now flows through the in+erter from 9 to 9**. If we wish to analy-e the beha+ior in this region, we e@uate the p 4 de+ice resisti+e region current with the n 4 de+ice saturation current and thus obtain the +oltage and current relationships. 7egion $ is similar to region # but with the roles of the p 4 and n 4 transistors re+ersed. Lowe+er, the current magnitudes in regions # and $ are small and most of the energy consumed in switching from one state to the other is due to the larger current which flows in region :. :. 7egion : is the region in which the in+erter exhibits gain and in which both transistors are in saturation . The currents (with regard to Figure 1 (c)) in each de+ice must be the same since the transistors are in series, so we may write
I ds)=− I dsn Khere
I ds)=
) 2
2
( V ¿ −V DD−V t) )
5nd
I dsn=
n 2
2
( V −V tn ) ¿
From this we can express 9 in in terms of the ratio and the other circuit +oltages and currents 1/ 2
V ¿ =
V DD + V t) + V tn ( n / ) ) 1+
1 /2
n / ) ) (
O..(#.)
*ince both transistors are in saturation, they act as current sources so that the e@ui+alent circuit in this region is two current sources in series between 9 and 9** with the output +oltage coming from their common point. The region is inherently unstable in conse@uence and the changeo+er from one logic le+el to the other is rapid. rapid. If n ? p and if 9in ? =9tp, then from e@uation (#.)
V ¿ =0.5 V DD This implies that the changeo+er between logic le+els is symmetrically disposed about the point at which
V ¿ =V out =0.5 V DD *ince only at this point will the two factors be e@ual. 6ut for n ? p the de+ice geometries geometries must be such that
L )=¿ μn W n / Ln μ ) W ) / ¿ Now the mobilities are inherently une@ual and thus it is necessary for the width to length ratio of the p 4 de+ice to be two or three times that of the n 4 de+ices, so
W ) / L ) ≑ 2.5 W n / L n Lowe+er it must be recogni-ed that mobility C is affected by the trans+erse electric field in the channel and is thus dependent on 9gs. It has been shown empirically that the actual mobility is −1
μ= μ . ( 1− ϕ ( V gs− V t ) )
ϕ is a constant approximately e@ual to "."', 9 t includes any body effect, and C - is the mobility with -ero trans+erse field. Thus a ratio of 1 will only hold good around the point of symmetry when 9 out ? 9in ? ".' 9.
Figure #". Trends in Transfer Transfer haracteristics with 7atio. The rat ratio io is oft often en uni unimp mporta ortant nt in man many y con config figura uratio tions ns and in mo most st case casess min minimu imum m si-e transisto transistor r geometries are used for both n 4 and p 4 de+ices. Figure #". indicates the trends in the transfer characteristic
as the ratio is +aried +aried.. The changes indicated indicated in the figure would be for @uite large +ariations +ariations in ratio (e. (e.g. up to 1" 1" 1) and the ratio is thus not too critical in this respect.
-.S DESIGN *R.CESS %8* design is aimed at turning a specific specification ation into mas>s for processing silicon to meet the specification. %8* circuits are formed on four basic layersA n 4 diffusion, diffusion , p 4 diffusion, diffusion , polysilicon, and metal, which are isolated from one another by thic> or thin (thinox) silicon dioxide insulating layers. layers . The thin oxide (thinox) mas> region includes n 4 diffusion, diffusion, p 4 diffusion, and transistor channels channels.. 0olysilicon and thinox regions interact so that a transistor is formed where they cross one another. In some processes, there may be a second metal layer and in some processes, a second polysilicon layer . 2ayers may deliberately Uoined together togeth er where contacts are formed formed.. The T he basic %8* transistor properties can be modified by the use of an implant within the thinox region and this is used in N%8* circuits to produce depletion mode transistors.
Sic Dig!%s *tic> diagrams diagrams may be used to con+ey layer information information through the use of a color code 4 for exampl example, e, in the case of N%8* design, design, green for n=diffusion, red for polysilicon, blue for metal, yellow for implant , and blac> for contact areas. areas. The encodings chosen are shown in Ta Table ble 1. Table Ta ble 1. /ncoding for *tic> aigrams.
Figure #1. *tic> iagrams of N%8* and 0%8* Transistors.
Figure ##. 2ayout of %8* 2ayers.
N-.S Design Syle The layout of N%8* in+ol+es • • • •
n=diffusion and other thinoxide regions VthinoxW (green) polysilicon (red) metal (blue) implant (yellow)
• •
contacts (blac>) buried (brown)
5 transistor is formed where+er polysilicon crosses n 4 diffusion (red o+er green).
C-.S Design Syle The stic> and layout representations for %8* used are a logical extension of the N%8* approach and style.. Kith the exception of implant (yellow) and the buried contact (brown), are used in %8* design. style Xellow in %8* design is now used to identify p 4 transistors and wires , as depletion mode de+ices are not utili-ed.. 5s a result, utili-ed result, no confusion results from the allocation of the same color to two different features. The two types of transistor used, n and p, are separated in the stic> layout by the demarcation line (brown color) abo+e abo +e wh which ich all p=t p=typ ypee de+ de+ices ices are pla placed ced.. Th Thee n=d n=de+i e+ices ces (gr (green een)) are con conse@ se@uen uently tly pla placed ced bel below ow the demarcation line. • • • • • •
n=diffusion (green) p=diffusion (yellow) polysilicon (red) metal (blue) contacts (blac>) demarcation line (brown)
DESIGN RULES AND LA8.UT The obUect of a set of design rules is to allow a ready translation of circuit design concepts , usually in stic> diagram or symbolic form, into actual geometry in silicon. silicon . The design rules are the effecti+e interface between the circuitGsystem designer des igner and the fabrication fabric ation engineer . learly, both sides of the interface ha+e a +ested interest in ma>ing their own particular tas>s as easy as possible and design rules usually attempt to pro+ide a wor>able and reliable compromise that is friendly to both sides. ircuit designers in general want tighter, smaller layouts for impro+ed performance and decreased silicon area.. 8n th area thee ot othe herr ha hand nd,, th thee pr proc ocess ess en engi gine neer er wa want ntss de desi sign gn ru rule less th that at r esu e sult in a co con ntr olla llable ble and reproducible process. The simple lambda (Y) design rules are based on a single parameter Y which leads to a simple set of rules for the designer, and wide acceptance of the rules by a large cross=secti cross=sect ion of the fabrication houses and silicon bro>ers, and allows for scaling of the designs to a limited extent. This latter feature may help to gi+e designs a longe longerr lifetim lifetimee. The simplicity of lambda=based lambda=based rules also pro+ides a simple introduction introduction to design rules and to mas> layout design in general.
L%&+ – ,se+ Design R$les In general, general, design rules and layout methodology based on the concept of Y pro+ide a process and feature si-e=independent way of setting out mas> dimensions to scale. 5ll paths in all layers will be dimens ioned in Y units and subse@uently Y can be allocated an appropriate +alue compatible with the feature si-e of the fabrication process. This concept means that the actual mas> layout design ta>es little account of the +alue subse@uently allocated to the feature si-e, but the design rules are such that , if correctly obeyed, the mas> layouts will
produce wor>ing circuits for f or a range of +alues allocated allocat ed to Y. For example, Y can be allocated a +alue of 1 ." Zm so that minimum feature si-e on chip will be # Zm (#Y) .
Figure #:. esign 7ules for 2ayers (N%8* and %8*).
Figure #$. Transistor esign 7ules (0%8*, N%8*, %8*).
Conc R$les Khen ma>ing contacts between polysilicon and diffusion in n%8* circuits it should be recogni-ed that there the re are three pos possib sible le app approa roache chess 4 poly polysili silicon con to met metal al then metal to dif diffus fusion ion,, or a bur buried ied contact contact polysilicon to diffusion, or a butting contact (polysilicon to diffusion using metal). metal) . The #Y x #Y contact cut indicates an area in which the oxide is to be remo+ed down to the underlying polysilicon or diffusion surface. Khen deposition of the metal layer ta>es place the metal is deposited through the contact cut area s
onto the underlying area so that contact is made between the layers. layers . Khen connecting diffusion diffusion to polysilicon using the butting contact approach, the process is rather more complex complex.. In effect, a #Y x #Y contact cut is made down to each of the layers to be Uoined. The layers are butted together in such a way that these two contact cuts become contiguous. *ince the polysilicon and diffusion outlines o+erlap and thin oxide under polysilicon acts as a mas> in the diffusion process, process , the polysilicon and diffusion layers are also butted together . The contact between the two butting layer s is then made by a metal o+erlay as shown in the Figure #'. #'.
Figure #'. ontact 7ules (N%8* and %8*).
STIC9 DIAGRA- AND AND LA8.UT LA8.UT . N-.S: C-.S
*LEASE .LL.3 THE N.TES . STIC9 DIAGRA-S
