Ecad & Vlsi Lab(3)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LABORATORY MANUAL FOR

ECAD & VLSI LAB (IV B.Tech., I – Sem)

BALAJI INSTITUTE OF TECHNOLOGY & SCIENCE Laknepally, Narsampet, Warangal

ECAD AND VLSI LAB Department Department of Electronics Electronics &Communication &Communication Engineering Engineering

ECAD & VLSI Lab

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LIST OF EXPERIMENTS: ECAD Programs:

1. HDL code code to realize realize all all the logic logic gates. gates. 2. Design Design of of 2-to-4 2-to-4 decoder. decoder. 3. Design of of 8-to-3 encoder.(with encoder.(with out and with with parity) parity) 4. Design Design of of 8-to-1 8-to-1 multiple multiplexer xer 5. Design Design of 4-bit 4-bit binary binary to gray gray convert converter er 6. Design of multiplexer/demultipl multiplexer/demultiplexer, exer, comparator comparator 7. Design of full adder using three modeling modeling styles 8. Design Design of flip flops: flops: SR, D, JK, T 9. Design of 4-bit binary, binary, BCD counter counter (Synchronous/asy (Synchronous/asynchronou nchronous s reset) or any sequence counter 10.

Finite state machine design

VLSI Programs: 1. Introduc Introduction tion to layou layoutt design design rules rules 2. Layout, physical physical verificatio verification, n, placement placement and route route for complex complex design state timing analysis, IR drop analysis and cross talk analysis of the following i.

Basic logic gates

ii.

CMOS inverter

iii.

CMOS NOR/NAND gates

iv

CMOS XOR and MUX gates



























vii.

Latch

viii.

Pass transistor

3. Layout of any combinationa combinationall circuit circuit (complex CMOS logic gate)Learning about data paths 4. Introduction Introduction to SPICE SPICE simulation simulation and coding coding of NMOS/CMOS circuit 5. SPICE simulation simulation of basic analog analog circuits: circuits: Inverter/ Inverter/ Differential amplifier 6. Analog circuit circuit simulation simulation (AC (AC analysis) analysis) – CS & CD amplifier amplifier 7. System System level level desig design n using using PLL PROCEDURE TO CODE A DESIGN AND VERIFY THE RESULT USING “XILINX ISE SIMULATOR SIMUL ATOR WITH WIT H SPARTAN3 SPARTAN 3 FPGA/COLD FPGA/CO LD Implementation” Step1:

File

New Project

Enter the Project Name Top level Source type : HDL Click Next Step2:

New Project Wizard – Project Properties window opens Select the Device and the Design flow for the Project: Product Category

:

All

Family

:

Spartan3

Device

:

XC3S200



























Simulator

:

ISE Simulator

(VHDL/Verilog)

Click Next New Project Wizard –Create New Source Window opens Click on New Source Select VHDL Module and enter the file name. see that Add to Project is selected. Click Next New Source Wizard – Design module window opens Enter the port name and select the direction appropriately Click Next



Finish

Next

Next

Finish.

Step3:

To enter the logic in the program, program, click the mouse at the the place where the logic needs to be entered. Go to Edit

Language Templates

Examples

……

Synthesis Constructs

Coding

Select the design you are coding. After selection click Edit

Use in File

Save the Program. Step4:To synthesize the Design

Double click Check Syntax in Synthesize – XST in Processes window After checking syntax double click Synthesize – XST Double click View Technology Schematic to view the Schematic diagram of the design. Step5: To Implement the Design

Double click Implement Design in Processes window. Step6: To view the wave forms.



























Select Test Bench Waveform and type the source file name with _tbw at the end. See that Add to project has been selected. Click Next

Next

Finish.

Initial Timing and Clock Wizard – Initialize Timing window opens Set the timings as required if any clock is needed in the design otherwise no need of any settings. Click Finish. Set the waveforms as required. Save and Close the waveforms window. Select Behavioral simulation as Sources for in sources window and click on the .tbw file in sources window. Now double click Simulate Behavioral Model in Xilinx ISE Simulator in processes window to view the output waveform of the design. Step7: To assign the package pins:

Double click Assign Package Pins in User Constraints in processes window. Project Navigator window opens. Click Yes. Click Yes. Xilinx PACE window opens. Select Package View. Select appropriate pins and enter them in the Loc in design object lis –I/O pins. Save the Window Bus Delimiter window opens. Select XST default, default, click OK and OK and close it. Implement the design again by double clicking Implement Design in Processes window. Step8:

Select Post-Route Simulation as Sources for in sources window. Select .tbw file in sources window. Double click Simulate Post-Place and Route Model in processes window. ISE simulator window opens. Click Yes. Click Yes. Waveforms with delay appear on the window.



























Select Configure device using boundary-scan (JTAG) and click Finish. Assign new configuration file window opens. Select .bit file and click open. For the next assign new configuration window click bypass. Right click the XC3S200 FPGA and click program. Programming properties window opens. Click OK.

Program succeeded Appears on the screen and the leds on the spartan3 kits glow indicating the success of the design. Step10:

Verify the result by connecting the digital trainer kit to the pins selected.





























EXPERIMENT- 1 VHDL CODE FOR AND GATE AIM: To AIM: To implement AND gate using VHDL. VHDL. THEORY: The AND gate performs logical multiplication, more commonly known as AND function. And gate can have any number of inputs greater than one. The operation of AND gate is such that output is HIGH only when all of the inputs are HIGH. When any of the inputs are LOW the output is LOW. TRUTH TABLE:

A

B

C

0

0

0

0

1

0

1

0

0

1

1

1

BOOLEAN EXPRESSION: C=AB RTL SCHEMATIC:

CIRCUIT DIAGRAM:





























VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity andgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end andgate; architecture Behavioral of andgate is begin c<= a and b; end Behavioral; TIMING WAVEFOMRS:





























VHDL CODE FOR OR GATE AIM: To AIM: To implement OR gate using Xilinx procedure. THEORY: The THEORY: The OR gate performs logical addition, more commonly known as OR function. OR gate can have any number of inputs greater than one. The operation of OR gate is such that output is HIGH only when any one of the inputs are HIGH. TRUTH TABLE: A 0 0 1 1

B 0 1 0 1

BOOLEAN EXPRESSION: C=A+B RTL SCHEMATIC:

C 0 1 1 1





























use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end orgate; architecture Behavioral of orgate is begin c <= a or b; end Behavioral; TIMING WAVEFORM:





























VHDL CODE FOR NAND GATE AIM: To AIM: To implement NAND gate using Xilinx Xilinx procedure. THEORY: The term NAND is a contraction of NOT-AND and implies an AND functi function on with with a comple complemen mented ted output output.. It is a univer universal sal gate. gate. the logical logical operation of NAND gate is such that a Low output occurs only when all inputs are HIGH. when any of the inputs are LOW, output will be HIGH. TRUTH TABLE: A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

BOOLEAN EXPRESSION: C=A’+b’= (AB)’ RTL SCHEMATIC:































VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity nandgate is port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nandgate; architecture Behavioral of orgate is begin c <= a nand b; end Behavioral; TIMING WAVEFORM:





























VHDL CODE FOR NOR GATE AIM: To AIM: To implement NOR gate using using Xilinx procedure. THEORY: The term NOR is a contraction of NOT-OR and implies an OR functi function on with with a comple complemen mented ted output output.. It is a univer universal sal gate. gate. the logical logical operation of NOR gate is such that a Low output occurs when any of the inputs are HIGH. when all of the inputs are LOW, output will be HIGH. TRUTH TABLE:

A

B

C

0

0

1

0

1

0

1

0

0

1

1

0

BOOLEAN EXPRESSION: C= (A+B)’=A’B’ RTL SCHEMATIC:





























PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity norgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end norgate; architecture Behavioral of norgate is begin c <= a nor b; end Behavioral; TIMING WAVEFORM;





























VHDL CODE FOR XOR GATE AIM: To AIM: To implement XOR gate using using Xilinx procedure. THEORY: It recognizes only the words that have an odd number of ones. This means that for odd odd number of ones, output output of XOR gate is HIGH. HIGH. TRUTH TABLE:

A

B

C

0

0

0

0

1

1

1

0

1

1

1

0

BOOLEAN EXPRESSION: C=A’B+AB’ RTL SCHEMATIC:





























PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity xorgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xorgate; architecture Behavioral of xorgate is begin c <= a xor b; end Behavioral; TIMING WAVEFORM:































VHDL CODE FOR XNOR GATE AIM: To AIM: To implement XNOR gate sing sing Xilinx procedure. THEORY: It reco recogn gniz izes es only only the the word words s that that have have an even even numb number er of ones/zeros. This means that for odd number of ones, output of XNOR gate is LOW. TRUTH TABLE:

A

B

C

0

0

1

0

1

0

1

0

0

1

1

1





























PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity xnorgate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xnorgate; architecture Behavioral of xnorgate is begin c <= a xnor b;





























VHDL CODE FOR NOT GATE AIM: To AIM: To implement NOT gate using using Xilinx procedure. THEORY: The inverter (NOT circuit) performs a basic logic function called “inversion” or “complementation”. The inverter changes one logical level to its opposite level. In terms of bits, it changes logic1 to logic 0 and logic 0 to logic1. TRUTH TABLE: A

B

0

1

1

0





























PROGRAM CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity notgate is Port ( a : in STD_LOGIC; b : out STD_LOGIC); end notgate; architecture Behavioral of notgate is begin b <= not a; end Behavioral;





























EXPERIMENT- 2 VHDL CODE FOR 2x4 DECODER AIM: To design a 2x4 decoder and to simulate in VHDL. THEORY: A decoder is a combinational circuit with multiple input, multiple output logic circuit that converts coded inputs to coded outputs, where the inputs are lesser in number than output codes. The input code is generally has fewer bits than the output code, there is one-to-one mapping from input code words into output code words. in a one-to-one mapping, each input code word produces a different output code word. The general structure of a decoder circuit can be shown as follows. The enable inputs, if present must be asserted for the decoder to perform perform its normal mapping function. Otherwise the decoder maps all the input code words into a single disabled output code word. The corresponding IC number































architecture Behavioral of decoder2x4 is begin process (x) is begin case x is when "00"=> d <="1000";

























































SIMULATION RESULTS FOR 2x4 DECODER:





























VHDL CODE FOR 3x8 DECODER AIM: To design a 3x8 decoder and to simulate in VHDL. TECHNOLOGY SCHEMATIC DIAGRAM FOR 3-8 DECODER:





























d3<= (not a) and b and c; d4<= a and (not b) and (not c); d5<= a and (not b) and c; d6<= a and b and (not c); d7<= a and b and c; end arc; SIMULATION RESULTS FOR 3X8 DECODER:































VHDL CODE FOR DECODER 4X16 USING 2X4





























PROGRAM CODE:





























d1<= ((not p) and (not q) and e);





























EXPERIMENT- 3





























if (en='1') then dout<="000";





































































































































































































































































































































































































































































































































































































































































































SIMULATION RESULTS FOR DECADE COUNTER:



























EXPERIMENT- 10

STATE MACHINE WITH MEALY OUTPUT AIM: To AIM: To implement the state machine machine with melay output using using VHDL. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; entity fsm is port(x,clk:in std_logic; y:out std_logic); end fsm; architecture mealy_case of fsm is type state_type is(reset,got1,got10); is(reset,got1,got10); signal state:state_type:=reset; state:state_type:=reset; begin process(clk) begin if clk='0' then case state is when reset => if x='0' then y<='0';state<=reset; else y<='0';state<=got1; y<='0';state<=got1; end if; when got1 got1 => if x='0' then y<='0';state<=got10; else y<='0';state<=got1; y<='0';state<=got1; end if; when got10 => if x='0' then y<='0';state<=reset; else y<='1';state<=got1; y<='1';state<=got1; end if; end case;



























TECHNOLOGY SCHEMATIC:

SIMULATION RESULTS:

RTL Schematic



























STATE MACHINE WITH MOORE OUTPUT: AIM: To AIM: To implement the state machine machine with melay output using using VHDL. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; entity fsm is port(x,clk : in std_logic; y : out std_logic); end fsm; architecture moore_case of fsm is type state_type is(reset, got1, got10, got101); signal state:state_type:=reset; state:state_type:=reset; begin process(clk) begin if (clk='0') then case state is when reset => if x='0' then state<=reset; else state<=got1; end if; when got1 => if x='0' then state<=got10; state<=got10; else state<=got1; end if; when got10 => if x='0' then state<=reset; else state<=got101; end if;





























state<=got1; end if; end case; end if; if state=got101 then y<='1'; else y<='0'; end if; end process; end moore_case;

SIMULATION RESULTS:





























EXPERIMENT-11 VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM: To design a serial in serial out shift register simulate in VHDL. THEORY: Shift registers are used in digital systems for temporary information storage and for data manipulation or transfer there are two ways to shift data into register i.e., serial or parallel, and similarly two ways of shift data out of register. In this type of shift register, data is stored into the register one bit at a time(serial) and taken out serially .they delay data by one clock time for each stage they will store a bit of data for each register. A serial in serial out shift register may be 1 to 64 bits in length, longer if registers or packages are cascaded. TRUTH TABLE: si X 0 1 0 1

clk rst 1 2 3 4

q 0000 0000 1000 0100 1010

sout X 0 0 0 0

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity shiftregister is





























begin process(rst,clk) begin if(rst='1')then q<="0000"; else if(clk'event and clk='1') then q(3)<=si; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); sout<=q(0); end if; end if; end process; p<=q; end siso; TECHNOLOGY SCHEMATIC:

























































VHDL CODE FOR SERIAL IN PARALLEL OUT SHIFT REGISTER AIM: To design a serial in parallel out shift register and to simulate in VHDL and verify experimentally in digital IC Lab. THEORY: shif shiftt regi regist ster ers s are are used used in digi digita tall syst system ems s for for temp tempor orar ary y inform informati ation on storag storage e and for data data manipu manipulat lation ion or trans transfer fer there there are two ways to shift data into register i.e., serial or parallel, and similarly two ways of shift data out of register. In this type of shift register, data is stored into the register one bit at a time time(s (ser eria ial) l) and and take taken n out out in para parall llel el it make makes s all all the the inte intern rnal al stag stages es available as outputs. If four bits are shifted in by four clock pulses via a single wire ,the data becomes available simultaneously on four outputs. TRUTH TABLE: si X 0 1 0 1

clk rst 1 2 3 4

pout 0000 0000 1000 0100 1010

VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; IEEE.STD_LOGIC_UNSIGNED.ALL; entity shiftregister is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;































if(rst='1')then q<="0000"; else if(clk'event and clk='1') then q(3)<=si; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); end if; end if; end process; pout<=q; end siso;






























SIMULATION RESULTS:





























VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER AIM: To design a serial in serial out shift register and to simulate in VHDL. VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity piso is generic(x : integer := 8); port( din: in std_logic_vector(x-1 std_logic_vector(x-1 downto 0); clk,ld,r,dir_r,se: in std_logic; so: out std_logic ); end piso; architecture rtl of piso is signal pre_q : std_logic_vector((x-1) downto 0) := (others => 'x'); begin shift_register_process: shift_register_process: process(clk,r) begin if (r = '1') then





























end rtl;






























SIMULATION RESULTS:































VHDL CODE FOR SERIAL/PARALLEL IN SERIAL/PARALLEL OUT SHIFT REGISTER

AIM: To design a serial/par serial/parallel allel in serial/par serial/parallel allel out shift shift register and and to simulate in VHDL. VHDL CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity spispo is generic(x : integer := 8); port( din: in std_logic_vector((x-1) std_logic_vector((x-1) downto 0); dout: out std_logic_vector((x-1) downto 0); clk,ld,r,dir_r,se,si: in std_logic;





























so <= pre_q(0) when dir_r = '1' else pre_q((x-1)) when dir_r dir_r = '0' else 'x'; end rtl;






























SIMULATION RESULTS:





























EXPERIMENT-12 ALU AIM: To AIM: To design a ALU performing operations. PROGRAM CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned ieee.std_logic_unsigned.all; .all; use ieee.std_logic_arith.all; entity ALU is por ortt ( A:

in std_lo d_log gic_v ic_vec ecto torr(1 down ownto 0); 0);

B:

in st std_logic_vector(1 do downto 0) 0);

Sel: Sel:

in std std_l _log ogic ic_v _vec ecto tor( r(1 1 down downto to 0); 0);

Res: Res: out std_lo std_logic gic_ve _vecto ctor(1 r(1 down downto to 0) );



























































SIMULATION RESULTS:





























CMOS Layers 

n-well process



p-well process



Twin-tub process process

n-well process





























Top view of the FET pattern





























Interconnect Layout Example





























Parallel Connected MOS Patterning































Alternate Layout of NOT Gate





























NAND2-NOR2 Comparison





























Stick Diagrams

























































Stick Diagram - Example II













































































































































































Ecad & Vlsi Lab(3)

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