Vlsi Lab Manual 2013

LAB MANUAL

VEL TECH MULTI TECH ( ISO 9001: 2000 Certified Institution & NBA Accredited ) (Owned by VEL Sree R.Rangarajan Dr. Sagunthala Rangarajan Educational Academy )

Approved by AICTE, New Delhi & Affiliated to Anna University No 42, Alamathi Road, Near Avadi Chennai Chenn ai – 600 062 \

DEPARTMENT OE ELECTRONICS AND COMMUNICATION ENGINEERING

EC2357 VLSI DESIGN LAB III YEAR / IV SEMESTER ECE

PREPARED BY

VERIFIED BY

ANJO C.A. N.ARUNKUMAR

(HOD/ECE) LIST OF EXPERIMENTS 1

S.NO

NAME OF THE EXPERIMENT

PAGE NO

Desig Design n En Entr try y and simul simulati ation on of combin combinati ationa onall logic logic circ circuit uitss (8 bit bit adders adders,, 4 bit mult mu ltip ipli lier ers, s, addr addres esss deco decode ders rs,, mu mult ltip iple lexe xers rs), ), Test Test benc bench h crea creati tion on,, func functi tion onal al verification, and concepts of concurrent and sequential execution to be highlighted. 1

1a)BASIC GATES 1b)HALF ADDER,FULLADDER 1c)HALF SUBTRACTOR,FULL SUBTRACTOR

2

Design Entry and simulation of sequential logic circuits (counters, PRBS generators, accumulators). Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted. 2a)IMPLEMENTATION OF COUNTERS 2b)IMPLEMENTATION OF 2X4 DECODER AND 4X2 ENCODER

3

Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate count, I/O configuration and pin assignment to be taught in this experiment

4

5

6

Generation of configuration/fuse files for all the blocks/codes developed as part of Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the inputs and outputs for each of the blocks must be demonstrated atleast on oscilloscopes (logic analyzer preferred). Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of gain, bandwidth, output impedance and CMRR.

Layout of a simple CMOS inverter, parasitic extraction and simulation

7

Design of a 10 bit number controlled controlled oscillator oscillator using standard cell approach, simulation followed by study of synthesis reports.

8

Automatic layout generation followed by post layout extraction and simulation of the circuit

2

SYLLABUS EC2357 VLSI DESIGN LAB

1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers, address decoders, multiplexers), multiplexers), Test bench creation, functional verification, verification, and concepts of concurrent and sequential execution to be highlighted.

2. Design Design Entry Entry and simulat simulation ion of sequenti sequential al logic logic circuit circuitss (counter (counters, s, PRBS PRBS generato generators, rs, accumulators). Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted.

3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate count, I/O configuration and pin assignment to be taught in this experiment.

4. Generation of configuration/fuse configuration/fuse files for all the blocks/codes developed developed as part of Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the inputs and outputs for each of the blocks must be demonstrated atleast on oscilloscopes (logic analyzer preferred).

5. Schematic Entry and SPICE SPICE simulation of MOS differential differential amplifier. amplifier. Determination Determination of gain, bandwidth, output impedance and CMRR.

6. Layout of a simple CMOS inverter, parasitic extraction and simulation.

7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation followed by study of synthesis reports.

8. Automa Automatic tic layout layout generat generation ion followe followed d by post layout layout extract extraction ion and simula simulation tion of the circuit BEYOND THE SYLLABUS Layout design of full adder circuit using Microwind. 1. Layout Layout design design of of Multipl Multiplexer exer using using Microwi Microwind. nd.

3

VLSI DESIGN FLOW

• During HDL simulation, the simulator software verifies the functionality and timing of your design or portion of your design. • The simulator interprets VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation. • Simulation allows you to create and verify complex functions in a relatively small amount of time.

Experimental results using simulation tools can be inferred for: 1) functional simulation 2) gate-level simulation 3) post-par simulation on ise simulator

PROCEDURE: 1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator 2. File New Project 3. Enter the Project Name and location then click next 4. Select the Device and other category and click next twice and finish. 5. Click on the symbol of FPGA device and then right click  click on new source. 6. Select the Verilog Module and give the file name click next and define ports click next and finish. 7. Writing the behavioral Verilog Code in Verilog Editor. 8. Run the Check syntax  Process window synthesize double click check syntax  and remove errors, if present, with proper syntax & coding. 9. Click on the symbol of FPGA device and then right click  click on new source. 10. Select the Test Bench Waveform and give the file name  select entity click next and finish. 11. Select the desired parameters for simulating your design. In this case combinational circuit and simulation time click finish. 12. Assign all input signal using just click on graph and save file. 13. From the source process window. Click Behavioral simulation from drop-down menu 14. Select the test bench file (.tbw) and click process button double click the Simulation Behavioral Model 15. Verify your design in wave window by seeing behavior of output signal with respect to input signal. STUDY OF SYNTHESIS TOOLS

4

THEORY:

Synthesis is the process of constructing a gate level netlist from a register-transfer Level model of the circuit described in VHDL, Verilog, or mixed language designs. The netlist files contain both logical design data and constraints . XILINX SYNTHESIS TOOL enables us to study: 1) Utilization of LUTs & Slices 2) I/O Buffer assignment 3) RTL Schematic in gate level 4) Time delay between I/Os and path

PROCEDURE:

1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator 2. File New Project 3. Enter the Project Name and location then click next 4. Select the Device and other category and click next twice and finish 5. Click on the symbol of FPGA device and then right click  click on new source 6. Select the Verilog Module and give the file name click next and define ports click next and finish 7. Writing the behavioral Verilog Code in Verilog Editor. 8. Run the Check syntax  Process window synthesize double click check syntax and remove errors, if present, with proper syntax & coding. 9. Synthesis your design, from the source window select, Synthesis/ implementation from the window Now double click the Synthesis –XST 10. After the HDL synthesis phase of the synthesis process, you can display a schematic representation of your synthesized source file. This schematic shows a representation of the pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates double click View RTL Schematic 11. Double click the schematic to internal view 12. Double click outside the schematic to move one-level back 13. This schematic shows a representation of the design in terms of logic elements optimized to the target device. For example, in terms of LUTs(Look Up Table), carry logic, I/O buffers, and other technology-specific components  Double click View Technology Schematic 14. Double click the schematic to inner view 15. Double click the LUT to inner view. This is Gate Level view of LUT, if you want see Truth Table and K-Map for your design just click the respective tabs. 16. After finishing the synthesis, you can view number of Slices, LUT(Look Up Table), I/Os are taken by your deign in Device using Desi gn summary.

PLACE AND ROUTE AND BACK ANNOTATION FOR FPGA

5

THEORY:

• Back annotation is the translation of a routed or fitted design to a timing simulation netlist. • To define the behavior of the FPGA, a hardware description language (HDL) or a schematic design methods are used. Common HDLs are VHDL and Verilog. T hen, using an electronic design automation (EDA) tool, a technology-mapped netlist is generated. • The netlist can then be fitted to the actual FPGA architecture using a process called placeand-route, usually performed by the FPGA vendor’s proprietary place-and-route software. • The user will validate the map, place and route results via timing analysis, si mulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated is used to (re)configure the FPGA. • In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly • In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. • Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. • Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. • Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. • Place & Route, the process of optimization of logic cells for effective utilization of FPGA area and the speed of operation, is used to modify and infer the following: 1) Re-assignment of Pins 2) Re-location of Slices 3) Run time minimization PROCEDURE:

1. Start the Xilinx ISE by using start Program files Xilinx ISE (8.1i)  project navigator 2. File  New Project3. Enter the Project Name and location then click next 4. Select the Device and other category and click next twice and finish 5. Click on the symbol of FPGA device and then right click  click on new source 6. Select the Verilog Module and give the file name  click next and define ports click next and finish 7. Writing the behavioral Verilog Code in Verilog Editor

6

8. Run the Check syntax

 Process

window

synthesize

double click

check syntax

9. Synthesis your design, from the source window select, synthesis/implementation from the window Now double click the Synthesis -XST

10. After Synthesis you assign the Pin Value for your design so, Package Pins

double

click the Assign

11. Enter the Pin value for your input and output signals. if you want see your Pin assignment in FPGA zoom in Architecture View or Package View 12. You see the Pins in FPGA. Save file as XST Default click ok and close the window 13. Design Implementation begins with the mapping or fitting of a l ogical design file to a specific device and is complete when the physical design is successfully routed and a bit stream is generated. Double Click Implementation Design 14. After implementation you see Design Summary, you get the all details about your design. If you want edit the place and route double click View/Edit placed design

15. You see where your IOs are placed in FPGA. And zoom to view how Pins are placed in FPGA. You can see where your pins are placed 16. Just double click View/Edit Routed Design to view interconnection wires and blocks 17. Click the pin to see where its placed in FPGA. And Zoom particular area to see Place and Routing. 18. If you want to change the place of the design, click and trace to another slice. See!!! You changed place and route of the design 19. Double click Back annotated Pin Location. Once back annotation is completed, constraint file is generated.

GENERATION OF CONFIGURATION/FUSE IN FPGA DEVICES, CONFIGURE AND HARDWARE TESTED FOR THE BLOCKS/CODES . 7

PROCEDURE:

1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator 2. File New Project cli ck next 3. Enter the Project Name and location then click 4. Select the Device and other category and click next twice and finish t hen right click  click on new source 5. Click on the symbol of FPGA device and then 6. Select the schematic and give the file name click next and define ports click next and finish 7. Select the Categories and symbols or type the symbol name 8. Click Add I/O markers Double click the I/O pin Enter the Name and click ok 9. Click Add Add wire button, then made the connections save the schematic. 10. Click the design utilities in process window run the view HDL functional model, to get the program for the schematic. t hen right click  click on new source. 11. Click on the symbol of FPGA device and then 12. Select the Test Bench Waveform and give the file name  select entity click next and finish. 13. Select the desired parameters for simulating your design. In this case combinational circuit and simulation time click finish. 14. Assign all input input signal using just click click on graph and save save file. 15. From the source process window. Click Behavioral Behavioral simulation from drop-down menu process button 16. Select the test bench file (.tbw) and click process

double click the Simulation

Behavioral Model 17. Verify your design in wave window by seeing behavior behavior of output signal with respect to input signal.

8

Fig 1:Waveform Editor - Initialize Timing Dialog Box

1. DESIGN ENTRY AND SIMULATION OF COMBINATIONAL COMBINATIONAL LOGIC CIRCUITS

BASIC LOGIC GATES Expt.No:1a Date

:

AIM: To implement basic logic gates using Verilog HDL APPARATUS REQUIRED: • •

PC with Windows XP. XILINX, ModelSim software.

PROCEDURE:    

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained.

AND Gate:

PROGRAM:

AND Gate: module Andgate(i1, i2, out); input i1; input i2; output out; and (out,i1,i2); endmodule 9

Truth table: AND Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 0 1 0 0 1 1 1 ------------------------------------------------OUTPUT WAVE

OR Gate:

Program: module Orgate(i1, i2, out); input i1; input i2; output out; or(out,i1,i2); endmodule Truth table: OR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 1 1 0 1 1 1 1 ------------------------------------------------

10

Output Wave

NAND Gate:

Program module Nandgate(i1, i2, out); input i1; input i2; output out; nand(out,i1,i2); endmodule Truth table: NAND Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 1 1 0 1 1 1 0 -----------------------------------------------Output Wave:

11

NOR Gate:

Program module Norgate(i1, i2, out); input i1; input i2; output out; nor(out,i1,i2); endmodule Truth table: NOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 0 1 0 0 1 1 0 ------------------------------------------------

Output wave

XOR Gate:

12

Program module Xorgate(i1, i2, out); input i1; input i2; output out; xor(out,i1,i2); endmodule Truth table:

XOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 0 0 1 1 1 0 1 1 1 0 -------------------------------------------------

Output Wave

XNOR Gate:

Program module Xnorgate(i1, i2, out); input i1; input i2; output out; xnor(out,i1,i2); endmodule Truth table: XNOR Gate -----------------------------------------------Input1 Input2 Output -----------------------------------------------0 0 1 0 1 0 1 0 0 1 1 1 13

-----------------------------------------------Output Wave:

Not Gate:

Program module Notgate(in, out); input in; output out; not(out,in); endmodule Truth table: NOT Gate --------------------------Input Output --------------------------0 1 1 0 ---------------------------

Output Wave

Buffer: 14

Program module Buffer(in, out); input in; output out; buf(out,in); endmodule Truth table : BUFFER --------------------------Input Output --------------------------0 0 1 1 ---------------------------

Output Wave:

HALF ADDER AND FULL ADDER Expt. No:1b 15

Date AIM:

:

To implement half adder and full adder using Verilog HDL.

APPARATUS REQUIRED: • •

PC with Windows XP XILINX, ModelSim software.



Half Adder:

Program : module HalfAddr(sum, c_out, i1, i2); output sum; output c_out; input i1; input i2; xor(sum,i1,i2); and(c_out,i1,i2); endmodule

Truth table: Half Adder -----------------------------------------------------------------Input1 Input2 Carry Sum -----------------------------------------------------------------0 0 0 0 0 1 0 1 16

1 0 0 1 1 1 1 0 -----------------------------------------------------------------Output Wave:

Full Adder:

Program: module FullAddr(i1, i2, c_in, c_out, sum); input i1; input i2; input c_in; output c_out; output sum; wire s1,c1,c2; xor n1(s1,i1,i2); and n2(c1,i1,i2); xor n3(sum,s1,c_in); and n4(c2,s1,c_in); or n5(c_out,c1,c2); endmodule

Truth Table:

i1 i2 C_in C_out Sum ---------------------------------------------------------------------------------------------0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 17

0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ----------------------------------------------------------------------------------------------

Output Wave:

HALF SUBTRACTOR & FULL SUBTRACTOR Expt. No:1c Date : AIM: To implement half subtractor and full subtractor using Verilog HDL. APPARATUS REQUIRED: • PC with Windows XP • XILINX, ModelSim software. 18



Halfsubtractor:

Program: module HalfSub(i0, i1, bor, dif); input i0; input i1; output bor; output dif; wire i0n; not(i0n,i0); xor(dif,i0,i1); and(bor,i0n,i1); endmodule Truth Table: Half Subtractor -----------------------------------------------------------------------Input1 Input2 Borrow Difference ------------------------------------------------------------------------0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 ------------------------------------------------------------------------

Output Wave:

19

FULL SUBTRACTOR:

Program: module FullSub(b_in, i1, i0, b_out, dif); input b_in; input i1; input i0; output b_out; output dif; assign {b_out,dif}=i0-i1-b_in; endmodule Truth Table: Full Subtractor B_in I1 i0 B_out Difference ---------------------------------------------------------------------------------------------0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 ----------------------------------------------------------------------------------------------

Output Wave:

20

Following is the Verilog code for an unsigned 8-bit adder/subtractor.

module addsub(a, b, oper, res); input oper; input [7:0] a; input [7:0] b; output [7:0] res; reg [7:0] res; always @(a or b or oper) begin if (oper == 1’b0) res = a + b; else res = a - b; end endmodule Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out. module adder(a, b, ci, sum, co); input ci; input [7:0] a; input [7:0] b; output [7:0] sum; output co; wire [8:0] tmp; assign tmp = a + b + ci; assign sum = tmp [7:0]; assign co = tmp [8]; endmodule

IMPLEMENTATION OF 2 x 4 DECODER AND 4 x 2 ENCODER Expt No:1d Date:

To implement 2 x 4 Decoder and 4 x 2 Encoder Verilog HDL. AIM: APPARATUS REQUIRED: PC with Windows XP. • 21

•

XILINX, ModelSim software.



Encoder:

4x2

Program: module Encd2to4(i0, i1, i2, i3, out0, out1); input i0; input i1; input i2; input i3; output out0; output out1; reg out0,out1; always@(i0,i1,i2,i3) case({i0,i1,i2,i3}) 4'b1000:{out0,out1}=2'b00; 4'b0100:{out0,out1}=2'b01; 4'b0010:{out0,out1}=2'b10; 4'b0001:{out0,out1}=2'b11; default: $display("Invalid"); endcase endmodule

Truth Table:

4to2 Encoder ------------------------------------Input Output ------------------------------------1000 00 0100 01 22

0010 0001 Output Wave:

10 11

Decoder:

2x4

Program: module Decd2to4(i0, i1, out0, out1, out2, out3); input i0; input i1; output out0; output out1; output out2; output out3; reg out0,out1,out2,out3; always@(i0,i1) case({i0,i1}) 2'b00: {out0,out1,out2,out3}=4'b1000; 2'b01: {out0,out1,out2,out3}=4'b0100; 2'b10: {out0,out1,out2,out3}=4'b0010; 2'b11: {out0,out1,out2,out3}=4'b0001; default: $display("Invalid"); endcase endmodule

Truth Table:

2to4 Decoder ------------------------------------Input Output ------------------------------------00 1000 01 0100 23

10 0010 11 0001 -----------------------------------Output Wave:

Following is the Verilog code for a 3-bit 1-of-9 Priority Encoder. module priority (sel, code); input [7:0] sel; output [2:0] code; reg [2:0] code; always @(sel) begin if (sel[0]) code = 3’b000; else if (sel[1]) code = 3’b001; else if (sel[2]) code = 3’b010; else if (sel[3]) code = 3’b011; else if (sel[4]) code = 3’b100; else if (sel[5]) code = 3’b101; else if (sel[6]) code = 3’b110; else if (sel[7]) code = 3’b111; else code = 3’bxxx; end endmodule Following is the Verilog code for a logical shifter. module lshift (di, sel, so); input [7:0] di; input [1:0] sel; output [7:0] so; reg [7:0] so; always @(di or sel) 24

begin case (sel) 2’b00 : so = di; 2’b01 : so = di << 1; 2’b10 : so = di << 2; default : so = di << 3; endcase end endmodule Following is the Verilog code for a 1-of-8 decoder. module mux (sel, res); input [2:0] sel; output [7:0] res; reg [7:0] res; always @(sel or res) begin case (sel) 3’b000 : res = 8’b00000001; 3’b001 : res = 8’b00000010; 3’b010 : res = 8’b00000100; 3’b011 : res = 8’b00001000; 3’b100 : res = 8’b00010000; 3’b101 : res = 8’b00100000; 3’b110 : res = 8’b01000000; default : res = 8’b10000000; endcase end endmodule

MULTIPLEXER & DEMULTIPLEXER Expt. No:1e Date : AIM: To implement Multiplexer & Demultiplexer using Verilog HDL. APPARATUS REQUIRED: PC with Windows XP. • XILINX, ModelSim software. • PROCEDURE:

Write and draw the Digital logic system.  Write the Verilog code for above system.  Enter the Verilog code in Xilinx software.. Multiplixer: 

25

Program: Using if statement: module mux (a, b, c, d, s, o); input a,b,c,d; input [1:0] s; output o; reg o; always @(a or b or c or d or s) begin if (s == 2’b00) o = a; else if (s == 2’b01) o = b; else if (s == 2’b10) o = c; else o = d; end endmodule]

Using Case statement:

module mux (a, b, c, d, s, o); input a, b, c, d; input [1:0] s; output o; reg o; always @(a or b or c or d or s) begin case (s) 2’b00 : o = a; 26

2’b01 : o = b; 2’b10 : o = c; default : o = d; endcase end endmodule Truth Table:

4to1 Multiplexer ----------------------------------------------Input=1011 ----------------------------------------------Selector Output ----------------------------------------------{0,0} 1 {1,0} 0 {0,1} 1 {1,1} 1 ----------------------------------------------Output Wave:

Demultiplexer:

Program: module Dux1to4(in, s0, s1, out0, out1, out2, out3); input in; input s0; input s1; output out0; 27

output out1; output out2; output out3; wire s0n,s1n; not(s0n,s0); not(s1n,s1); and (out0,in,s1n,s0n); and (out1,in,s1n,s0); and (out2,in,s1,s0n); and (out3,in,s1,s0); endmodule Truth Table: Demultiplexer ----------------------------------------------Input=1 ----------------------------------------------Status Output ----------------------------------------------{0,0} 1000 {0,1} 0100 {1,0} 0010 {1,1} 0001

Output Wave:

28

RESULT: Thus the verilog code for combinational logic circuits has been simulated and verified. 2.DESIGN ENTRY AND SIMULATION OF SEQUENTIAL LOGIC CIRCUITS FLIP-FLOPS Expt.No:2a Date :

To implement Flipflops using Verilog HDL. AIM: APPARATUS REQUIRED: PC with Windows XP. • XILINX, ModelSim software. • PROCEDURE:    

Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained.

D Flip-Flop:

D-FF

Program: module DFF(Clock, Reset, d, q); input Clock; input Reset; input d; 29

output q; reg q; always@(posedge Clock or negedge Reset) if (~Reset) q=1'b0; else q=d; endmodule

Truth Table: D FipFlop

-------------------------------------------------------------------------Clock Reset Input (d) Output q(~q) --------------------------------------------------------------------------0 0 0 0(1) 1 0 0 0(1) 0 0 1 0(1) 1 0 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 1 0 1(0) 1 1 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 0 0 0(1) 1 0 0 0(1) 0 0 0 0(1) --------------------------------------------------------------------------

Output Wave:

T Flip-Flop: 30

T-

Program: module TFF(Clock, Reset, t, q); input Clock; input Reset; input t; output q; reg q; always@(posedge Clock , negedge Reset) if(~Reset) q=0; else if (t) q=~q; else q=q; endmodule

T FipFlop --------------------------------------------------------------------------Clock Reset Input (t) Output q(~q) --------------------------------------------------------------------------0 0 0 0(1) 1 0 0 0(1) 0 0 1 0(1) 1 0 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 1 1 0(1) 1 1 1 1(0) 0 1 0 1(0) 1 1 0 1(0) 0 1 1 1(0) 1 1 1 0(1) 0 0 0 0(1) 1 0 0 0(1) 0 0 0 0(1) -------------------------------------------------------------------------Output Wave:

Truth Table:

31

JK Flip-Flop:

JK-FF

Program : module JKFF(Clock, Reset, j, k, q); input Clock; input Reset; input j; input k; output q; reg q; always@(posedge Clock, negedge Reset) if(~Reset)q=0; else begin case({j,k}) 2'b00: q=q; 2'b01: q=0; 2'b10: q=1; 2'b11: q=~q; endcase end endmodule

Truth Table:

JK FipFlop -------------------------------------------------------------------------Clock Reset Input (j,k) Output q(~q) -------------------------------------------------------------------------0 0 (0,0) 0(1) 1 0 (0,0) 0(1) 0 0 (0,1) 0(1) 1 0 (0,1) 0(1) 0 0 (1,0) 0(1) 1 0 (1,0) 0(1) 0 0 (1,1) 0(1) 1 0 (1,1) 0(1) 0 1 (0,0) 0(1) 1 1 (0,0) 0(1) 0 1 (0,1) 0(1) 1 1 (0,1) 0(1) 0 1 (1,0) 0(1) 32

1 1 (1,0) 1(0) 0 1 (1,1) 1(0) 1 1 (1,1) 0(1) 0 0 (0,0) 0(1) 1 0 (0,0) 0(1) 0 0 (0,0) 0(1) -------------------------------------------------------------------------

Output Wave:

VERILOG CODE FOR 4BIT MULTIPLIER module unsigned_mult (out, a, b); output [7:0] out; input [3:0] a; input [3:0] b;

assign out = a * b; endmodule

33

IMPLEMENTATION OF COUNTERS Expt No:2b Date:

To implement Counters using Verilog HDL AIM: APPARATUS REQUIRED: PC with Windows XP. • XILINX, ModelSim software. •


Write and draw the Digital logic system. Write the Verilog code for above system. Enter the Verilog code in Xilinx software. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained.

Counter:

2-BIT

Program:

module Count2Bit(Clock, Clear, out); input Clock; input Clear; output [1:0] out; reg [1:0]out; always@(posedge Clock, negedge Clear) if((~Clear) || (out>=4)) out=2'b00; 34

else out=out+1; endmodule

Truth Table:

2 Bit Counter --------------------------------------------------Clock Clear Output[2] --------------------------------------------------0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 0 00 1 0 00 0 1 00 1 1 01 0 1 01 1 1 10 0 1 10 1 1 11 0 1 11 1 1 00 0 1 00 1 1 01 0 1 01 1 1 10 0 1 10 1 1 11 0 1 11 1 1 00 0 0 00 1 0 00 ------------------------------------------------

Output Wave: 35

Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear. module counter (clk, clr, q); input clk, clr; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4’b0000; else tmp <= tmp + 1’b1; end assign q = tmp; endmodule Following is the Verilog code for a 4-bit unsigned down counter with synchronous set.

module counter (clk, s, q); input clk, s; output [3:0] q; reg [3:0] tmp; always @(posedge clk) begin if (s) tmp <= 4’b1111; else tmp <= tmp - 1’b1; end assign q = tmp; endmodule Following is the Verilog code for an unsigned 8-bit adder with carry in. module adder(a, b, ci, sum) input [7:0] a; input [7:0] b; input ci; output [7:0] sum; assign sum = a + b + ci; endmodule Following is the Verilog code for an unsigned 8-bit adder with carry out. 36

module adder(a, b, sum, co); input [7:0] a; input [7:0] b; output [7:0] sum; output co; wire [8:0] tmp; assign tmp = a + b; assign sum = tmp [7:0]; assign co = tmp [8]; endmodule

PRBS Generator prbs.v module prbs (rand, clk, reset); input clk, reset; output rand; wire rand; reg [3:0] temp; always @ (posedge reset) begin temp <= 4'hf; end always @ (posedge clk) begin if (~reset) begin temp <= {temp[0]^temp[1],temp[3],temp[2],temp[1]}; end end assign rand = temp[0]; endmodule

37

RESULT: Thus the verilog code for sequential logic circuits has been simulated and verified.

3.STUDY OF SYNTHESIS TOOLS THEORY:

Synthesis is the process of constructing a gate level netlist from a register-transfer Level model of the circuit described in VHDL, Verilog, or mixed language designs. The netlist files contain both logical design data and constraints . XILINX SYNTHESIS TOOL enables us to study: 1) Utilization of LUTs & Slices 2) I/O Buffer assignment 3) RTL Schematic in gate level 4) Time delay between I/Os and path

PROCEDURE:

17. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator 18. File New Project 19. Enter the Project Name and location then click next 20. Select the Device and other category and click next twice and finish 21. Click on the symbol of FPGA device and then right click  click on new source 22. Select the Verilog Module and give the file name click next and define ports click next and finish 23. Writing the behavioral Verilog Code in Verilog Editor. 24. Run the Check syntax  Process window synthesize double click check syntax and remove errors, if present, with proper syntax & coding. 25. Synthesis your design, from the source window select, Synthesis/ implementation from the window Now double click the Synthesis –XST 26. After the HDL synthesis phase of the synthesis process, you can display a schematic representation of your synthesized source file. This schematic shows a representation of the pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates double click View RTL Schematic 27. Double click the schematic to internal view 28. Double click outside the schematic to move one-level back 29. This schematic shows a representation of the design in terms of logic elements optimized to the target device. For example, in terms of LUTs(Look Up Table), carry logic, I/O buffers, and other technology-specific components  Double click View Technology Schematic 38

30. Double click the schematic to inner view 31. Double click the LUT to inner view. This is Gate Level view of LUT, if you want see Truth Table and K-Map for your design just click the respective tabs. 32. After finishing the synthesis, you can view number of Slices, LUT(Look Up Table), I/Os are taken by your deign in Device using Desi gn summary.

3.(a) PLACE AND ROUTE AND BACK ANNOTATION FOR FPGA THEORY:

• Back annotation is the translation of a routed or fitted design to a timing simulation netlist. • To define the behavior of the FPGA, a hardware description language (HDL) or a schematic design methods are used. Common HDLs are VHDL and Verilog. T hen, using an electronic design automation (EDA) tool, a technology-mapped netlist is generated. • The netlist can then be fitted to the actual FPGA architecture using a process called placeand-route, usually performed by the FPGA vendor’s proprietary place-and-route software. • The user will validate the map, place and route results via timing analysis, si mulation, and other verification methodologies. Once the design and validation process is complete, the binary file generated is used to (re)configure the FPGA. • In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly • In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. • Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. • Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. • Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. • Place & Route, the process of optimization of logic cells for effective utilization of FPGA area and the speed of operation, is used to modify and infer the following: 1) Re-assignment of Pins 2) Re-location of Slices 3) Run time minimization PROCEDURE:

1. Start the Xilinx ISE by using start Program files Xilinx ISE (8.1i)  project navigator 2. File  New Project3. Enter the Project Name and location then click next

39

4. Select the Device and other category and click next twice and finish 5. Click on the symbol of FPGA device and then right click  click on new source 6. Select the Verilog Module and give the file name  click next and define ports click next and finish 7. Writing the behavioral Verilog Code in Verilog Editor 8. Run the Check syntax

 Process

window

synthesize

double click

check syntax

9. Synthesis your design, from the source window select, synthesis/implementation from the window Now double click the Synthesis -XST

10. After Synthesis you assign the Pin Value for your design so, Package Pins

double

click the Assign

11. Enter the Pin value for your input and output signals. if you want see your Pin assignment in FPGA zoom in Architecture View or Package View 12. You see the Pins in FPGA. Save file as XST Default click ok and close the window 13. Design Implementation begins with the mapping or fitting of a l ogical design file to a specific device and is complete when the physical design is successfully routed and a bit stream is generated. Double Click Implementation Design 14. After implementation you see Design Summary, you get the all details about your design. If you want edit the place and route double click View/Edit placed design

15. You see where your IOs are placed in FPGA. And zoom to view how Pins are placed in FPGA. You can see where your pins are placed 16. Just double click View/Edit Routed Design to view interconnection wires and blocks 17. Click the pin to see where its placed in FPGA. And Zoom particular area to see Place and Routing. 18. If you want to change the place of the design, click and trace to another slice. See!!! You changed place and route of the design 19. Double click Back annotated Pin Location. Once back annotation is completed, constraint file is generated.

40

4.GENERATION OF CONFIGURATION/FUSE IN FPGA DEVICES, CONFIGURE AND HARDWARE TESTED FOR THE BLOCKS/CODES .

PROCEDURE:

18. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator 19. File New Project 20. Enter the Project Name and location then click next 21. Select the Device and other category and click next twice and finish 22. Click on the symbol of FPGA device and then right click  click on new source 23. Select the schematic and give the file name click next and define ports click next and finish 24. Select the Categories and symbols or type the symbol name 25. Click Add I/O markers Double click the I/O pin Enter the Name and click ok 26. Click Add wire button, then made the connections save the schematic. 27. Click the design utilities in process window run the view HDL functional model, to get the program for the schematic. 28. Click on the symbol of FPGA device and then right click  click on new source. 29. Select the Test Bench Waveform and give the file name  select entity click next and finish. 30. Select the desired parameters for simulating your design. In this case combinational circuit and simulation time click finish. 31. Assign all input signal using just click on graph and save file. 32. From the source process window. Click Behavioral simulation from drop-down menu

33. Select the test bench file (.tbw) and click process button

double click the Simulation

Behavioral Model 34. Verify your design in wave window by seeing behavior of output signal with respect to input signal.

41

DESIGN AND SIMULATION OF EMITTER FOLLOWER AND DIFFERENTIAL AMPLIFIER

Ex. No:5 Date:

AIM

To design and simulate the emitter follower and differential amplifier circuits. SOFTWARE USED

Tanner EDA Tools (i) (ii) (iii)

S-Edit T-Edit W-Edit

THEORY: Differential amplifier:

Differential Amplifier amplifies the current with very little voltage gain. It consists of two FETs connected so that the FET sources are connected together. The common source is connected to a large voltage source through a large resistor Re, forming the "long tail" of the name, the long tail providing an approximate constant current source. The higher the resistance of the current source Re, the lower Ac is, and the better the CMRR. In more sophisticated designs, a true (active) constant current source may be substituted for the long tail. The output from a differential amplifier is itself often differential.

Emitter follower:

Common-Collector (Emitter Follower) amplifier is one of three basic single-stage bipolar junction transistor (BJT) amplifier topologies, typically used as a voltage buffer. In this circuit the base terminal of the transistor serves as the input, the emitter the output, and the collector is common to both. The common collector circuit can be shown to have a voltage gain of almost unity. Base-emitter voltage in the bipolar transistor is very insensitive to bias changes, so any change in base voltage is directed to the emitter.

42

CIRCUIT DIAGRAM: DIFFERENTIAL AMPLIFIER:

PROCEDURE:

1. Open a schematic editor(S-Edit) from the Tanner EDA Tools. 2. Select the required components from the symbol browser and design given circuit using S-Edit. 3. Write the program in T-Edit and run the simulation to simulate the given program to view the result. 4. Output waveform is viewed in the waveform viewer.

PROGRAM: DIFFERENTIAL AMPLIFIER

.model pmos pmos .model nmos nmos .tran 1m 2m 43

.print in1 in2 out1 out2

EMITTER FOLLOWER

.model npn npn .tran 1m 5m .print in out EMITTER FOLLOWER:

SIMULATION REPORT: DIFFERENTIAL AMPLIFIER:

T-Spice - Tanner SPICE Version 10.01 Network license from: LAB1-1 Product Release ID: Copyright (c) 1993-2004 Tanner Research, Inc. 44

Parsing "C:\Documents and Settings\students\My Documents\Module0.sp" Probing options: probefilename = File0.dat probesdbname = C:\Documents and Settings\students\My Documents\diffamp.sdb probetopmodule = Module0 Device and node counts: MOSFETs - 4

MOSFET geometries - 2

BJTs - 0

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 0 Inductors - 0 Transmission lines - 0 Voltage sources - 3

Resistors - 0 Mutual inductors - 0 Coupled transmission lines - 0 Current sources - 1

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0

Macro devices - 0

External C model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 7

Boundary nodes - 4

Total nodes - 11

SIMULATION STATISTICS:

* DC operating point * Total DC operating points

=1

* Total Newton iterations

= 35

* Total Current evaluations

= 180

* Transient analysis * Transient timesteps

= 422

* Successful timesteps

= 408 45

* Failed timesteps

= 14

* Newton non-convergence failures

= 14

* Delta voltage (dv) failures

=0

* Newton iterations

= 863

* Successful Newton iterations

= 709

* Failed Newton iterations

= 154

* Average Newton iterations/timestep

= 2.045

* Average Newton iterations/success

= 1.738

* Current evaluations

= 2519

* Matrix statistics:

OP

TRAN

* Matrix factors

35

863

* Matrix solves * Size

35 7

863

7

* Initial elements

23

27

* Final elements

25

27

* Fill-ins

2

* Initial density

48.92%

55.10%

* Final density

52.89%

55.10%

* Total current evaluations

= 2699


= 898

* Total matrix factorizations

= 898

* Total matrix-vector solves

= 898

* Total matrix solve time (seconds)

0

= 0.015

* T-Spice process times * Newton solver

0.03 seconds


0.02 seconds

* Jacobian construction

0.00 seconds

* Linear solver

0.01 seconds

Parsing

0.00 seconds

Setup

0.00 seconds 46

DC operating point

0.00 seconds

Transient Analysis

4.39 seconds

Overhead

8.11 seconds -----------------------------------------

Total

12.50 seconds

Simulation completed

EMITTER FOLLOWER:

T-Spice - Tanner SPICE Version 10.01 Network license from: LAB1-1 Product Release ID: Copyright (c) 1993-2004 Tanner Research, Inc. Parsing "C:\Documents and Settings\students\My Documents\emitterfollower.sdb" Probing options: probefilename = File0.dat probesdbname = C:\Documents and Settings\students\My Documents\File0.sdb probetopmodule = Module0 Device and node counts: MOSFETs - 0

MOSFET geometries - 0

BJTs - 1

JFETs - 0

MESFETs - 0

Diodes - 0

Capacitors - 2 Inductors - 0 Transmission lines - 0 Voltage sources - 2

Resistors - 4 Mutual inductors - 0 Coupled transmission lines - 0 Current sources - 0

VCVS - 0

VCCS - 0

CCVS - 0

CCCS - 0

V-control switch - 0

I-control switch - 0 47

Macro devices - 0

External C model instances - 0

Subcircuits - 0

Subcircuit instances - 0

Independent nodes - 3

Boundary nodes - 3

Total nodes - 6 SIMULATION STATISTICS:

* DC operating point * Total DC operating points

=1


= 46

* Total Current evaluations

= 127

* Transient analysis * Transient timesteps

= 80

* Successful timesteps

= 80

* Failed timesteps

=0

* Newton non-convergence failures

=0

* Delta voltage (dv) failures

=0

* Newton iterations

= 80

* Successful Newton iterations

= 80

* Failed Newton iterations

=0

* Average Newton iterations/timestep

= 1.000

* Average Newton iterations/success

= 1.000


= 161

* Matrix statistics:

OP

TRAN

* Matrix factors

46

80

* Matrix solves * Size

46 3

80

3

* Initial elements

5

7

* Final elements

5

7

* Fill-ins

0

* Initial density

55.56%

0 77.78% 48

* Final density

55.56%

* Total current evaluations

= 288


= 126

* Total matrix factorizations

= 126

* Total matrix-vector solves

= 126

* Total matrix solve time (seconds)

77.78%

=0

* T-Spice process times * Newton solver

0.00 seconds


0.00 seconds

* Jacobian construction

0.00 seconds

* Linear solver

0.00 seconds

Parsing

0.05 seconds

Setup

0.00 seconds

DC operating point

0.00 seconds

Transient Analysis

0.01 seconds

Overhead

4.81 seconds -----------------------------------------

Total

4.87 seconds

Simulation completed

WAVEFORM: DIFFERENTIAL AMPLIFIER:

49

EMITTER FOLLOWER:

RESULT:

The design and simulation of Differential Amplifier and Emitter Follower has been performed using Tanner EDA Tools.

LAYOUT DESIGN FOR CMOS INVERTER Ex. No: 6 Date: 50

Aim:

To draw the layout of an CMOS inverter using L-Edit of Tanner EDA tools.

SOFTWARE USED

Tanner EDA Tools

L-Edit

DESCRIPTION

CMOS INVERTER

The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS) device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting (switch closed) while the bottom transistor behaves like an open circuit. Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V).

PROCEDURE

1. Open layout Editor (L-Edit) from Tanner EDA tools. 2. Select a New file and enter the File type and enter the cell name in the new cell section. 3. Making use of the pallets in L-edit draw the required layers for the Layout. 4. Each Layer should be based on the Lambda rules. 5. Check for DRC for any error at each level of Layer.

LAYOUT DIAGRAM

51

STICK DIAGRAM

CIRCUIT DIAGRAM 52

DESIGN RULES: Layer Rule Explanation well (CWN, CWP) 1.1 minimum width 1.2 minimum space (different potential, a hot well) 1.3 minimum space (same potential) 1.4 minimum space (different well type) active (CAA) 2.1/2.2 minimum width/space 2.3 source/drain active to well edge space 2.4 substrate/well contact active to well edge space 2.5 minimum space between active poly (CPG) 3.1/3.2 minimum width/space 3.3 minimum gate extension of active 3.4 minimum active extension of poly 3.5 minimum field poly to active space select (CSN, CSP) 4.1 minimum select spacing to channel of transistor 1 4.2 minimum select overlap of active 4.3 minimum select overlap of contact 4.4 minimum select width and spacing 2 active contact 6.1.a exact contact size 6.2.a minimum active overlap 6.3.a minimum contact spacing 6.4.a minimum space to gate of transistor

Value / l 10 9 0 or 6 0 3 5 3 0 or 4 2 2 3 1 3 2 1 2 2¥2 1.5 2 2

L-EDIT DRC SUMMARY REPORT

53

EXECUTION SUMMARY

Execution Start Time L-Edit Version Rule Set Name Tight Metal

MOSIS/HP 1.0U SCN3M,

File name Inverter.tdb

E:\Batch4\L-Edit 11.0\CMOS

Cell Name

Students

Computer Name

LAB1-2

Memory used at start

11.3M

DRC JOB RESULTS SUMMARY

Total DRC errors Generated

0

CPU Time

00:00:11

Real Time

00:00:11

Rules Executed

80

L-Edit DRC Log:-

Running DRC Standard Rule Set

Rule Set Name

MOSIS/HP 1.0U SCN3M, Tight Metal

Execution Start Time

INPUT LAYER SUMMARY

Layer Name Active

Object Count

Flattened

4

4

Active Contact Cap Well

6 0

6 0 54

Metal 1 Metal 1-Tight

12 0

0

Metal 2 Metal 2-Tight

12

0

0

0

0

Metal 3

0

0

N Select

2

2

N Well

1

1

Overglass

0

0

P Select

2

2

Pad Comment

0

0

Poly

3

3

Poly Contact

0

0

Resistor ID

0

Via 1

0

0

Via 2

0

0

0

DISABLED RULES:-

1.2 Well to Well (Different Potential) Spacing – Not Checked 2.5 Covered in 4.2 active from different implant 10.1a Bonding Area: Overglass (88X88um) 10.4 Pad to Unrelated-Metal 2 Space (30um) 10.5a Pad to Unrelated-Metal 1 (15um) 10.5b Pad to Unrelated-Poly Space (15um) 10.5c Pad to Unrelated-Act Space (15um) 18.3 Active Overlap of well-Cap-Poly (Covered by Other rules) 18.4 PolyCnt to Well-Cap Active (Covered by other rules) Acute Angles

0 55

All Angle Edges

0

Offgrid

Disabled

Zero-Width wires

0

Polygons with over 199 Vertices

0

Wires with over 200 vertices

0

Self intersections

0

Wire Join/End styles

0

CELL WITH ERRORS FOUND:-

RESULTS SUMMARY

DRC Errors generated

0

CPU Time

00:00:11

Real Time

00:00:11

Input Object

30 (30)

Rules executed

80

Geometry Flags Executed

7

Disabled Rules

9

MOS LAYOUT

We use MICROWIND2 to draw the MOS layout and simulate its behavior. Go to the directory in which the software has been copied (By default MICROWIND2). Double-click on the MicroWind2 icon. The MICROWIND2 display window includes four main windows: the main menu, the layout display window,the icon menu and the layer palette. The layout window features a grid, scaled in lambda ( ) units. The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a CMOS 6metal layers 0.25μm technology, consequently lambda is 0.125 μm.

56

Analog Simulation

Click on Simulate à Start Simulation . The timing diagrams of the nMOS device appear

57

58

RESULT:

Thus the Layout design of a CMOS inverter has been drawn and checked for DRC using L-Edit of Tanner EDA Tools.

Design of 10-bit controlled Oscillator Ex no:7 Date:

Aim: To design a 10-bit controlled Oscillator by using S-Edit software.

Apparatus Required: • •

S-Edit Computer

59

Procedure:

•

•

•

•

Open the S-Edit by using startProgramss-edit V13.0. Choose the file then give Ok.

NewNew

designFile Name and

Select addbrowseClick on My Document TannerEDAClick LibrariesAllClick OK. In the main menu ClickCellNew viewWindow ill appear .

•

Construct the circuit as per circuit diagram.

•

Click Check view and hierarchy for verification.

•

Simulate the circuit press the Play button and the output has obtained.

Circuit Diagram:

60

Simulation output:

61

Result: Thus the design of 10-bit controlled Oscillator has been simulated and verified the output.

AUTOMATIC LAYOUT GENERATION OF THE INVERTER Ex no:8 Date: In this paragraph, the procedure to create automatic layout generation of the layout of a CMOS inverter is described. Click the icon “MOS generator” on the palette. The following window appears. The proposes size is 1.25μm for the width, 0.25μm for the length. Simply click “Generate Device”, and click on the middle of the screen to fix the MOS device. Click again the icon “MOS generator” on the palette. Change the type of device by a tick on “p62

channel”, and click “Generate Device”. Click on the top of the nMOS to fix the pMOS device.

HOW TO SIMULATE

1. Start Microwind2. By default the software is configured with 0.25μm technology. Click “File èOpen”. 2. Select “INV3”. Click “Simulateè Process section in 2D”. 3. Draw a line representing the location for 2D-process view. The 2D view

appears.Click “OK”. 4. Click “Simulate è Start Simulation”. Observe the oscillator frequency. 5. Click “File èSelect Foundry”. Select “ams08.rul” (0.8μm technology). 6. Ask again for the 2D view. Observe the change in the process aspect. 7. Ask again for analog simulation. Observe the change in frequency and voltage supply. LAYOUT FOR CMOS INVERTER

63

Vlsi Lab Manual 2013

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