VLSI Lab Viva quest ions and answers 1. What is Intrinsic and Extrinsic Semiconductor?
The The pur e Silicon ilicon i iss known a known ass Int Intr insic nsic Semiconduc iconducttor. Whe When impur impur ity it y is is added added with ith pur e Silicon, ilicon, it itss electr electr ical proper ical proper ties ties ar ar e var ied. ied. This i This iss known a known ass Ext Extr insic nsic Semiconduc iconducttor. 2. What is CMOS Technology?
The The f a br ication ication of an IC usi us in C!"S tr ansi nsistors is known as C!"S Techno echnolloy. C!"S C!"S tr ansi nsistor is not nothin but an inver ter, ter, made up of an n#!"S and p#!"S tr ansi nsistor connecte onnected d in se ser ies. ies. 3. i!e the ad!antages o" CMOS o" CMOS IC?
$ Si%e is is less le ss $ &ih Spee Speed $ 'ess (ower )iss (ower )issii pati pation on #. What are "our generations o" Int o" Integration Circuits?
$ SSI *Small *Small Scale Inte Inter r ation+ ation+ $ !SI *!e *!edium Scale Inte Inter r ation+ ation+ $ 'SI *'a *'are Scale Inte Inter r ation+ ation+ $ 'SI *ery 'are Scale Inte Inter r ation+ ation+ $. i!e the !ariety o" Int o" Integrated Circuits?
$ !or e Speciali%e Speciali%ed d Cir cuits its $ -pplicati -pplication on Speci Specif f ic ic Inte Inter r ated ated Cir cuits its *-SICs+ $ Syste Systems#"n#Chips ms#"n#Chips %. Why &MOS technology is 're" erre erred more than (MOS technology?
#c #channel nnel tr t r ansi nsistors have r eater eater swi switc tchin hin spee speed whe when comp compaar ed to to (!"S t (!"S tr r ansi nsistors. &ence &ence,, !"S i !"S iss pr ef err ed th t ha n (!"S. ). What are the di"" ere erent MOS layers?
$ n#di n#diffusi ffusion $ p#di p#diffusi ffusion $ (ol (olysilic ysilicon on $ !etal *. What are the di"" ere erent layers in MOS transistor? Page 1
VLSI Lab Viva quest ions and answers The The lay la yers a rs ar r e Subst Substr ate, ate, diffuse diffused )r ain ain / Sour ce, ce, Insulat Insulator or *S *Sii"0+ / 1ate 1ate..
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+. What are the di"" erent o'erating regions "or an MOS transistor?
$ Cutoff 2 eion $ on# Satur ated *'inear+ 2 eion $ Satur ated 2 eion 1,. What is Enhancement mode transistor?
The device that is normally cut#off with %ero ate bias is called Enhancement mode tr ansistor. 11. What is -e'letion mode de!ice?
The )evice that conducts with %ero ate bias is called )epletion mode device. 12. When the channel is said to e 'inched o""?
If a lare ds is a pplied, this voltae will deplete the inversion layer. This oltae eff ectively pinches off the channel near the dr ain. 13. What are the ste's in!ol!ed in manu"acturing o" IC?
$ Silicon waf er (r e par ation $ Epitaxial 1rowth $ "xidation $ (hoto#lithor a phy $ )iffusion $ Ion Implantation $ Isolation techni3ue $ !etalli%ation $ -ssembly processin / (ackain 1#. What is meant y E'itaxy?
Epitaxy means arr anin atoms in sinle crystal f ashion upon a sinle crystal substr ate. 1$. What are the 'rocesses in!ol!ed in 'hoto lithogra'hy?
*4+ !ask in process *0+ (hoto etchin process. These ar e impor tant processes involved in photolithor a phy. 1%. What is the 'ur'ose o" mas/ ing in "arication o" IC?
!ask in is used to identify the location in which Ion#Implantation should not take place. 1). What lire the materials used "or mas/ ing?
(hoto r esist, Si50, Si , (oly Silicon.
1*. What are the ty'es o" (hoto etching?
Wet etchin and dry etchin ar e the types of photo etchin. 1+. What is di""usion 'rocess? What are do'ing im'urities?
)iffusion is a process in which impur ities ar e diffused into the Silicon chip at 4555 C temper atur e 2,. What is Ion0Im'lantation 'rocess?
It is process in which the Si mater ial is doped with an impur ity by mak in the acceler ated impur ity atoms to str ike the Si layer at hih temper atur e. 21. What are the !arious Silicon a" er (re'aration?
$ Crystal rowth / dopin $ Inot tr immin / r indin $ Inot slicin $ Waf er polishin / etchin $ Waf er cleanin. 22. What are the di"" erent ty'es o" oxidation?
The two types of oxidation ar e )ry / Wet "xidation. 23. What is Isolation?
It is a process used to provide electr ical isolation between diff er ent components and inter connections. 2#. i!e the di"" erent ty'es o" CMOS 'rocess?
$ p#well process $ n#well process $ twin#tub process $ S"I process 2$. What is Channel0sto' Im'lantation?
In n#well f a br ication, n#well is protected with the r esist mater ial. *6ecause, it should not be aff ected dur in 6oron implantation+. Then 6oron is implanted exce pt n#well. The a bove said process is done usin photo r esist mask. This type of implantation is known as Channel#stop implantation. 2%. What is OCOS?
'"C"S mean 'ocal "xidation of Silicon. This is one type of oxide construction.
2). What is SWMI?
SW-!I means Side Wall !asked Isolation. It is used to r educe bird7s beak eff ect.
2*. What is --?
')) means 'ihtly )oped )r ain Structur es. It is used for implantation of n# r eion in n#well process. 2+. What is Tin0tu 'rocess? Why it is called so?
Twin#tub process is one of the C!"S technoloies. Two wells *the other name for well is Tub+ ar e cr eated in this process. So, because of these two tubs, this process is known as Twin# tub process. 3,. What are the ste's in!ol!ed in tin0tu 'rocess?
$ Tub 8ormation $ Thin#oxide Construction $ Sour ce / )r ain Implantation $ Contact cut def inition $ !etalli%ation. 31. What are the s'ecial " eatures o" Tin0tu 'rocess?
In Twin#tub process, Thr eshold voltae, body eff ects of n and p devices ar e independently optimi%ed. 32. What are the ad!antages o" Tin0tu 'rocess?
-dvantaes of Twin#tub process ar e *4+ Se par ate optimi%ed wells ar e availa ble. *0+ 6alanced performance is obtained for n and p tr ansistors. 33. What is SOI? What is the material used as Insulator?
S"I means Silicon#on#Insulator. In this process, a Silicon based tr ansistor is built on an insulatin mater ial like Sa pphir e or Si"0. 3#. What are the ad!antages and disad!antages o" SOI 'rocess?
-dvantaes of S"I process9 4. Ther e is no well formation in this process. 0. Ther e is no f ield# Inversion problem. :. Ther e is no body eff ect problem. )isadvantaes of S"I process9 4. It is very diff icult to protect inputs in this process. 0. )evice ain is low. :. The couplin ca pacitance between wir es always exists. 3$. What are the ad!antages o" CMOS 'rocess?
$ 'ow Input Impedance $ 'ow delay Sensitivity to load. 3%. What are the !arious etching 'rocesses used in SOI 'rocess?
ar ious etchin processes used in S"I ar e, )ry and Wet etchin
3). What is 4iCMOS Technology?
It is the combination of 6i polar technoloy / C!"S technoloy. 3*. What are the asic 'rocessing ste's in!ol!ed in 4iCMOS 'rocess?
-dditional masks def inin ( base r eion $ Collector ar ea $ 6ur ied Sub collector *SCC)+ $ (rocessin ste ps in C!"S process 3+. What is meant y interconnect? What are the ty'es are o" interconnect?
Inter connect means connection between var ious components in an IC. Types of Inter connect9 4. !etal Inter connect 0. (olySilicon Inter connect :. 'ocal Inter connect. #,. What is Silicide?
The combination of Silicon and tantaleum is known as Silicide. It is used as ate mater ial in (olysilicon Inter connect. #1. What is (olycide?
The combination of Silicide and (olysilicon is known as (olycide. It is used as ate mater ial. #2. What is Stic/ diagram?
The diar am which conveys the layer information throuh the use of var ious colours is known as Stick diar am. It is also the car toon of a chip layout. #3. What are the uses o" Stic/ diagram?
$ It can be dr awn much easier and f aster than a complex layout. $ These ar e especially impor tant tools for layout built from lare cells. ##. i!e the !arious color coding used in stic/ diagram?
$ 1r een # n#diffusion $ 2 ed # polysilicon $ 6lue # metal $ ;ellow # implant $ 6lack # contact ar eas. #$. Com'are eteen CMOS and i'olar technologies. CMOS Technology 4i0'olar Technology
$ 'ow static power dissi pation $ &ih input impedance *low dr ive curr ent+
$ Scala ble thr eshold voltae $ &ih noise marin $ &ih pack in density $ &ih delay sensitivity to load *f anout limitations+ $ 'ow out put dr ive curr ent $ 'ow m *m < in+ $ 6idir ectional ca pability $ - near ideal switchin device= $ &ih power dissi pation $ 'ow input impedance *hih dr ive curr ent+ $ 'ow voltae swin loic $ 'ow packin density $ 'ow delay sensitivity to load $ &ih out put dr ive curr ent $ &ih m *m a ein+ $ &ih f t at low curr ent $ Essentially unidir ectional #%. -e" ine Threshold !oltage in CMOS?
The Thr eshold voltae, T for a !"S tr ansistor can be def ined as the voltae a pplied between the ate and the sour ce of the !"S tr ansistor below which the dr ain to sour ce curr ent, I)S eff ectively drops to %ero. #). What is 4ody e"" ect?
The thr eshold voltae Th is not a constant with r espect to the voltae diff er ence between the substr ate and the sour ce of !"S tr ansistor. This eff ect is called substr ate#bias eff ect or body eff ect. #*. What is Channel0length modulation?
The curr ent between dr ain and sour c e terminals is constant and independent of the a pplied voltae over the terminals. This is not entir ely corr ect. The eff ective lenth of the conductive channel is actually modulated by the a pplied )S, incr easin )S causes the depletion r eion at the dr ain >unction to row, r educin the lenth of the eff ective channel.
#+. What is atch 5 u'?
'atch#up is a condition in which the par asitic components ive r ise to the esta blishment of low r esistance conductin paths between )) and SS with disastrous r esults. Car eful control dur in f a br ication is necessary to avoid this problem. $,. What is demarcation line?
)emar cation line is an imainary line used in stick diar am, to se par ate p#!"S and n#!"S tr ansistors. -ll p#!"S tr ansistors ar e placed a bove demar cation line and n#!"S below the demar cation line $1. What are the to ty'es o" ayout design rules?
'ambda desin rules and micron rules ar e ma>or types of layout desin rules. $2. What is ay0out design rule?
The rules followed to pr e par e the photo mask ar e known as 'ayout desin rules. $3. What are 6S and -7 tools?
'S means 'ayout ersus Schematic. It checks layout aainst schematic diar am. It is very impor tant to ver ify layout. )2C means )esin 2ule Checker. This tool checks every occurr ence of desin rule list on layout. Width, spacin of every metal line in layout ar e checked with this tool. $#. What is instance? What is instancing?
To construct bi complex cir cuit, the basic cells *small cells+ can be copied. This process is known as Instancin. The cell which is copied is known as Instance. $$. What is " lat cell?
The cell which is independent and not r elated to other ob>ects is known as f lat cell. $%. What are the cells a!ailale in 'rimiti!e lirary?
"T, -), "2, ar e the basic cells in pr imitive li br ary. $). What is -esign 8ierarchy?
When we want to desin -)#? input ate, we use -)#0 and "2#0 basic blocks. 6y combinin -)#0 and "2#0, we cr eate -)#? input ate. This is known as )esin &ier ar chy. $*. Which is the so"tare used in this la?
cadence . $+. What are the other alternati!e so"tare a'art " rom cadence used "or 6SI design?
!icrowind, Tanner, &spice, (spice, !entor r a phics, @ilinx etcA
%,. &ame the Simulator used in cadence "or simulation ?
Insim or incisive simulator %1. What is 7T ?
2T' stands for 2 eister Tr ansf er 'evel. It is a hih#level hardwar e descr i ption lanuae *&)'+ used for def inin diital cir cuits. The most popular 2T' lanuaes ar e &)' and er ilo. %2. What is the di"" erence eteen simulation and synthesis? Simulation is used to ver ify the functionality of the cir cuit.. a+8unctional Simulation9 study of ckt7s oper ation independent of timin par ameters and ate delays. b+ Timin Simulation 9study includin estimated delays, ver ify setup, hold and other timin r e3uir ements of devices like f li p f lops ar e met Synthesis9 "ne of the for emost in back end ste ps wher e by synthesi%in is nothin but conver tin &)' or E2I'"1 descr i ption to a set of pr imitives or components*as in 8(1-7S+to f it into the taret technoloy. 6asically the synthesis tools conver t the desin descr i ption into e3uations or components. %3. Which is the tool used "or analog design o" !lsi circuits?
ir tuoso %#. What is the 'lat"orm "or !irtuoso?
Encounter %$. Why don9t e use :ust one &MOS or (MOS transistor as a transmission gate?
6ecause we can7t et full voltae swin with only !"S or (!"S .We have to use both of them toether for that purpose. %%. Why don9t e use :ust one &MOS or (MOS transistor as a transmission gate?
nmos passes a ood 5 and a der aded 4 , wher eas pmos passes a ood 4 and bad 5. for pass tr ansistor, both voltae levels need to be passed and hence both nmos and pmos need to be used. %). What are set u' time ; hold time constraints? What do they signi"y? Setu' time< Time befor e the active clock ede of the f li p#f lop, the input should be sta ble. If the sinal chanes state dur in this interval, the output of that f li p#f lop cannot be pr edicta ble *called metasta ble+.
8old Time< The af ter the active clock ede of the f li p#f lop, the input should be sta ble. If the sinal chanes dur in this interval, the output of that f li p#f lop cannot be pr edicta ble *called metasta ble+. %*. Ex'lain Cloc/ S/ e?
clock skew is the time diff er ence between the arr ival of active clock ede to diff er e nt f li p#f lopsB of the same chip. %+. Why is not &&- gate 're" erred o!er &O7 gate "or "arication?
-) is a better ate for desin than "2 because at the tr ansistor level the mobility of electrons is normally thr ee times that of holes compar ed to "2 and thus the -) is a f aster ate. -dditionally, the ate#leakae in -) structur es is much lower. ),. What is 4ody E"" ect?
In ener al multi ple !"S devices ar e made on a common substr ate. -s a r esult, the substr ate voltae of all devices is normally e3ual. &owever while connectin the devices ser ially this may r esult in an incr ease in sour ce#to#substr ate voltae as we proceed ver tically alon the ser ies chain *sb45, sb0 5+.Which r esults th0Dth4. )1. Why is the sustrate in &MOS connected to round and in (MOS to 6--?
we try to r everse bias not the channel and the substr ate but we try to maintain the dr ain, sour ce >unctions r everse biased with r espect to the substr ate so that we donBt loose our curr ent into the substr ate. )2. What is the "undamental di"" erence eteen a MOS=ET and 4>T ?
In !"S8ET, curr ent f low is either due to electrons *n#channel !"S+ or due to holes*p# channel !"S+ # In 6T, we see curr ent due to both the carr iers..Electrons and holes. 6T is a curr ent controlled device and !"S8ET is a voltae controlled device )3. In CMOS technology in digital design hy do e design the si@e o" 'mos to e higher than the nmos. What determines the si@e o" 'mos rt nmos. Though this is a sim'le Auestion try to list all the reasons 'ossile?
In (!"S the carr iers ar e holes whose mobility is lessF a prrox half G than the electrons, the carr iers in !"S. That means (!"S is slower than an !"S. In C!"S technoloy, nmos hel ps in pullin down the output to round (!"S hel ps in pullin up the output to dd. If the si%es of (!"S and !"S ar e the same, then (!"S takes lon time to chare up the out put node. If we have a larer (!"S than ther e will be mor e carr iers to chare the node 3uick ly and over come the slow natur e of (!"S . 6asically we do all this to et e3ual r ise and
f all times for the out put node.
)#. Why (MOS and &MOS are si@ed eAually in a Transmission ates?
In Tr ansmission 1ate, (!"S and !"S aid each other r ather competin with each other. That7s the r eason why we need not si%e them lik e in C!"S. In C!"S desin we have !"S and (!"S competin which is the r eason we try to si%e them propor tional to their mobility. )$. What ha''ens hen the (MOS and &MOS are interchanged ith one another in an in!erter?
If the sour ce / dr ain also connected proper ly...it acts as a buff er. 6ut suppose input is loic 4 "H( will be der aded 4 Similar ly der aded 5 )%. Why are 'MOS transistor netor/s generally used to 'roduce high signals hile nMOS netor/s are used to 'roduct lo signals?
This is because thr eshold voltae eff ect. - n!"S device cannot dr ive a full 4 or hih and p!"S canBt dr ive full 757 or low. The maximum voltae level in n!"S and minimum voltae level in p!"S ar e limited by thr eshold voltae. 6oth n!"S and p!"S do not ive r ail to r ail swin. )). What9s the di"" erence eteen Testing ; 6eri" ication? Testing9 - manuf actur in ste p that ensur es that the physical device , manuf actur ed from the synthesi%ed desin, has no manuf actur in def ect. 6eri" ication9 (r edictive analysis to ensur e that the synthesi%ed desin, when manuf actur ed, will perform the iven IH" function )*. What is atch B'? Ex'lain atch B' ith you a!oid atch B'?
cross
section o" a CMOS In!erter. 8o do
- latch up is the inadver tent cr eation of a low#impedance path between the power supply r ails of an electronic component, tr ier in a par asitic structur e*The par asitic structur e is usually e3uivalent to a thyr istor or SC2+, which then acts as a shor t cir cuit, disruptin proper functionin of the par t. )ependin on the cir cuits involved, the amount of curr ent f low produced by this mechanism can be lare enouh to r esult in permanent destruction of the device due to electr ical over str ess # E"S )+. What is slac/?
The slack is the time delay diff er ence from the expected delay*4Hclock+ to the actual delay in a par ticular path. Slack may be ve or #ve. *,. Ex'lain ho logical gates are controlled y 4oolean logic? In 6oolean alebr a, the true state is denoted by the number one, r e f err ed as loic one or loic hih. While, the "alse state is r e pr esented by the number %ero, called loic %ero or loic low. -nd in the diital electronic, the loic hih is denoted by the pr esence of a voltae potential.
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*1. Mention hat are the di"" erent gates here 4oolean logic are a''licale? &OT ate< It has one out input and one output. 8or example, if the value of - 5 then the alue of 64 and vice versa &- ate< It has one out put due to the combination of two out put. 8or example, if the value of - and 6 4 then value of J should be 4 O7 ate< Either of the value will show the same out put. 8or example, if the value of is 4 or 6 is 5 then value of J is 4 These ar e the basic thr ee types of ates wher e 6oolean loic work, a par t from these, other ates that ar e functional works with the combination of these thr ee basic ates, they ar e @"2 ate, -) ate, or ate and @"2 ate. ·
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*2. Ex'lain ho inary numer can gi!e a signal or con!ert into a digital signal?
6inary number consists of either 5 or 4, in simple words number 4 r e pr esents the " state and number 5 r e pr esents "88 state. These binary numbers can combine billion of machines into one machines or cir cuit and oper ate those machines by performin ar ithmetic calculations and sor tin oper ations. *3. Mention hat is the di"" erence eteen the TT chi's and CMOS chi's? TT Chi's
CMOS Chi's ·
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TT' chips for tr ansistor tr ansistor loic. It uses two 6i#polar unction Tr ansistors in the desin of each loic ate TT' chips can consist of a substantial number of par ts like r esistors TT'S chip consumes lot mor e power especially at r est. - sinle ate in TT' chip consumes a bout mW of power TT' chips can be used in computers
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C!"S stands for Complementary !etal "xide Semi#conductor. It is also an inter ated chip but used f ield eff ect tr ansistors in the desin C!"S has r eater density for loic ates. In a C!"S chip, sinle loic ate can compr ise of as little as two 8ETs C!"S chips consume less power. sinle C!"S chip consume a bout 45nW of power C!"S chip is used in !obile phones
*#. Ex'lain hat is a seAuential circuit? - se3uential cir cuit is a cir cuit which is cr eated by loic ates such that the r e3uir ed loic at the out put depends not only on the curr ent input loic conditions, but also on the se3uences past inputs and out puts. *$. Ex'lain ho 6erilog is di"" erent to normal 'rogramming language? er ilo can be diff er ent to normal pror ammin lanuae in followin aspects ·
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Simulation time conce pt !ulti ple thr eads 6asic cir cuit conce pts like pr imitive ates and network connections
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*%. Ex'lain hat is 6erilog? er ilo is an &)' *&ardwar e )escr i ption 'anuae+ for descr i bin electronic cir cuits and systems. In er ilo, cir cuit components ar e pr e par ed inside a !odule. It contains both behavior al and structur al statements. Structur al statements sinify cir cuit components like loic ates, counters and micro#processors. 6ehavior al statements r e pr esent pror ammin aspects like loops, if#then statements and stimulus vectors. *). In 6erilog code hat does timescale 1 nsD 1 's signi" ies? In er ilo code, the unit of time is 4 ns and the accur acyH pr ecision will be upto 4ps. **. Mention hat are the to ty'es o" 'rocedural loc/s in 6erilog? The two types of procedur al blocks in er ilo ar e Initial< Initial blocks runs only once at time %ero lays< This block loop to execute over and aain and executes always, as the name suests ·
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*+. Ex'lain hy 'resent 6SI circuits use MOS=ETs instead o" 4>Ts? In compar ison to 6T, !"S8ETS can be made very compact as they occupy very small silicon ar ea on IC chip and also in term of manuf actur in they ar e r elatively simple. !or eover, diital and memory ICs can be employed with cir cuits that use only !"S8ETs, i.e., diodes, r esistors, etc. +,. Mention hat are three regions o" o'eration o" MOS=ET and ho are they used? !"S8ET has thr ee r eions of oper ations Cut#off r eion Tr iode r eion Satur ation r eion The tr iode and cut#off r eion ar e used to function as a switch, while, satur ation r eion is used to oper ate as an amplif ier. ·
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+1. Ex'lain hat is the de'letion region? When positive voltae is tr ansmitted across 1ate, it causes the fr ee holes *positive chare+ to be pushed back or r e pelled from the r eion of the substr ate under the 1ate. When these holes ar e pushed down the substr ate, they leave behind a carr ier depletion r eion. +2. Ex'lain hy is the numer o" gate in'uts to CMOS gates usually limited to "our? &iher the number of stacks, slower the ate will be. In "2 and -) ates the number of ates pr esent in the stack is usually alike as the number of inputs plus one. So input ar e r estr icted to four. +2. Ex'lain hat is multi'lexer? - multi plexer is a combination cir cuit which selects one of the many input sinals and dir ect to the only output.
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