UG Diploma in Analog VLSI Design Course: Mini Project Course Code: 10UGVL06 Nature of Project: Analog VLSI Layout Design
Project Title: Design of a Static CMOS Tri-state Inverter
Defined Specification: Minimum Achievable Delay
Project By: Manasa S Upadhyaya
CONTENTS: 1. Introduction 2. Architecture analysis and comparisons 3. Device sizing details 4. Switching potential estimate 5. Theoretical estimated parameters 6. Delay versus load estimate 7. SPICE Simulations 8. Layout plan 9. DRC and LVS report 10.Conclusion. 11.References
ABSTRACT: This project report comprises design of a static CMOS tri state inverter for minimum achievable delay, driving 10 identical copies of it. 3 possible architectures for realising the inverter are discussed; out of these the best architecture is chosen. The device sizing, switching potential estimation is carried out through hand calculations and verified through SPICE simulations. Variation of load versus delay is plotted. Finally the layout of the inverter is captured using standard cell layout technique along with DRC and LVS reports.
1. INTRODUCTION: A tri state logic comprises the usual true (0) and false (1) states, with a third high impedance state (or 'off-state') which effectively disconnects the logic output. The mode of operation of tri state logic circuit is determined by the state of enable input. When the enable input is ‘high’, the device is enabled for normal logic operation. When the enable is ‘low’ the circuit is in the high impedance state. This provides an effective way to connect several logic outputs to a single input, where all but one are put into the high impedance state, allowing the remaining output to operate in the normal binary sense. This is commonly used to connect banks of computer memory and other similar devices to a common data bus; a large number of devices can communicate over the same channel simply by ensuring only one is enabled at a time. When a digital input is left disconnected (i.e., when it is given a high impedance signal), the digital value interpreted by the input depends on the type of technology used. TTL technology will reliably default to a "1" state. On the other hand CMOS technology will temporarily hold the previous state seen on that input (due to the capacitance of the gate input). The tri-state inverter forms the basis for various types of clocked logic, latches, bus drivers, multiplexers, and I/O structures. The symbol and truth table of a tri state inverter is as shown below:
En Symbol:
A
Y En Truth table: En/ En
A
Y
0/1
0
Z
0/1
1
Z
1/0 1/0
0 1
1 0
2. ARCHITECTURE
ANALYSIS AND COMPARISONS:
Following are the architectures that can be used for realising a tri state inverter: Using Transmission gate: A transmission gate connected to the output of an inverter as shown in Fig2.1 provides tri state capability, but also consumes unnecessary power. This topology contributes to dynamic power each time that the input and output (Y’) are switched, even when gate is disabled in the tri state mode. It is also a non restoring circuit, i.e., if the input is a noisy or degraded signal, the output will receive same noise. The disadvantages of the above topology can be avoided by putting a transmission gate inside the inverter. The possibilities fig are as follows: Circuit topologies:
fig2.2
fig2.3
In general, the two topologies shown above are logically equivalent, but the effect of charge sharing comes into picture for the circuit of fig2.2. When the output is tri-stated, if the input A toggles, the charges from the internal nodes disturbs the floating output node. Due to this, the voltage level of the floating output node will not remain same as its previous value. This effect may switch the next gate driven by this gate. Hence it can cause erroneous output of the circuit. For the circuit of fig2.3, the effect of charge sharing is not seen in its tri-state condition as the output node Y is completely disconnected from the input and internal nodes. Hence this circuit topology is best suited for realising a simple tri-state inverter.
3.
DEVICE SIZING :
Specification: To size the device for minimum achievable delay. Load: 10 copies. Method used: RC Delay model. Nomenclature: Subscripts: p – PMOS
n – NMOS d – Drain terminal of MOSFET s – Source terminal of MOSFET g – Gate terminal of MOSFET b – Body/Substrate of MOSFET Parameters: V dd – Supply terminal V ss – Ground terminal R–Drain to Source resistance C – Gate Capacitance µ – mobility of electrons (n) /holes (p) W – Width of MOSFET L – Chanel length T pdr – Rise time of output Y T pdf – Fall time of output Y T pd – Propagation delay time
1.
Since TSMC 180nm technology is used for design of the inverter, so channel length, L p = Ln = 180nm.
2.
Consider a unit inverter which has been designed minimum propagation delay. Let W n and W p be the widths of NMOS and PMOS of the inverter as shown fig3.1.
fig3.1
fig3.2
3.
Now for the tri-state inverter, as shown in fig3.2, let the width of NMOS be 2 times that of unit inverter so that the effective resistance of the 2 NMOSs’ together is equal to that of the unit inverter. The same holds good for the PMOSs’ as well.
4.
The gate capacitance: Cg∝W*L⟹ Cg-pCg-n= 2*Wp2*Wn=WpWn ∵ Lp=Ln
5. The resistance of a transistor: R∝ 1μ * W ⇒ RpRn= μnμp*2*Wn2*Wp=μnμp*WnWp. 6. 7.
Let the mobility ratio be μ=μnμp. The design calculations are carried out by considering En (En) as high (low). So the transistors M2 and M3 are on. 8. Considering for Cdb=Cgs=Csb=Cg contacted diffusion and Cdb=Cgs=Csb≅Cg/2 for uncontacted shared diffusion. 9. From fig3.3, Cgs1=Cdb1=Csb2=Cg-n Cgs4=Cdb4=Csb3=Cg-p Cdb4=12*Cg-n Cdb3=12*Cg-p
The effective input capacitance is given by: Cin=Cgs1+Cgs4=Cg-n+Cg-p=Cg-n*(1+WpWn) (From step 2)
fig3 The parasitic capacitance is given by: Cpar=Cdb3+Cdb4=12*(Cg-n+Cg-p)=12*Cg-n*(1+WpWn)
Since the inverter capacitance is given by:
drives
10
copies
of
itself,
the
load
Cload=Cout=10*Cin=10*Cg-n*(1+WpWn) 10.Determination
of Rise time (T pdr ): 11.For the output Y to rise from V ss (low) to V dd (high), it must be connected to V dd . Which implies that, both PMOSs’ must be turned on, i.e., A = 0 (low). Using the equivalent second order RC network as shown in fig3.4, the rise time is determined.
Tpdr=Rp*Cg-p+Rp*Cpar+Cload=Rp*Cg-p+Cpar+Cload
fig3
On substituting equations of step 9 in above equation, we get Tpdr=212*Rn*Cg-n*μnμp*WnWp
12.Determination
of Fall time (T pdf ): For the output Y to fall from V dd (high) to V ss (low), it has to be connected to V ss. Hence both NMOSs’ must be on, i.e., A = 1(high). The fall time is again determined by equivalent RC network (fig3.5).
Tpdf=Rn*Cg-n+Rn*Cpar+Cload= n+Cpar+Cload
Rn*Cg-
) Tpdf=Rn*Cg-n*(232+212*WpWn
13.Propagation delay: The average propagation delay is given by,
fig3.
Tpd=12*(Tpdr+Tpdf) ⟹Tpd=12*Rn*Cg-n*(212*μnμp*WnWp+232+212*WpWn)
To determine W n and W p for defined specification: Let w=WpWn. To find minimum value of T pd , differentiating equation with respect to w and equating to zero. dTpddw=0 ⟹12*Rn*Cg-n*212*μnμp+212*-1w2=0 ⟹w2=μnμp ⟹WpWn=μnμp
1.
SWITCHING POTENTIAL ESTIMATE :
The switching point of an inverter is a point on its voltage transfer characteristic at which the input voltage is equal to the output voltage. This potential is termed as the switching potential. To determine the switching potential of the tri-state inverter, it is configured as a simple inverter. To do this, first consider the NMOSs’. The 2 NMOSs’ of equal sizes connected in series can be approximated to be a single NMOS with channel length equal to sum of the individual lengths. Ln1+Ln2=2*Ln . And the trans conductance parameter, β(=μ*Cox*WL)of the single N MOS is given by βn1+βn2=βn2. Similarly the equal sized PMOSs’ can be approximated as a single PMOS of channel length 2*Lp and β=βp2 . At the switching point, the MOSFETs are operating in saturation region; hence the drain current of NMOS and PMOS must be equal.
∴ βn22*Vsp-Vthn2=βp22*Vdd-Vsp-Vthp2.
Where, V sp – Switching potential V thn – Threshold voltage of NMOS V thp – Threshold voltage of PMOS V dd – Supply voltage On solving the above equation for V sp , we get Vsp=βpβn*Vdd-Vthp+Vthn(1+βpβn).
2.
THEORETICAL ESTIMATED PARAMETERS:
The parameters of the MOSFETs are taken from the measurements of MOSIS test structures obtained by MOSIS. VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns TRANSISTO NP-CHANNEL UNITS R CHANNEL PARAMETE RS V th
0.50
– 0.49
volts
K' (µ*Cox /2)
171.0
–37.0
µA/V^2
Low-field Mobility (µ)
406.07
87.86
cm^2/V *s
From the above derived equations and details, choosing W n of the unit inverter as 0.5µm, therefore for the tri-state inverter, the devices sizes are:
Transistor
Channel Width
Channel Length
NMOS
1.00µm
0.18µm
PMOS
2.162µm
0.18µm
Switching potential value: βn=2*(μ0*Cox2*WL)n=2*171*10.18=1900 βp=2*(μ0*Cox2*WL)p=2*37*2.1620.18=888.82
Switching potential,
Vsp=βpβn*Vdd-Vthp+Vthn(1+βpβn)=888.821900*1.80.49+0.5(1+888.821900)=0.8289V.
3.
DELAY VERSUS LOAD ESTIMATE:
From the linear delay model, we have the normalised delay of the gate as d=f+p
Where p –normalised parasitic delay of the gate under zero load, f – Stage effort; f=g*h, where g – logical effort and h – fanout of the gate. Hence d=g*h+p. The logical effort of the gate is given by g=Cin-gateCin-inv where Cin-gate input capacitance of the gate and Cin-inv input capacitance of an inverter delivering the same output current as that of the gate. Consider a unit transistor designed to achieve minimum delay. Cin-inv=Cg-n*(1+μ) Cin-gate=2*Cg-n*(1+μ) ⟹g=2
The fanout of the tri-state inverter is equal to number of identical copies drawn by the gate. Hence the value of ‘h’ varies from 1 to 10. The parasitic delay of the gate is given by p=Cpar-gateCin-inv, where Cpar-gate – parasitic capacitance at the output node of the gate and Cin-inv – capacitance at the input node of the unit inverter. Hence for the tri-state inverter,
p=2.
Hence the normalised delay,
4.
d=2*h+2.
SPICE SIMULATIONS :
Tool used: LT SPICE IV Schematic:
1. To verify the device size. Choosing Wn for inverter as 0.5µm, therefore for the tri-state inverter, Wn=2*0.5μ=1μm. Consider En/En =1/0.
Analysis: transient analysis is carried out to determine the propagation delay.
Propagation delay v/s width of the PMOS transistors:
From the transient analysis, we get minimum delay at W p = 2.132µm.
2. To determine the switching potential. Keeping W n = 1 µm and W p = 2.132 µm. Analysis: dc sweep to determine the switching potential. Consider En/En =1/0.
From the dc sweep analysis, V sp = 0.833V
3. To plot the average propagation delay-versus load. The gate is made to drive 0 to 10 copies of it and the corresponding delay values are plotted.
1.
LAYOUT PLAN:
Tool used : The Electric VLSI Design System. Stick diagram:
Layout Plan:
2.
DRC AND LVS REPORT :
DRC report:
Layout v/s Schematic (Network Consistency Checking (NCC) in the tool):
3.
CONCLUSION :
The tri-state inverter with a simple architecture has been analysed and designed to achieve the defined specification. The theoretically estimated values are approximately equal to the simulated values. This is so because, while determining the theoretical values, approximate RC delay models have been used. In the load versus delay plots, the delay at zero load is not same as estimated but for higher loads the 2 plots match.
REFERENCES : 1. Neil H.E Weste, David Haris, Ayan Banerjee-‘CMOS VLSI Design A Circuit and systems Perspective’, Third edition, Pearson Education. 2. John P Uyemura, ‘Introduction to VLSI CIRCUITS AND SYSTEMS’, Wiely-India. 3. Rabeay, ‘Digital Integrated Circuits’, 2nd.Edition, Prentice Hall. 4. Website: www.mosis.com 4.
