Ti Jtag Seminar

Topic 8 - JTAG Boundary Scan

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory


Agenda

JTAG

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(IEEE 1149.1/P1149.4)

Tutorial Introductory

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Conventional Methods of Test

(10 minutes)

The Boundary-Scan Architecture

(15 minutes)

The Increasing Problem of Test

(5 minutes)

The Boundary-Scan Idea

(15 minutes)

Typical Applications

(15 minutes)

Interconnect Testing

\u2014

Logic Cluster Testing

\u2014

Memory Testing

\u2014

System-Level Test

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1997 TI Test Symposium

(5 minutes)

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AL 10Sept.-97 1149.1(JTAG)-Tut.I-1

What Is JTAG?

Real JTAG Applications

(10 minutes)

Q&A

(10 minutes)

(5 minutes)

For More Information





Standard Approach To Test

JTAG / IEEE 1149.1

What Is JTAG?

Developed by Joint Test Action Group (over 200 SC, test, and system vendors) starting in mid '80's

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Sanctioned by IEEE as Std 1149.1 Test Access Port and Boundary-Scan Architecture in 1990

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Solution: Build test facilities/test points into chips

Focus: Ensure compatibility between all compliant ICs 1997 TI Test Symposium



Standard Test Access Port ... User Register

TDI


\u2026 and Boundary-Scan Architecture

TDO

DR

TMS TAP Controller

TCK

IR

Decode Logic

CORE

Chip-Internal Scan: Partitions chips at storage cells (latches/ flipflops) to effectively partition sequential logic into clusters of combinational logic

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Instruction Register

TRST* \ u 2 5 a 0

4/5-Wire Interface at Chip-Level

\ u 2 5 a 0

Serial Instruction/Serial Data Port

\ u 2 5 a 0

Extensible to Include

\ u 2 0 1 4

user-defined instructions

\ u 2 0 1 4

user-defined data registers



Scan effectively partitions digital logic to facilitate control and observation of its function

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Bypass Register

Boundary-Scan: Partitions boards at chip I/Os for control and observation of board-level nodes

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The Incredible Shrinking Board \u25a0

Miniaturization results in loss of test access

The Increasing Problem of Test Yesterday 1997 TI Test Symposium


Today




The Ever-Expanding Chip

Tom orrow?


Can\u2019t Afford Not To Test Cost will increase by a factor of ten as fault finding moves from one level of complexity to the next. The result:

Increasing integration at chip level complicates controllability

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Reduced Profit Margins

Delayed Product Introduction

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1

0

1

C1 C1 1D 1D

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1. Device level 2. Board level 3. System level Yesterday AL 10Sept.-97 1149.1(JTAG)-Tut.I-9

4. Field level

Today 1997 TI Test Symposium

1 unit of cost 10 units of cost 100 units of cost 1,000 units of cost 1997 TI Test Symposium



Dissatisfied Customers


Conventional Methods of Board Test Functional Test (\u2018Edge-Connector\u2019 Test)

Conventional Methods of Test

Based on board function, rather than structure

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Test generation primarily manual

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Test access limited to primary I/O only

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Conventional Methods of Board Test

Conventional Methods of Board Test

In-Circuit Test (\u2018Bed-of-Nails\u2019 Test)

In-Circuit Test (\u2018Bed-of-Nails\u2019 Test) Based on board structure, but limited by chip complexity

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Expensive testers and fixtures required

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Chip function can be ignored for shorts testing

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Chip function must be considered for continuity test

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Test access limited by: Fine pitch packages

\u2014 \u2014

Double-sided boards

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Conformal coating

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MCMs



Test generation, though automated, requires ICT models

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The Boundary Scan Idea

The Boundary-Scan Idea 1997 TI Test Symposium


\u2018In-Circuit\u2019 test points onto the silicon, creating \u2018Virtual Nails\u2019

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CORE

Boundary scan cells bound each net, providing for continuity testing

CORE

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Observe/Control cells provide for test and normal function

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Boundary Scan Method of Board Test

The Boundary Scan Idea Scan provides a means to arbitrarily observe test results and source test stimulus

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CORE

CORE

CORE

Based on board structure; Not limited by chip function/ complexity

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Scan method requires minimal on chip/board resources (pins/nets)

CORE

CORE

Test access is not limited by board physical factors

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CORE

CORE

J T A G







Boundary Scan Method of Board Test

The Boundary Scan Cell t) SO (Serial Output) u p n I l a OBSERVE CONTROL m r TEST/DATA o MUX (N I CAPTURE/SCAN MUX N

Chip function need not be considered for board test (shorted/open nets)

■

Test generation is highly automated; Simple ‘In-Circuit Library’ models (BSDL) are vendorsupplied or EDA-generated

■



CORE

SCAN LATCH/FLOP

SI (Serial Input)




The Control Architecture ■

■

CORE

ID Register

TDI

TDO

Boundary scan and other test data registers operate under control of instruction register Data is scanned from TDI to TDO through selected test data register or instruction register under control of Test Access Port (TAP) controller

Bypass Register DR

TMS TCK

TAP Controller

Decode Logic

IR

■


TAP operates synchronously to TCK using TMS for state selection


The Test Access Port Controller 1 Test Logic Reset 0 0

Run Test/Idle

1

Select DR-Scan

1 1

1

0

Shift-DR

Shift-IR

1 1

Exit 1-DR

0

Pause-DR

Exit 2-DR

0

0

TDI

Bypass Register DR

TMS TCK

TAP Controller

IR


Decode Logic Instruction Register

Following shift operation, new test stimulus transferred to BSC update latches


SCAN-DR

—

SCAN-IR

Scans consist of 3 primary steps: —

CAPTURE

—

SHIFT

—

UPDATE

1

0


The Sample/Preload Instruction (REQUIRED)

■

■

Input data captured in BSC scan latches prior to shift operation

TDO

RUN-TEST

—

Update-IR

0

Provides for test external to chip, such as interconnect test

Shift operation allows test response to be observed at TDO while next test stimulus inserted at TDI

RESET

—

1

1

Output pins operate in test mode, driven from contents of BSC update latch

■

—


(REQUIRED)

ID Register

Exit 2-IR


The Extest Instruction

CORE

0

1


■

■

Pause-IR

1

16-state TAP provides 4 major operations:

1

Exit 1-IR

0 0

0

1

Update-DR


Capture-IR

0 0

■

0

Capture DR

state transitions occur on rising edge of TCK based on the current state and the TMS input value ONLY

1

Select IR-Scan

0

1


UPDATE LATCH/FLOP

N O (N o r m a l O u tp u t)

ID Register Bypass Register DR

TMS TCK

TAP Controller

IR


Decode Logic Instruction Register

Output and input pins operate in normal mode

Input pin data and core logic output data captured in BSC scan latches

CORE

TDI

Provides means to preload boundary before entry to test mode

■ TDO

Shift operation allows test response to be observed while next test stimulus inserted at TDI

Following shift operation, new stimulus transferred to BSC update latches




The Bypass Instruction (REQUIRED)

■

CORE

■

■ ID Register

TDI

TDO

Provides for abbreviated scan path through chip

Typical JTAG Applications

Output and input pins operate in normal mode The one-bit bypass register is selected for scans

Bypass Register DR

TMS

Decode Logic

TAP IR Controller

TCK

■


Mandatory that an all-ones value updated into the IR decodes to Bypass, as well as any opcodes which are otherwise undefined 1997 TI Test Symposium






Interconnect Test

Interconnect Test

Full B/S Board

Partial B/S Board

■

■

■

■

All nets bound by BSC's and/or primary I/O requiring no physical access Parallel access reduced to card edge only

■

Test generation and application fast and easy ■

J T A G

J T A G



■ C I G O L

" R E T S U L C "

■

■

Deterministic test stimulus (ATPG-generated) can be driven to cluster from B/S outputs Test response can be captured at B/S inputs BIST methods (PRPG/PSA) can be used for increased test throughput and near "At-speed" performance

Cluster testing may be used to access non-scan nets 1997 TI Test Symposium


Logic Cluster Test

Logic Cluster Test Random-logic cluster is bound by boundaryscannable chips

Expense and complexity reduced for test generation and test application for chips/nets with B/S access



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Not all nets are bound by boundary scan and/or primary I/O, perhaps requiring some ICT access

r o s s e c o r p o r c i M

Buffer

‘LVT18502

Parallel Data In

Buffer 2 0 5 8 1 T V ‘L Buffer 2 0 5 8 1 T V L ‘

Control Logic (Non-Scan)

Latch ‘A B T 1 8 Address 5 0 2

Memory Array

Buffer ‘ A B Control T 1 8 5 0 2

Registered Transceiver ‘ L V Data T 1 Scan Path 8 5 0 IEEE 1149.1 4 I S K O D M C D T T T T







Memory Test

Memory Test SN74BCT8245

Latch 2 0 5 8 1 T Address B ‘A

■

■

Memory Array

Buffer 2 0 5 8 1 T Control B A ‘

■

■

Registered Transceiver 4 0 5 Data 8 1 T V ‘L

■

1B1 1B2 1B3 1B4 2B1 2B2 2B3 2B4

Memory array bound by boundary scan chips Automatic test patterns can be generated and driven from B/S outputs

DIR G TDO TMS

Test response can be captured at B/S inputs Transceivers can test for net shorts w/o memory R/W BIST methods (PRPG/PSA) can be used for increased test throughput


256 x 8 RAM Array D0 D1 D2 D3 D4 D5 D6 D7

SN74BCT8244 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4

A0 A1 A2 A3 A4 A5 A6 A7

1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 G2 G1

WE TDI TCK

TDO TMS

CS

SN74BCT8244 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4

1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4

G2 G1 TDO TMS


1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4

TDI TCK

256 ACCESSES

MODE

1,000,000 ACCESSES

IEEE 1149.1 Time To Apply 5.625000 Seconds EXTEST & Scans 512 SAMPLE) Patterns 512

375.00 Minutes 2,000,000 2,000,000

IEEE 1149.1 Time To Apply 0.000041 Seconds (with BIST Scans 7 capability) Patterns 512

< 0.01 Minutes 28,000 2,000,000

TDI TCK





System-Level Test ■

A S P

A S P

A S P

TDO TDI TMS TCK

■

System-level test

■

System design verification

■

Sys integration (Mfg test)

■

Sys self-test (Field Svc)

■

■

✦

TAP-addressable interface unit extends JTAG access beyond board-level

Real JTAG Applications

Supports in place board test and board-to-board test Allows reuse of device/ board test data

ASP-Addressable Scan Port Device 1997 TI Test Symposium






Real Applications of the TAP ■

I

N S

T C

E A

R

N

A

L

N

CORE T

E

S

T

BIST

■

Emulation

■

Programming ■

TAP ■

TDI

TCK


TMS

TDO

Design Verification/Debug ■

Scan access to chips, boards, systems for: — Design verification/debug —

Manufacturing test

—

Hardware/software integration

—

Field test/diagnostics

Access built-in self-test (BIST) Access on-chip/in-circuit emulation (ONCE/ICE)

Access in-system programming (ISP) of PLDs/EEPROMs Let your imagination run wild!!!


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Provides control and observation of system under test without need for physical access — Ease of set-up for test —

Can be used in standard system configuration (no need for card extenders, etc.)

—

Can be used in environmental chambers

—

Can access on-chip emulation for software/debug

—

Can access ISP for code download/offload/ changes 1997 TI Test Symposium



System Configuration Maintenance

Manufacturing Test ICT

■

Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access — Improved fault coverage/diagnostic without large capital expense — Highly automated test generation reduces test development time

■

Provides low-level test access within configured systems for: — In-house system integration —

J T A G

—

Fielded-system test and diagnostics Built-in self-test

—

In-field upgradability via ISP, etc.

—

Remote field test, diagnostic and upgrade

J T A G





TI’s JTAG Educational Products

IEEE Standards

Call (214)-638-0333 to ORDER

■

■

Call (800) 678-IEEE to ORDER

■

Scan Educator PC-based tutorial with interactive — boundary-scan simulation.

IEEE 1149.1 Testability videotapes Two-part video presenting an overview and — instructions for boundary scan.

IEEE 1149.1 Boundary-Scan

Item No. SATV001 (NTSC VHS) and SATV002 (PAL VHS), $149 each.

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■



■

The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder, Rodham E. Tulloss, ed., IEEE CS Press, ISBN 0-8186-9070-4. —

■

The Boundary-Scan Handbook, Kenneth P. Parker, Kluwer Academic Publishers, ISBN 0-7923-9270-1. —

■

Edited by two principal chairs of the IEEE 1149.1 working group, this Computer Society tutorial compiles several of the seminal papers on boundaryscan along with several invited papers on various topics including applications, implementation, and others. It will primarily be of interest to the design and/or test engineer.

Authored by the principal force behind the Boundary-Scan Description Language (BSDL) and an IEEE 1149.1 working group principal as well as a long time manufacturing and design-for-test expert, this is truly considered THE indispensable handbook on boundary scan for the design and/or test engineer.

Boundary-Scan Test - A Practical Approach, Harry Bleeker, Peter van den Eijnden, Frans de Jong, Kluwer Academic Publishers, ISBN 0-792-9296-5. —

Authored by several JTAG and IEEE 1149.1 working group principals, this book is a ready reference to boundary-scan technology, its benefits, and considerations for design and test managers and engineers.



The official document which specifies the international standard for a boundary-scan description language. This supplement to IEEE Std 1149.1-1990 was ratified in September 1994.




Tutorials/Handbooks

The official document which specifies the international standard for a test access port and boundary-scan architecture. Informally known as the JTAG standard, it was officially ratified by the IEEE in February 1990. Since, it has been supplemented twice. The first supplement, ratified in June 1993, is included in the referenced document. The second supplement is currently a separate document, as referenced below.

IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, ISBN 155937-497-7, IEEE order number SH94256. —

In process of converting to MPEG on CD-ROM

—

IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE Standard Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4, IEEE order number SH16626. —

FREE download at http://www.ti.com/sc/data/jtag/scanedu.exe

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Abbreviations/Acronyms ASIC

Application-Specific Integrated Circuit IEEE

ASP

Addressable Scan Port

ATE

Automatic Test Equipment

ATPG

Automatic Test Pattern Generation

BIST

Built-In Self-Test

B/S

Boundary-Scan

BSC

Boundary-Scan Cell

BSDL

Boundary-Scan Description Language

BSR

Boundary-Scan Register

BST

Boundary-Scan Test

CAE

Computer-Aided Engineering

DFT

Design-for-Test

DR

Data Register

DSP

Digital Signal Processing/Processor

EDA

Electronic Design Automation

eTBC

Embedded Test Bus Controller

FPGA

Institute of Electrical & Electronics Engineers IR Instruction Register

ISP

In-System Programming

JTAG

Joint Test Action Group

MCM

Multi-Chip Module

Mfg

Manufacturing

PCB

Printed Circuit Board

PLD

Programmable Logic Device

PRPG

Pseudo-Random Pattern Generation

PSA

Parallel Signature Analysis

PWB

Printed Wiring Board

SPL

Scan Path Linker

SVF

Serial Vector Format

TAP

Test Access Port

TBC

Test Bus Controller

TCK

Test Clock

Field-Programmable Gate Array

TDI

Test Data Input

ICE

Hierarchical Scan Description LanguageTDO TMS In-Circuit Emulation

ICT

In-Circuit Test

TRST

Test Reset

UUT

Unit Under Test

HSDL


Test Data Output Test Mode Select


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