PAM TDM

Experiment No 4 PAM and TDM

AIM: To design and demonstrate the working of TDM and recovery of two band limited signals of PAM signals. Plot the relevant waveforms. EQUIRED: COMPONENTS R EQUIRED

 Name of the Component/Equipment

Specifications/Range

Quantity

Transistor

SL100

2

IC 4051

Power dissipation -750mW Supply voltage - ± 5V

2

Resistors

10K Ω,67K Ω,1K Ω,2.7K Ω

1

CRO

100MHz

1

Function Generator

1MHz

3

Regulated Power Supply

0-30V , 1A

1

THEORY In Pulse-Amplitude Modulation (PAM), the amplitude of a periodic train of pulses is varied in  proportion to a message me ssage signal.TDM provides an effective method for sharing a communication commun ication channel. TDM is a technique used for transmitting several message signals over a communication channel  by dividing the time frame into slots, one slot for each message signal. This is a digital technique in which the circuit is highly modular in nature and provides reliable and efficient operation. There

is no cross talk in TDM due to circuit non-linearity since the pulses are completely isolated. But it also has its disadvantages, which includes timing jitter and synchronization is required.

PROCEDURE: 1. Connections are made as shown in Fig.1 2. Feed the input message signals M1 and M2 of 2 volts PP at 200Hz. 3. Feed the high frequency carrier signal of 2V (P-P) at 2KHz 4. Connect the two PAM circuits and check for the clear PAM output 5. Give the output of two PAM signals to IC 4051 multiplexer to get multiplexed output (with proper clock pulse). 6.  Now connect the multiplexed output to next IC 4051 which acts as de-multiplexer to get  back the original PAM signals at pin number 13 and 14. 7. Record the results by tracing the waveforms obtained.

CIRCUIT DIAGRAM

Fig .1

CIRCUIT DESIGN PAM 1

PAM 2

fm = 500Hz, fc = 3 KHz

fm = 1 KHz, fc = 5 KHz

Given Vc = 4Vpp, Vm = 3Vpp

Given Vc = 8Vpp, Vm = 6Vpp

hfe = 30, VBESAT = 0.7v

hfe = 30, VBESAT = 0.7v

VCESAT = 0.3V, Ic = 1mA

VCESAT = 0.3V, Ic = 1mA

Appling KVL at the output side;

Appling KVL at the output side;

Vm = VCE + IER E

Vm = VCE + IER E

1.5 = 0.3 + 1m R E

3 = 0.3 + 1m R E

R E = 1 KΩ

R E = 2.7 KΩ

Appling KVL at the input side;

Appling KVL at the input side;

Vc = IBR B + VBE + IER E

Vc = IBR B + VBE + IER E

2 = R B X 1m / 30 + 0.7 + 1m X 1K

4 = R B X 1m / 30 + 0.7 + 1m X 1K

R B = 9KΩ (choose 10KΩ)

R B = 69KΩ (choose 67KΩ)

EXPECTED OUTPUT:

R ESULT AND CONCLUSION: