LEC Jumpstart Training Overview

Conformal Logic Equivalence Checking (LEC) Version 14.2

Course Agenda   

Introduction to Cadence Support Sup port & Training Introduction to Logic Equivalence Checking Flat Comparison Flow SETUP mode: Step 1-4  LEC mode: Step 5-8 



Hierarchical Comparison Flow What is hierarchical comparison  Run Dynamic comparison 

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© 2012 Cadence Design Systems, Inc. All rights reserved.

Course Agenda   

Introduction to Cadence Support Sup port & Training Introduction to Logic Equivalence Checking Flat Comparison Flow SETUP mode: Step 1-4  LEC mode: Step 5-8 



Hierarchical Comparison Flow What is hierarchical comparison  Run Dynamic comparison 

2


Cadence Customer Training Training Go to http://www.cadence.com   Support & Training to sign up. Expert instructors share their knowledge to provide you the latest methodologies, design flows, and tool expertise.

Logic Equivalence Checking with Encounter Conformal EC

Demos

Encounter Conformal ECO

Labs with Design Data

Classroom Environment

Audio

Internet Learning Series

Encounter Conformal LowPower Verification

Virtual Classroom

Learning Activities

Self-help tools from Online Support allow you to build on your knowledge.

Rapid Adoption Adoption Kits provide a jumpstart for the user who wants to get going with the tool now.

3


Custom Equivalence Checking with Encounter Conformal EC

Quizzes

Encounter Conformal Constraint Designer

http://support.cadence.com

Cadence Online Support (COS) 

Cadence Online Support (https://support.cadence.com) is a website that gives you access to support resources, including – An extensive knowledge base with – – – – – – –

User guides Reference manuals Design topics Frequently asked questions Known problems and solutions White papers Application notes

– Software updates for Cadence products – Access to Cadence customer support engineers – Register now and take advantage of the many benefits of Cadence online support. If you do not have an active account, please send an email to COS_Registration and one will be setup for you. Testcase database, Scripts and references can be found at ‘Attachments’ and ‘Related Solutions’ sections below the PDF. This pdf can be searched with the document 'Title' on https://support.cadence.com Note:

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Conformal L Baseline Equivalence Checking  RTL2gate

and gate2gate equivalence checking − Verifies all transformations that occur during design implementation − Exhaustive verification without the use of test vectors

 FPGA

EC verification targeting Xilinx and Altera devices  Semantic and structural checks − Additional capabilities beyond EC to detect bugs earlier in the design cycle  Safest

EC solution

− Independent verification – finds bugs others miss  Best

rate

5

comparison completion


X <= NOT Y;

RTL

Logic Synthesis Logic Optimization

Test Insertion

Clock Synthesis

Floor Planning

Placement

Routing

P&R Optimization

ECOs

Conformal Equivalence Checker

Conformal XL Verification of Complex Designs with Datapath  Increased

use of advanced datapath optimization by logic synthesis tools  Provides formal analysis and verification solution for complex datapath − − − −

Operator merging Advanced pipelining Retiming Resource sharing

wide variety of datapath architectures  Provides analysis tools to determine causes of nonequivalences and aborts  Enables multi-threaded compare and functional partitioning

A

B

C

A

X

+ Y

Operator Merging

 Supports

6


B

Advanced Pipeline Support

Merged Operator

Y

C

Starting and Exiting Starting

Conformal LEC

– Menu mode: lec [–L| -XL | -GXL | -ECO | –LPXL | – LPGXL]

– Command mode: lec [–L| -XL | -GXL] -nogui – Switch between menu and command modes: set gui [on | off]

– Batch mode lec -dofile -nogui dofile Exiting

Conformal LEC

exit [-force]

LEC automatically closes all windows upon exit.

7


Graphical User Interface (GUI) Read library

Read design

Design hierarchy window

Transcript window Command entry window Status

8


Golden

Debug tools

Mode

Revised

Messages

100% completed

Status bar

Product Documentation: Tool Environment Click

the Help button in the Encounter Conformal environment to access documentation for the tools.

− Commands: List of all command options, usage, examples, and related commands − Reference Manual: Command reference with detailed command usage and definitions − User Guide: Information related to the product, such as installation, process flow, and graphical interface The directory location of the PDF manuals is $CONFORMAL_HOME/doc. On the Encounter ® Conformal ® command line, type man to display command syntax. Append the -verbose option to display a command explanation. 9


Web Interface WEB INTERFACE allows you to view products’ features, Guides, FAQs, Sample dofiles. This Conformal feature is enabled by starting a server from any Conformal tools. It does not require any additional licenses and runs concurrently with the main program. The server is automatically shut down when you exit the tool.



Starting the Server



To start the server for web browser viewing, use the “set web on -browser” command as follow

Set web on –browser 

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LEC will bring up the browser with the appropriate Web Interface starting page


Web Interface • Documentation

11


• Current directory



Module 1

Flat Comparison Flow

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Flat Comparison Flow Golden Design

Standard Library

Revised Design

Specify Constraints and Design Modeling

Setup Mode LEC Mode

Specify Compare Parameters

Compare Designs

Miscompare?

yes

no

Equivalence Checking Complete 13


Diagnose

LEC Flow SETUP

LEC

Specifying blackboxes Reading libraries and designs Specifying design constraints Specifying modeling directives Mapping process Resolving unmapped key points Compare process Debugging nonequivalent key points

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Setting Blackboxes and Reading Designs Run

the blackbox command before a module is read in:

add notranslate module *ram* –library –both You

can read Verilog library and design files at the command line:

add search path /user1/rtl/ -golden read design *.v –verilog –golden add search path /user1/verilog/ -lib -revised read library library.v -verilog –revised read design revised.v –verilog –revised

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Design Constraints Design

constraints are user’s inputs that control part of a design’s logic. After Conformal successfully reads the designs and libraries, you can place constraints on the designs to do the following:

scan_in U DFF scan_en (0) 1

CLK

U 0 DFF 1s 1

CLK Revised

Golden

Ties U1 DFF output to 0 U1 DFF

0

U1 DFF

CLK

CLK

– Exclude sections of a design from verification. add pin constraint 0 scan_en -revised add instance constraint 0 U1 –revised

– Specify behavior, such as one-hot or one-cold. – Specify relationships, such as pin equivalence. add pin equivalence CLK -revised

–invert

CLK_n \

DLAT

DLAT

DLAT

CLK CLK_n

GND

SET

SET DFF

DFF

– Constrain internal nets, such as primary input, primary output, and tied signals. add tied signal 0 GND -net –revised set undriven signal 0 –revised

Z

0 DFF

– Constrain instances, such as instance equivalence. – Constrain feedback. add cut point /U1/net1 -revised

DFF

CLK

U1

CLK

net1

Z DLAT

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DLAT

CLK

Modeling Directives Modeling directives are needed to handle modeling styles specific to vendor libraries or synthesis tools. en latch

DFF



Examples of Modeling Options

CLK in1

in1

Revised

RegB

RegA

RegB

RegC

RegA1

RegC

RegB

–all_seq_merge

All other modeling options are optional with an XL license:

D0 RegA

Golden

set flatten model –sequential_redundant

Run analyze setup for the rest of the modeling options. © 2012 Cadence Design Systems, Inc. All rights reserved.

in1

PO

D0

– Sequential redundant

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1’b1

Golden

–seq_constant

– Sequential merging 

1’b1 PO

DFF

– Sequential constant

set flatten model

PO

1’b1

set flatten model –gated_clock

DFF

Revised

– Clock gating

set flatten model

DFF

en CLK Golden

DFF

RST Golden

RegA

RegC

Revised

PO CLK

D0

DFF

PO

PO

DFF CLK

CLK

RST

RST Revised

Switching to LEC Mode set system mode lec When

you change modes from Setup to LEC:

– Golden and Revised designs are flattened. – Circuit modeling is performed. – Automatic key point mapping take places after circuit modeling. All

of the steps above happen with one command. set log file logfile.$LEC_VERSION -replace add notranslate module *sram* -library -both read design cpu_rtl.v -verilog -golden read design -file verilog.vc -verilog -revised add pin constraint 0 scan_en -revised set flatten model -latch_fold

set system mode lec ...

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How Is Mapping Done? What Is Key Point Mapping? Pairing corresponding golden and revised key points: G

R

PI PI PO PO

Key points

DFF DFF

Combinatorial logic

DLAT DLAT BBOX BBOX

Revised

Golden

CUT CUT Z Z E E

SET MApping Method

- name first //default

Name-based

Followed by Function-based /core/fd 0

A B

DFF

CK

BB

DFF

CK Golden

19

/core/fd 0

A

A

/core /fd 0

A

B

DFF

B

CK Revised

/core_fd [0]

DFF

CK Golden

Revised


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Mapping Manager Choose

Tools – Mapping Manager to open the Mapping Manager, or click the mapping manager icon. Red-filled circle in unmapped points indicates problems.

Unmapped points

Not-mapped Mapped points

Extra Compared points

Unreachable To show only unmapped points:

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1.

Choose Preference — Sort by name.

2.

Choose Class — Disable All.

3.

Choose Class — Not-Mapped.


E U

Messages Example

of reported messages:

LEC> report messages Transcript window // Command: report messages Report modeling message for Golden F34: converted X assignment(s) as don ’t care(s) (Occurrence: 78) Report modeling message for Revised F5: Folded DLAT(s) into DFF(s) (Occurrence: 340) ... Transcript window // Warning: more than 1/3 of the key points have mis-matched names ...

Mapping

Takes Too Long

– Interrupt the mapping process: Control-c in a UNIX window. – To remap using the “name only” method, enter LEC> delete mapped points -all LEC> set mapping method -name only LEC> map key points 21


Add and Test Renaming Rules Window In the Conformal LEC window, choose Setup  Renaming Rule to open the Renaming Rule window.  You can add, test, and edit rules in this window. 

Middle-click on a key point in the mapping manager to copy the contents. Middle-click to paste the contents. Test a new rule before adding it.

Dofile now has:

add renaming rule rule0 "abc" "xyz” -revised add renaming rule rule2 … 22


Comparison Compare

points are sink points of logic cones, for example:

– Primary outputs (PO), cut gates, DFFs, D-latches, and blackboxes (BBOX) – Only mapped points can be compared. – Comparison is an iterative process. – Conformal remembers points already compared. – Comparison can be interrupted with Control-c. – Enter compare to continue comparing.

add compare points -all compare

/fd0 PO

DFF /bb0 IN_0 IN_1

OUT_0 OUT_1

BLACKBOX 23


Comparison Results

All nonequivalences and aborts need to be resolved.

Transcript window // Command: compare ================================================================================ Compared points PO DFF DLAT BBOX Total -------------------------------------------------------------------------------Equivalent 2 146 2 1 151 -------------------------------------------------------------------------------Non-equivalent 0 2 0 0 2 ================================================================================

Filtering comparison results with the Mapping Manager

Status indicators

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?

Equivalent Inverted-Equivalent Nonequivalent Abort Not-Compared


Split status indicators show top-level sequential merge instances equivalence: Design – Equivalent Sequential Merge – Equivalent Design – Equivalent Sequential Merge – Abort

Displaying Debug Information – Opening the Diagnosis Manager Use

the Mapping Manager to debug:

To display only nonequivalent results and sort them to show smaller cones first: 1.

Choose Class —Disable All

2.

Choose Class — Non-Equivalent

3.

Click the AZ↑↓ icon and select Sort by Support Size



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To display the Diagnosis Manager: 1. Click left to select a nonequivalent point (red-filled circle). 2. Click right and select Diagnose.


Diagnosis Manager A

1

1

1 1 D

1

Golden

seq0

DFF

11 D QQ

seq1

DFF CP

A

1 1 0

1

seq0 Revised

D

0 0

D

Color-coded support points

Q

DFF

1 Q Q

Red: Nonequivalent points

seq1

Green: Equivalent points

DFF CP

B

1 1

0

Error Candidates Noncorresponding Support Noncorresponding, and not mapped (red) M

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Noncorresponding but mapped (yellow with M) © 2012 Cadence Design Systems, Inc. All rights reserved.

- Points to possible root cause - Highlighted in GUI

Crosshighlighting of support key point and error pattern

Black: Points will not be or are not yet compared Brown: Abort points

Schematic Viewer Open

the schematic viewer from the diagnosis manager.

Right-click on any gate to open it’s fanin or fanout cones.

Double-click any gate to open Source Code.

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Source Code Manager From

the Diagnosis Manager or the Schematic, you can open the Source Code Manager.

Signals can be traced across module boundaries.

Driver and load tracing can be enabled using set hdl diagnosis on

before reading designs.

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Analyze Commands

XL License Required

If

you have mapping issues after trying renaming rules, run analyze setup command to automatically resolve setuprelated issues. analyze setup –verbose If

you have aborts in a design with a lot of datapath components, run the analyze datapath command. analyze datapath -verbose If

you have aborts, run the analyze abort command after the initial comparison to resolve the aborts: // compare analyze abort –compare –threads 4

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Sample Dofile For Flat-Compare Flow set log file lec.flat.log.$LEC_VERSION -replace usage -auto -elapse read library -replace -both

./lib/library.v

read design

./rtl/top.v

-replace -golden

read design -replace -revised

./syn/top.gv

report design data report black box // Specify user renaming rules if needed to help mapping add renaming rule rule1 "reg__%d" "reg[@1]" -revised // Specify user constraints for test add pin constraint 0 scan_en add ignore output

-both

scan_out -both

// Specify modeling directives for constant optimization & clock-gating set flatten model

-seq_constant -gated_clock

// Enable parallel processing, 4 threads set parallel option -threads 4 // Flattening, remodeling, mapping the design set system mode lec // Enable auto analysis to help resolving setup issues analyze setup -verbose // Comparison add compare point -all compare

// Automatic attempt to resolve abort points if any analyze abort -compare 30


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Sample Dofile For Flat-Compare Flow with Datapath set log file lec.flat.log.$LEC_VERSION -replace usage –auto -elapse read library -replace -both

./lib/library.v

read design

./rtl/top.v

-replace -golden

read design -replace -revised

./syn/top.gv

report design data report black box // Specify user renaming rules if needed to help mapping add renaming rule rule1 "reg__%d" "reg[@1]" -revised // Specify user constraints for test add pin constraint 0 scan_en add ignore output

-both

scan_out -both

// Specify modeling directives for constant optimization & clock-gating set flatten model

-seq_constant -gated_clock

// Enable parallel processing, 4 threads set parallel option -threads 4 // Flattening, remodeling, mapping the design set system mode lec // Enable auto analysis to help resolving setup issues analyze setup -verbose // Run analyze datapath on aborts in a design with a lot of datapath components analyze datapath –verbose // Comparison add compare point -all compare // Automatic attempt to resolve abort points if any © 2012 Cadence Design Systems, Inc. All rights reserved.

31 analyze

abort -compare

31



Module 2

Hierarchical Comparison Flow

32


What Is Hierarchical Comparison Flow? Hierarchical

comparison is a bottom-up, module-by-module

comparison. – It is done automatically with a tool-generated script or .do file – Requirement: Design must contain some hierarchy – Benefits: Shorter runtime, easier to debug TOP

TOP

U3 U1

U2

A

Golden

33

U3

U4


B

U1

U4 U2 Revised

X

Constraint Propagation Top-level

constraints must be propagated to the lower-level modules to prevent errors during comparison. To automatically propagate constraints to all lower-level modules, use the -constraint option when generating the hierarchical dofile. Golden

Revised

TOP

TOP U1

U1 scan_en

U2

SETUP> SETUP> SETUP> SETUP> SETUP>

SE_0 SE_1

U2

set log file hier.log -replace read design rtl.v -verilog -golden read design -file verilog.vc gate.v -revised

add pin constraint 0 scan_en –revised write hier dofile hier.do –constraint \ –noexact_pin_match –replace -balanced_extraction … SETUP> run hier_compare hier.do 34


Dynamic Hierarchical Comparison Using

– – – – –

XL License Required

dynamic hierarchical comparison, you can

Generate the hierarchical .do file only once Analyze aborts automatically during comparison Stop at the first nonequivalent or the first abort result Compare any submodules more easily Interrupt with Control-C and continue where left off

SETUP> RUN HIER_COMPARE hier.do -Break_Noneq -Break_Abort

The hier.do file used in the run hier_compare command is generated using this command: write hier_compare -run_hier_compare dofile hier.do

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Sample Dofile For Hierarchical Comparison Flow set log file lec.flat.log.$LEC_VERSION -replace usage -auto read library -replace -both ./lib/library.v read design -replace -golden ./rtl/top.v read design -replace -revised ./syn/top.gv report design data report black box // Specify user renaming rules if needed to help mapping add renaming rule rule1 "reg__%d" "reg[@1]" –revised // Specify user constraints for test add pin constraint 0 scan_en -both add ignore output scan_out –both // Specify modeling directives for constant optimization & clock-gating set flatten model -seq_constant -gated_clock // Enable parallel processing, 4 threads set parallel option -threads 4 // Enable auto analysis to help resolving setup issues set analyze option -auto // Generate & execute the hierarchical dofile script for hier comparison write hier_compare dofile hier.do -replace -usage \ -constraint -noexact_pin_match \ -prepend_string "report design data; usage ; analyze datapath -module -resourcefile -verbose; usage; \ analyze datapath -verbose; usage" \ -balanced_extraction -input_output_pin_equivalence -function_pin_mapping run hier_compare hier.do 36


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LEC Jumpstart Training Overview

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