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PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
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Flow Graph, Pseudo Code
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Logic Design
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Transistor Layout Manufacturing
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PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
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• UL>*-55 12 6-*10/3 12 ;-*E5 /W ;*:;< ;)90- Y/20B KB 15 5
primitive carry (Cy, A, B, C); input A, B, C; output Cy; table // A B C Cy 1 1 ? : 1 ; 1 ? 1 : 1 ; ? 1 1 : 1 ; 0 0 ? : 0 ; 0 ? 0 : 0 ; ? 0 0 : 0 ; endtable endprimitive
UL>*-55 12 6-*10/3 12 ;-*E5 /W a//0-)2 -L>*-551/25 module carry (S, Cy, A, B, C); input A, B, C; output S, Cy; assign assign endmodule
S = A ^ B ^ C; Cy = (A & B) | (B & C) | (C & A);
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module add (cy_out, sum, a, b, cy_in); input a, b, cy_in; output sum, cy_out; sumx,s1y); (sum, a, b, cy_in); module add4 (s, cy4, cy_in, carry c1 (cy_out, a, b, cy_in); input [3:0] x, y; endmodule input cy_in; output [3:0] s; output cy4; wire [2:0] cy_out; add B0 (cy_out[0], s[0], x[0], y[0], ci); add B1 (cy_out[1], s[1], x[1], y[1], cy_out[0]); add B2 (cy_out[2], s[2], x[2], y[2], cy_out[1]); add B3 (cy4, s[3], x[3], y[3], cy_out[2]); endmodule ()*+,)*- ./+-0123 45123 6-*10/3
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module sum (sum, a, b, cy_in); input a, b, cy_in; output sum; wire t; xor x1 (t, a, b); xor x2 (sum, t, cy_in); endmodule
"%
module carry (cy_out, a, b, cy_in); input a, b, cy_in; output cy_out; wire t1, t2, t3; and g1 and g2 and g3 or g4 endmodule
(t1, a, b); (t2, a, c); (t3, b, c); (cy_out, t1, t2, t3);
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module add4; input x[3:0], y[3:0], cy_in; output s[3:0], cy4; boundary [0, 0, 130, 500]; port x[0] aluminum width = 1 origin = [0, 35]; port y[0] aluminum width = 1 origin = [0, 85]; port cy_in polysilicon width = 2 origin = [70, 0]; port s[0] aluminum width = 1 origin = [120, 65]; add a0 add a1 endmodule
origin origin
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[0, 0]; [0, 120];
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Logical design (front-end CAD)
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Floorplanning Placement
Circuit Extraction
Physical design (back-end CAD)
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PROF. INDRANIL SENGUPTA DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
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module testbench; reg A,B,C,D,E,F; wire Y; example DUT(A,B,C,D,E,F,Y);
0 A=x, B=x, C=x, D=x, E=x, F=x, Y=x
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module initial begin $monitor ($time,” A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b”, A,B,C,D,E,F,Y); #5 A=1; B=0; C=0; D=1; E=0; F=0; #5 A=0; B=0; C=1; D=1; E=0; F=0; #5 A=1; C=0; #5 F=1; #5 $finish; end endmodule
wire
example (A,B,C,D,E,F,Y); t1, t2, t3, Y;
nand #1 and #2 nor #1 nand #1 endmodule
G1 G2 G3 G4
(t1,A,B); (t2,C,~B,D); (t3,E,F); (Y,t1,t2,t3);
5 A=1, B=0, C=0, D=1, E=0, F=0, Y=x 8 A=1, B=0, C=0, D=1, E=0, F=0, Y=1 10 A=0, B=0, C=1, D=1, E=0, F=0, Y=1 13 A=0, B=0, C=1, D=1, E=0, F=0, Y=0 15 A=1, B=0, C=0, D=1, E=0, F=0, Y=0 18 A=1, B=0, C=0, D=1, E=0, F=0, Y=1 20 A=1, B=0, C=0, D=1, E=0, F=1, Y=1 2.EE"$6 #$ #;)4#8.9S a) iverilog -o mysim example.v example-test.v b) vvp mysim
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module testbench; reg A,B,C,D,E,F; wire Y; example DUT(A,B,C,D,E,F,Y); initial begin $dumpfile (“example.vcd”); $dumpvars (0,testbench); $monitor ($time,” A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b”, A,B,C,D,E,F,Y); #5 A=1; B=0; C=0; D=1; E=0; F=0; #5 A=0; B=0; C=1; D=1; E=0; F=0; #5 A=1; C=0; #5 F=1; #5 $finish; end endmodule
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2.EC"4#-.$ ME.$9 ;"4#.3- ?)-#9$ =0V8)Design Style FPGA
Gate array
Standard cell
Full custom
Cell size
Fixed
Fixed
Fixed height
Variable
Cell type
Programmable
Fixed
Variable
Variable
Cell placement
Fixed
Fixed
In row
Variable
Interconnect
Programmable
Variable
Variable
Variable
Design time
Very fast
Fast
Medium
Slow
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