Implementation of some basic hardware designs at FPGA using VERILOG
A project under Dr. Praveen Kumar Associate Professor Department of Electronics and Electrical Engineering Indian Institute of Technology, Guwahati
Submitted By Anki t Kumar Kumar Gar Gar g Vinay Giri th
B. Tech (7 semester) National Institute Institute of Technology Arunachal Pradesh
ACKNOWLEDGEMENT Every project big or small is successful largely due to the effort of a number of wonderful people who have always given their valuable advice or lent a helping hand. I sincerely appreciate the inspiration; support and guidance of all those people who have been instrumental instrumental in making this project a success. We, the student of NIT Arunachal Pradesh (Dept. of EEE), are extremely grateful to “Dr. Praveen Kumar” for the confidence bestowed in us and entrusting our project. At this juncture we feel deeply honored in expressing my sincere thanks to Mr. Upendra at IITG for making the resources available at right time and providing valuable insights leading to the successful completion of my project. I express my gratitude to Mr. Abhishek Kumar, Asst. Professor, Dept. of EEE EEE at NIT AP AP for arranging arranging the summer training in good schedule and assisting us in compiling the project. Last but not the least we place a deep sense of gratitude to our family members and our friends who have been constant source of inspiration during the preparation of this project work.
CONTENTS 1. Introduction 1.1. HDL 1.2. Verilog HDL 1.3. VHDL 1.4. Standardization of Verilog 1.5. FPGA 2. Modeling concepts with Verilog HDL 2.1. Modules & port 2.2. Instances 2.3. Components of simulation 2.3.1.1. Design Block 2.3.1.2. Stimulus Block 3. Gate level modeling 3.1. Gate types 3.2. Designing of 4*1 multiplexer with gate level modeling 3.3. Designing of 16 bit Full Adder 4. Data flow modeling 4.1. Designing of 4*1 multiplexer with data flow modeling 4.2. Designing of Full Adder with data flow modeling 4.3. Designing of 4 bit multiplication with data flow modeling
5. Behavioral Modeling 5.1. Structured procedures 5.2. Procedural assignment 5.3. Timing control 5.4. Conditional statement 5.5. Loops 6. Designing of 32 bit Floating Point Adder 6.1. Standard IEEE 754 6.2. Programme Programme written in Verilog
7. Designing of PWM generator 8. Conclusion 9. Reference
1. INTRODUCTION The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented, where logic gates were placed on a single chip. The first IC was SSI (Small Scale Integration), chips where the gate count was very small. Later with the advent of MSI and LSI design process started getting very complicated and the designer felt the need for automate the processes. Computer aided designing techniques were began to involve. With the advent of VLSI technology because of the complexity of these circuits it was not possible to verify these circuits on the bread board. Logic simulators came into existence to verify the functionality of these circuits before they were fabricated on chip. 1.1. HDL
A hardware description language or HDL is a specialized computer language used to program the structure, design and operation of electronic circuits, and most commonly, digital logic circuits. A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis, simulation, and simulated testing of an electronic circuit. A hardware description language looks much like a programming programming language such as C; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time. With the advent of HDLs designers no longer have to manually place gates to built digital circuits. They could describe in the form of data flow or functionality. HDL are used for simulation of system boards, interconnect buses, FPGAs (Field Programmable Gate Array) and PALs (Programmable Array Logic).
1.2. Verilog HDL
Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit (IC) designers. The other one is VHDL. Verilog allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. Verilog can be used to describe designs at four levels of abstraction: 1. Algorithmic level (much like c code with if, case and loop statements). 2. Register transfer level (RTL uses registers connected by Boolean equations). 3. Gate level (interconnected AND, NOR etc.). 4. Switch level (the switches are MOS transistors inside gates). The language also defines constructs that can be used to control the input and output of simulation. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description (a net list) for the circuit. Although some Verilog constructs are not synthesizable on FPGA boards, still it is most popularly used language for for hardware description. description.
1.3. VHDL
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. It can describe the behavior and structure of electronic systems, but is particularly suited as a language to describe describe the structure and behavior of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional MSI circuits.
The development of VHDL was initiated in 1981 by the United States Department of Defense (DoD) to address the hardware life cycle crisis. The cost of reproducing electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology.
1.4. Standardization of Verilog By 1990, Cadence began to feel the pressure of selling a proprietary product (Verilog) against an open standard product (VHDL). Consequently, he organized Open Verilog International (OVI), and in 1991 gave it the documentation for the Verilog Hardware Description Language. This was the event which "opened" the language. Subsequently, OVI did a considerable amount of work to improve the Language Reference Manual (LRM), clarifying things and making the language specification as vendor-independent as possible. In 1994, the IEEE 1364 working group was formed to turn the OVI LRM into an IEEE standard. This effort was concluded with a successful ballot in 1995, and Verilog became an IEEE standard in December, 1995. Now, Verilog simulators are available for most computers at a variety of prices, and which have a variety of performance characteristics and features. Verilog is more heavily used than ever. It has truly become a standard hardware description language.
1.5. FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after
manufacturing – hence "field programmable". programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). The internal architecture of an FPGA consist of several uncommitted logic blocks in which the design is to be encoded. The internal logic blocks consist of several universal gates that can be programmed programmed to operate like multiplexer’s logic gate transistors and RAMs. The internal cell blocks are connected through different Figure 1: Digilent NEXYS 2 FPGA Board types of devices such as static RAM, EEPROM. In conclusion, FPGA’s offer low risk, low cost, low stress, high density and high speed-performance. The FPGA kit used in our project is appropriate for testing and verification and has proven to be very important tool for successful project implementation.
2. Modeling concepts with Verilog HDL A digital simulation is made up of various components. For an efficient Verilog based design designer must use a good design methodology, top-down and bottom-up. 2.1. Modules & Port: The module is the basic unit of hierarchy in Verilog. Modules describe boundaries [module, end module], inputs and outputs ports.
It can be a single element or collection of lower level modules. The Module can describe a hierarchical design (a module module of modules). modules). A module should be contained within one file. file . Ports provide an interface by which a module can communicate with its environment. The environment can communicate with the module only through these ports.
2.2. Instances: Modules can be instantiated from within other modules. When a module is instantiated, connections to the ports of the module must be specified. There are two ways to make port connections. One is connection by name, in which variables connected to each of module inputs or outputs are specified in a set of parenthesis following the name of the ports. In this method order of connections is not significant. The second method is called ordered connection. In this method the order of the ports must match the order appearing in the instantiated module. When ports are connected by name it is illegal to leave any ports unconnected. This may occur when ports are connected by order. 2.3. Components Components of simulation: 2.3.1. Design Block: In design block we simply write the Verilog code for a specified function by using a specified methodology. 2.3.2. Stimulus Block: Once the design block is completed, it must be tested. The functionality of the design block can be tested by applying stimulus and checking result. We call such a block the stimulus block. It is also also general called as test-bench. test-bench.
3.Gate 3. Gate Level Modeling Gate level design is second lowest level of abstraction. Most digital designs are done at this level. At this level the circuit is described in
terms of gates. Design at this level is very intuitive for the user with the very basic knowledge of digital circuits. 3.1. Basic Gates: These implement the basic logic gates. They have one output and one or more inputs. In the gate instantiation syntax shown below, gate stands for one of the keywords And, Nand, or, Nor, Xor, Xnor. Syntax GATE (drive strength) # (delays) instance_name1 (output, input_1, input_2, input_n), instance_name2 (out, in1, in2,..., inN); 3.2. Designing of 4*1 multiplexer with gate level modeling:
We have designed a 4*1 multiplexer with the help of gate level design. Here we have 4 inputs and one output, according to the selection line we will choose our output. The programe is as following. module multiplexer(out, multiplexer(out, i0, i1, i2, i3, s1, s2); output out; input i0,i1,i2,i3; input s1,s2; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not(s0n,s0); and(y0,i0,s1n,s0n); and(y1,i1,s1n,s0n); and(y2,i2,s1,s0n); and(y3,i3,s1,s0); or (out,y0,y1,y2,y3); endmodule The test bench for the above described module is as following: module mutiplexer_tb; mutiplexer_tb; // Inputs reg i0, i1, i2, i3, s1, s2;
// Outputs wire out;
Figure 2: Simulation result of 4*1 multiplex multiplexer er
// Instantiate the Unit Under Test (UUT) multiplexer uut ( .out(out), .i0(i0),.i1(i1), .i2(i2), .i3(i3), .s1(s1), .s2(s2) initial begin // Initialize Inputs i0 = 0;i1 = 0;i2 = 0;i3 = 0;s1 = 0; s2 = 0; // Wait 100 ns for global reset to finish #100; #1 s1= 1; #2 s2=1; #1 s1=0; #1 s2=1; end endmodule
);
3.3. Designing of 16 bit full adder: We have designed a 16 bit full adder, where the full adder with carry has been instantiated 16 times to add as following. module adder16bit_notdefoult adder16bit_notdefoult (a,b,c_in,sum,c_out); input [15:0] a,b,c_in; output [15:0] sum, c_out; HAlfAdder add1 (a[0], b[0], 0, sum[0], c_out[0]); HAlfAdder add2 (a[1], b[1], c_out[0], sum[1], c_out[1]); HAlfAdder add3 (a[2], b[2], c_out[1], sum[2], c_out[2]); HAlfAdder add4 (a[3], b[3], c_out[2], sum[3], c_out[3]); HAlfAdder add5 (a[4], b[4], c_out[3], sum[4], c_out[4]); HAlfAdder add6 (a[5], b[5], c_out[4], sum[5], c_out[5]); HAlfAdder add7 (a[6], b[6], c_out[5], sum[6], c_out[6]); HAlfAdder add8 (a[7], b[7], c_out[6], sum[7], c_out[7]); HAlfAdder add9 (a[8], b[8], c_out[7], sum[8], c_out[8]); HAlfAdder add10 (a[9], b[9], c_out[8], sum[9], c_out[9]); HAlfAdder add11 (a[10], b[10], c_out[9], sum[10], c_out[10]); HAlfAdder add12 (a[11], b[11], c_out[10], sum[11], c_out[11]); HAlfAdder add13 (a[12], b[12], c_out[11], sum[12], c_out[12]); HAlfAdder add14 (a[13], b[13], c_out[12], sum[13], c_out[13]); HAlfAdder add15 (a[14], b[14], c_out[13], sum[14], c_out[14]); HAlfAdder add16 (a[15], b[15], c_out[14], sum[15], c_out[15]); endmodule module HAlfAdder(input a,input b,input c_in,output sum,output c_out); wire s1,c1,c2; xor (s1,a,b); and (c1,a,b); xor(sum,s1,c_in); and(c2,s1,c_in); or (c_out,c2,c1); endmodule module adder16bit_notdefoult_tb adder16bit_notdefoult_tb;; // Inputs
reg [15:0] a; reg [15:0] b;
reg [15:0] c_in;
Figure 3: Simulation result of bit full adder // Outputs wire [15:0] sum; wire [15:0] c_out;
// Instantiate the Unit Under Test (UUT) adder16bit_notdefoult adder16bit_notdefoult uut ( .a(a), .b(b), .c_in(c_in), .sum(sum), .c_out(c_out) ); Initial begin // Initialize Inputs a = 0; b = 0; c_in = 0; a=16'b0000000000000011; b=16'b0000000000000011; b=16'b0000000000000011; // Add stimulus here end endmodule
4.Data flow modeling Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design. The gate level modeling becomes very complex for a VLSI circuit. Hence dataflow modeling became a very important way of implementing the design. In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value onto a net. The continuous assignments are made using the keyword assign The assign statement: The assign statement is used to make continuous assignment in the dataflow modeling. The assign statement usage is given below: assign out = in0 + in1; // in0 + in1 is evaluated and then assigned to out.// 4.1. Design of 4*1 multiplexer multiplexer with the dataflow modeling:
module mux_4x1 (out, in0, in1, in2, in3, s0, s1); output out; input in0, in1, in2, in3; input s0, s1; assign out = (~s0 & ~s1 & in0)|(s0 & ~s1 & in1)| (~s0 & s1 & in2)|(s0 & s1 & in0); endmodule
4.2. Design of full adder with the data data flow modeling: modeling: module full_adder (sum, c_out, in0, in1, c_in); output sum, c_out; input in0, in1, c_in; assign { c_out, sum } = in0 + in1 + c_in; endmodule
4.3. Designing of 4 bit multiplication with data flow modeling: module multiplication4bit_not multiplication4bit_notdefoult(pro defoult(product,inp1,inp2,clo duct,inp1,inp2,clock); ck); output [7:0]product; [7:0]product; input input [3:0]inp1; [3:0]inp1; input input [3:0]inp2; [3:0]inp2; input input clock; wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17; assign product[0] = (inp1[0]&inp2[0]); (inp1[0]&inp2[0]); HA HA1(product[1],x1,(inp1[1]& HA1(product[1],x1,(inp1[1]&inp2[0]),(in inp2[0]),(inp1[0]&inp2[1 p1[0]&inp2[1])); ])); FA FA1(x2,x3,(inp1[1]&inp2[1] FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]& ),(inp1[0]&inp2[2]),x1); inp2[2]),x1); FA FA2(x4,x5,(inp1[1]&inp2[2] FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]& ),(inp1[0]&inp2[3]),x3); inp2[3]),x3); HA HA2(x6,x7,(inp1[1]&inp2[3]) HA2(x6,x7,(inp1[1]&inp2[3]),x5); ,x5); HA HA3(product[2],x15,x2,(inp1[2] HA3(product[2],x15,x2,(inp1[2]&inp2[0]) &inp2[0])); ); FA FA5(x14,x16,x4,(inp1[2]&inp2[1] FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15); ),x15); FA FA4(x13,x17,x6,(inp1[2]&inp2[2]) FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16); ,x16); FA FA3(x9,x8,x7,(inp1[2] FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17 &inp2[3]),x17); ); HA HA4(product[3],x12,x14,(inp1[3] HA4(product[3],x12,x14,(inp1[3]&inp2[0]) &inp2[0])); ); FA FA8(product[4],x11,x13,(inp1[3]& FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12 inp2[1]),x12); ); FA FA7(product[5],x10,x9,(inp1[3]&i FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11); np2[2]),x11); FA FA6(product[6],product[7],x8 FA6(product[6],product[7],x8,(inp1[3]&inp ,(inp1[3]&inp2[3]),x10); 2[3]),x10); endmodule module HA(sout,cout,a,b); output sout,cout; output sout,cout; input input a,b; a,b; assign assign sout sout = a^b; assign assign cout cout = (a&b); endmodule module FA(sout,cout,a,b,cin); FA(sout,cout,a,b,cin); output sout,cout; output sout,cout; input a,b,cin; input a,b,cin; assign sout assign sout =(a^b^cin); assign cout assign cout = ((a&b)|(a&cin)|(b&cin)); ((a&b)|(a&cin)|(b&cin)); endmodule
5. Behavioral Modeling Behavioral modeling is higher level of modeling in which programs are written at the algorithmic level. Verilog behavioral code is inside procedural blocks, but there is an exception: some behavioral code also exists outside procedure blocks. 5.1. Structured Procedures: There are two types of structure procedures in Verilog: Initial: initial block execute only once at time zero (start execution at time zero). Always: Always block executes over and over again. In other words as the name suggests it executes always. 5.2. Procedural assignment: Procedural assignment statements assign values to reg, integer, real, or time variables and cannot assign values to nets (wire data types). We can assign to a register (reg data type) the value of a net (wire), constant, another register, or a specific value. There are two types of assignment 1. Blocking assignments 2. Non-Blocking assignment assignment
Blocking assignments are executed in the order they are coded, hence they are sequential. Since they block the execution of next statement, till the current statement is executed, they are called blocking assignments. assignments. Assignment are made made with "=" symbol Non-blocking assignments are executed in parallel. Since the execution of next statement is not blocked due to execution of current statement, they are called non-blocking statement. Assignments are made with "<=" symbol. Example a <= b;
5.3. Timing control This specifies the delay time units before a statement is executed during simulation. A delay time of zero can also be specified to force
the statement to the end of the list of statements to be evaluated at the current simulation time. Syntax #delay statement; 5.4. Conditional Statements:
Conditional statements are used for making decision on certain condition. These conditions are going to decide, whether or not a statement is going to be executed. Keyword if-else are used for conditional statement. There are three types of conditional statements. 1. If (expression) true statement; 2. If (expression) true statement; else (expression) true statement; 3. if (expression) true statement; Else If (expression) true statement; Else If (expression) true statement; Else default; 5.5. Loops:
There are four types of looping statements in Verilog: while, for, repeat, forever. The syntax for these loops are very similar to the syntax in c programming language. All looping statements can only appear inside an initial or always block.
6.Designing 6. Designing of 32 bit Floating Point Adder The floating point arithmetic is clearly the most efficient way of representing real numbers in computers. Representing an infinite, continuous set (real numbers) with a finite set (machine numbers) is not an easy task: some compromises must be found between speed, accuracy, ease of use and implementation and memory cost. Floating Point Arithmetic represent a very good compromise for most numerical applications.
The floating point numbers representation is based on the scientific notation: the decimal point is not set in a fixed position in the bit sequence, but its position is indicated as a base power. All the floating point numbers are composed composed by three components: components: · Sign: it indicates the sign of the number (0 positive and 1 negative) · Mantissa: it sets the value of the number Exponent: it contains the value of the base power (biased) · Base: the base (or radix) is implied and it is common to all the numbers (2 for binary numbers) 6.1. Standard IEEE 754:
Standard IEEE 754 specifies formats and methods in order to operate with floating point arithmetic . These methods for computational with floating point numbers will yield the same result regardless the processing is done in hardware, software or a combination for the two or the implementation. For single precision 32 bit number 1 bit is signed bit then next 8 bits are exponent bits and then next 23 bits are mantissa bits. Exponent and mantissa values determine the different number r cases that it can be had. 8 · If E = 2 -1 and T ¹ 0, then r is NaN regardless of S 8 · If E = 2 -1 and T = 0, then r is ±infinity according with the sign bit S · If 1 £ E £ 2w - 2, then t hen r is a normal number · If E = 0 and T ¹ 0, then r is a subnormal number · If E = 0 and T = 0, then r is ±zero according with S 6.2. Programme Programme written in Verilog module floatingpointadder floatingpointadder (a, b, sum); output [31:0] sum; input [31:0] a,b; a,b ; //in SEEEEEEEEFFFFFFFFFFFFFFFFFF SEEEEEEEEFFFFFFFF FFFFFFFFFFFFFFF// FFFFF// wire [31:0] wire [31:0] sum; wire [7:0] wire [7:0] EA, EB, ES, es;
the
form
of
wire [22:0] MA, MB, MS, ma, mb; wire [22:0] wire sign_sum, wire sign_sum, sign_a, sign_b; wire [1:0 wire [1:0 ]result, result1, result2 ; wire [7:0] wire [7:0] diff_exp; reg [7:0]j reg [7:0]j = 0; assign sign_a=a[31]; assign sign_a=a[31]; assign sign_b=b[31]; assign EA=a[30:23]; assign EA=a[30:23]; //where actual exponent is a[30:23] - 127// assign EB=b[30:23]; assign EB=b[30:23]; assign MA=a[22:0]; assign MA=a[22:0]; assign MB=b[22:0]; assign MB=b[22:0]; assign diff_exp=EA-EB; diff_exp=EA-EB; compare comp1 (MA,MB,result1); compare comp2 (EA,EB,result2);
wire [2:0] wire [2:0] outa,outb; assign outa assign outa = (EA==8'b00000000 (EA==8'b00000000 && MA==0)? 3'b000: // zero// (EA==8'b00000000 (EA==8'b00000000 && MA>0)? 3'b001: //subnormal// (EA>8'b00000000 (EA>8'b00000000 && MA<255)? 3'b011: //normal// (EA==8'b11111111 (EA==8'b11111111 && MA==0)? 3'b100: //infinity// 3'b110; //NAN//
assign outb assign outb = (EB==8'b00000000 (EB==8'b00000000 && MB==0)? 3'b000: // zero// (EB==8'b00000000 (EB==8'b00000000 && MB>0)? 3'b001: //subnormal// //subnormal// (EB>8'b00000000 && MB<255)? 3'b011: //normal// (EB==8'b11111111 (EB==8'b11111111 && MB==0)? 3'b100: //infinity// 3'b110; //NAN//
assign sign_sum = (outa==000)? sign_b: //if number a=0// (outb==000)? (outb==000)? sign_a: //if number b=0// (outa[0]==1 && outb[0]==100)? sign_b: //number a (normal or subnormal) + number B (infinity)//
(outb[0]==1 && outa==100)? sign_a: sign_a : //number a(infinity) + number number b (normal or subnormal)// subnormal)// (outa==outb && outb==100 && sign_a==sign_b)? sign_a: // infinity+infinity// (outa==outb && outb==100 && sign_a!=sign_b)? 1: //infinityinfinity// (outa==110 && outb==110)? 1: //nan+nan// (outa==110 && outb[0]==1)? 1: //nan+-normal/subnormal// (outb==110 && outa[0]==1)? 1: //normal/subnormal+-nan// (outa==outb && outa==001 &&outa[31]==outb[31])? &&outa[31]==outb[31])? sign_a: // Both are subnormal with same sign// (outa==outb && outa==001 &&outa[31]!=outb[31] && result1==11)? result1==11)? sign_a: // Both are subnormal with opposite sign// (outa==outb && outa==001 &&outa[31]!=outb[31] && result1==00)? result1==00)? sign_b: // Both are subnormal with opposite sign// (outa==outb && outa==001 &&outa[31]!=outb[31] && result1==01)? result1==01)? sign_a: // Both are subnormal with opposite sign// (outa==001 && outb==011)? sign_b: // number a is subnormal and b is normal any sign// (outa==011 && outb==001 )? sign_a: sign_a : // number a is normal and b is subnormal with any sign// (outa==011 && outb==011 && result2==11)? result2==11)? sign_a: sign_a: // both are normal with EA >EB with any sign on both// (outa==011 && outb==011 && result2==00)? result2==00)? sign_b: sign_b: // both are normal with EA MB with opposite sign// (outa==011 && outb==011 && sign_a!=sign_b && result2==01 && result1 == 00 )? sign_b: sign_b : // both are normal with EA =EB and MA
(outa==011 && outb==011 && sign_a!=sign_b && result2==01 && result1 == 01 )? sign_a: sign_a : // both are normal with EA =EB and MA=MB with opposite sign// 1'bx; // default// //if number a=0// assign ES = (outa==000)? EB: (outb==000)? (outb==000)? EA: //if number b=0// (outa[0]==1 && outb[0]==100)? EB: //number a (normal or subnormal) + number B (infinity)// (outb[0]==1 && outa==100)? EA://number EA: //number a(infinity) + number b (normal or subnormal)// (outa==outb && outb==100 && sign_a==sign_b)? EA:// EA: // infinity+infinity// (outa==outb && outb==100 && sign_a!=sign_b)? 11111111: //infinity-infinity// (outa==110 && outb==110)? 11111111: //nan+nan// (outa==110 && outb[0]==1)? 11111111: //nan+normal/subnormal// (outb==110 && outa[0]==1)? 11111111: //normal/subnormal+nan// (outa==outb && outa==001 &&outa[31]==outb[31]) &&outa[31]==outb[31])?? 0: // Both are subnormal with same sign// (outa==outb && outa==001 &&outa[31]!=outb[31])? &&outa[31]!=outb[31])? MA-MB: // Both are subnormal with opposite sign// (outa==001 && outb==011 && sign_a==sign_b )? EB: // number a is subnormal and b is normal with equal sign// (outa==001 && outb==011 && sign_a!=sign_b)? EB: // number a is subnormal and b is normal with oppossite sign// (outa==011 && outb==001 && sign_a==sign_b )? EA: // number a is normal and b is subnormal with equal sign// (outa==011 && outb==001 && sign_a!=sign_b)? EA: // number a is normal and b is subnormal with oppossite sign// (outa==011 && outb==011 &&sign_a==sign_b && result2==11)? result2==11)? EA: // both are normal with EA >EB with any sign on both//
(outa==011 && outb==011 &&sign_a==sign_b &&sign_a==sign_b && && result2==00)? result2==00)? EB: // both are normal with EA
//if number a=0//
(outb==000)? (outb==000)? MA:
//if number b=0//
(outa[0]==1 && outb[0]==100)? MB: //number a (normal or subnormal) + number B (infinity)// (outb[0]==1 && outa==100)? MA: b (normal or subnormal)// subnormal)// (outa==outb && infinity+infinity//
outb==100
(outa==outb && outb==100 //infinity-infinity//
//number a(infinity) + number
&&
&&
sign_a==sign_b)?
sign_a!=sign_b)?
(outa==110 && outb==110)? 00000000000000000000001: 00000000000000000000001: //nan+nan// (outa==110 && outb[0]==1)? outb[0]==1)? 00000000000000000000001: 00000000000000000000001: //nan+-normal/subnormal// (outb==110 && outa[0]==1)? outa[0]==1)? 00000000000000000000001: 00000000000000000000001: //normal/subnormal+-nan//
MA:
//
23'bx1:
(outa==outb && outa==001 &&outa[31]==outb[31]) &&outa[31]==outb[31])?? MA+MB: // Both are subnormal with same sign// (outa==outb && outa==001 &&outa[31]!=outb[31])? &&outa[31]!=outb[31])? MA-MB: // Both are subnormal with opposite sign//
(outa==001 && outb==011 && sign_a==sign_b && EB>23)? MB: // number a is subnormal and b is normal with equal sign// (outa==001 && outb==011 && sign_a==sign_b && EB==23)? MB: // number a is subnormal and b is normal with equal sign// (outa==001 && outb==011 && sign_a!=sign_b && EB>23)? MB: // number a is subnormal and b is normal with oppossite sign// (outa==001 && outb==011 && sign_a!=sign_b && EB==23)? MB: // number a is subnormal and b is normal with oppossite sign// (outa==011 && outb==001 && sign_a==sign_b && EA>23)? MA: // number a is normal and b is subnormal with equal sign// (outa==011 && outb==001 && sign_a==sign_b && EA==23)? MA:// MA:// number a is normal and b is subnormal with equal sign// (outa==011 && outb==001 && sign_a!=sign_b && EA>23)? MA: // number a is normal and b is subnormal with oppossite sign// (outa==011 && outb==001 && sign_a!=sign_b && EA==23)? MA:// MA:// number a is normal and b is subnormal with oppossite sign// (outa==001 && outb==011 && sign_a==sign_b && EB<23)? ma+MB: // number a is subnormal and b is normal with equal sign// (outa==001 && outb==011 && sign_a!=sign_b && EB<23)? maMB: // number a is subnormal subnormal and b is normal with oppossite oppossite sign//
(outa==011 && outb==001 && sign_a==sign_b && EA<23)? MA+mb: // number a is normal and b is subnormal with equal sign// (outa==011 && outb==001 && sign_a!=sign_b && EA<23)? MAmb: // number a is normal and b is subnormal with oppossite sign//
(outa==011 && outb==011 &&sign_a==sign_b &&sign_a==sign_b && && result2==11) result2==11)?? MA+mb: MA+mb: // both both are normal with EA >EB with with same sign on both// (outa==011 && outb==011 &&sign_a==sign_b &&sign_a==sign_b && result2==00)? result2==00)? ma+MB: // both are normal with EA EB with opposite sign on both// (outa==011 && outb==011 &&sign_a!=sign_b &&sign_a!=sign_b && result2==00)? result2==00)? ma+MB: // both are normal with EA
// default//
always @(clk) begin for ( i=0; i>1 : ((outa==011 && outb==011 && result2==00)? MA>>1:MA); end for ( j=0; (j
begin assign mb = (outa==011 && outb==001 outb==00 1 && EA<23)? MB>>1 :(outa==011 && outb==011 && result2==11)? result2==11)? MB>>1 : MB; end end assign es assign es = ((MA+MB)>23'b11111111111111 ((MA+MB)>23'b11111111111111111111111)? 111111111)? EA+1: EA;
Figure 4: Simulation result of 32bit Floating Point Adder assign sum={sign_sum,ES,MS}; endmodule module compare (inp1, inp2, result); input [22:0] inp1,inp2; output [1:0]result; assign result = (inp1>inp2)? (inp1>inp2)? 00: (inp1
7.Designing of PWM Generator PWM has many applications such as controlling a servo motor, controlling light intensity in LEDs and it does it very efficiently. It works on the principles of switching the power on and off very quickly and therefore changing the average power supplied from the source. Having a periodic rectangular signal, we change the duty cycle (modulate) to be smaller or bigger and therefore control our device. Before the design, we must first think of what inputs and outputs are needed for the design. In our case, we have used 8 input switches from the FPGA board to control the PWM and 1 output pin to send the output signal. Our FPGA board has the clock frequency of 50Mhz. we want to get the output frequency as 50 Hz with our desired duty cycle. In our design we have produced three waveforms which are 120 degree apart from each other with 50Hz frequency. This waveform’s duty cycle vary according to our need.
8.Conclusion In our work, we have successfully implemented the programs written in Verilog language on FPGA. We have used DEGILENT FPGA board with inbuilt clock frequency of 50 MHz and with 8 sliding switches and four push buttons. The output has been observed with the help of oscilloscope. The programs were first simulated with
the help of ISim simulator on software and then the result was verified experimentally on the board.
9.Reference 1. http://www.asic-world.com/verilog_ctrl1.html 2. Samir Palnitkar, Palnitkar, Verilog HDL, A guide to digital design and synthesis 3. Verilog Coding for Logic Synthesis, Weng Fook Lee, Willey Publication 4. Vivek Sagdeo, The The Complete Complete Verilog Verilog Book 5. FPGA prototyping by Verilog examples, Pong P. Chu 6. Design of Single Precision Float Adder (32-bit numbers) according to IEEE 754 Standard Using VHDL, Arturo Barrabés Castillo 7. Verilog Tutorial By Sachin B. Patkar
