Implementation of Audio Tone Generator on FPGA Using Verilog HDL Coding Ms. Zinkal D. Bhatt Embedded system, EC Department, Nirma University, Ahmadabad- India
[email protected]
Abstract: - This Document Contain the Basic information about the Verilog HDL coding application for audio tone generator, FPGA is a digital logic chip that can be programmed to do almost any digital function. An effort has been carried out to make the FPGA to perform like a music tune. In this paper the Verilog HDL code for ambulance siren & police siren is implemented on FPGA Spartan -3 kit & using speaker outcome is noted. Xilinx software is used for simulation. Also the random tune is generated for the purpose of practise.
Furthermore, since theoretical knowledge is learned during lecture times, there is an opportunity to gain more hands-on experiment if the theory learned can be successfully be produced in an application.
Objectives The objectives of this project are listed as follow:
is a digital logic chip that can be programmed to do almost any digital function. An effort is carried out to design and
Keywords: Verilog HDL, note, Sparten-3, FPGA
make it to perform like a music box.
Introduction FPGAs are programmable digital logic chips which can be
To design and implement a music box using FPGA. As FPGA
To enhance Verilog HDL programming skills. Since the
programmed to do almost any digital function. FPGAs are "fine-
Verilog HDL programming language is used to program the
grain" devices. That means that they contain a lot (up to 100000)
FPGA to perform like a music box. Programming skill will be
of tiny blocks of logic with flip-flops. FPGAs have special routing
sharpened indirectly through this project.
resources to implement efficiently binary counters and arithmetic
To apply theoretical knowledge to produce an application.
functions (adders, comparators) and RAM.
Theoretical theory may not be the same as the practical;
FPGAs can contain very large digital designs. The designs can run
therefore experiment was carried out to study an application.
much faster than design a board with discrete components, since
Introduction to software: Xilinx
everything runs within the FPGA, on its silicon die. FPGA can be
Xilinx, Inc. is an American technology company, primarily a
downloaded many times with different functionalities. If a mistake
supplier of programmable logic devices. It is known for inventing
is made in design, just fix the "logic function", re-compile and re-
the field programmable gate array (FPGA) and as the first
download it. No PCB, solder or component to change.
semiconductor company with a fabless manufacturing model.
In this project, FPGA is programmed to perform like a music box
Spartan family
in which it contains several sounds and music. A study of the
The Spartan series targets applications with a low-power footprint,
internal function of the FPGA chip is carried out through the
extreme cost sensitivity and high-volume; e.g. displays, set-top
experiments.
boxes, wireless routers and other applications.
In order to make the FPGA chip function like audio tone
The Spartan-6 family is built on a 45-nanometer [nm], 9-metal
generator, a program is written out in Verilog HDL language and
layer, dual-oxide process technology. The Spartan-6 was marketed
downloaded into the FPGA chip. Sounds and music will be
in 2009 as a low-cost solution for automotive, wireless
written in Verilog HDL language as well.
Audio Tone Generator Using Verilog HDL Coding
communications, flat-panel display and video surveillance
To get a down-ramp. We invert the same bits, like that:
applications.
(~tone[21:15]). This gives us 7 bits again, that go down from 127 to 0.To switch between the up-ramp and the down-ramp, we use
Snippet of Verilog code in Xilinx
tone[22]. As soon as the up-ramp hits 127, we switch to the downAmbulance siren : FPGAs can easily implement binary counters. Let's start with a
ramp, until it goes to 0, and then back to the up-ramp.
16-bits counter. Using a 25MHz clock, we "divide the clock"
wire [6:0] ramp = (tone[22] ? tone[21:15] :
using a 16 bits counter that counts from 0 to 65535 (65536
~tone[21:15]);
different values). The highest bit of the counter toggles at a frequency
of
25000000/65536=381Hz.
In
more
details,
"counter[0]" toggles at 12.5MHz, "counter[1]" at 6.125MHz, and so on. Since we use the MSB (bit 15) of the counter to drive the output, a nice 381Hz square signal comes out of the "speaker" output.
// "if tone[22]=1 then ramp=tone[21:15] else ramp=~tone[21:15]" If this ramp business does not make sense to you, we have a more
Let's alternate between two tones. We first use a 24 bits counter "tone" to produce a slow square wave. The MSB bit "tone" toggles
// That means
with
a
frequency
of
about
1.5Hz.
Then we use this bit to switch another counter between two frequencies. Here comes the ambulance!
detailed explanation : Let's say I have a 6 digits decimal counter that goes from 000000 to 199999. The counter is free counting, increments every 1 millisecond (i.e. 1000 times a second) and after it reaches 199999, it returns to 0 and keeps going up again. At that speed, this counter
rolls
over
every
200
seconds.
Obviously, the first digit (I call it digit #0, or digit[0]) will
module music(clk, speaker); input clk; output speaker; parameter clkdivider = 25000000/440/2;
increment the fastest. Too fast for your eyes, so unusable. But the second digit (digit #1) will increment 10 times slower. And so on...
reg [23:0] tone; always @(posedge clk) tone <= tone+1;
Now let's say you look only at digits #4 and #3 (=digit[4:3]). The
reg [14:0] counter; always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;
just not looking at them. You'll see digit[4:3] forming a number
other digits are still going on at their respective speeds; you are
reg speaker; always @(posedge clk) if(counter==0) speaker <= ~speaker; endmodule
between
0
and
99,
and
incrementing
every
second.
Furthermore, I make the following rule: if digit[5] is '0', the I look at digit[4:3], while if digit #5 is '1', I look at the opposite, i.e. (99digit[4:3]). In other words, if(digit[5]=='0') then my rampvalue=digit[4:3] else if(digit[5]=='1') then my rampvalue=(99-digit[4:3]); So "ramp" value goes from 7'b0000000 to 7'b1111111. To get a
Police siren
usable value to produce a sound, we pad it with the 2 bits '01' up
That becomes serious now. We need to generate a ramp that
front, and the 6 bits '000000' in the back.
sounds like a police siren.We start with my "tone" counter. We use only 23 bits to make it twice as fast (MSB toggles at around
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};
3Hz). Then here comes the trick to get an up-ramp. We extract bits 15 through bit 21 of the tone counter, like that: tone[21:15]. This
This
gives us 7 bits, that go from 0 to 127 at some medium speed. After
15'b010000000000000 to 15'b011111111000000, or in hex
it
15'h2000 to 15'h3FC0, or in decimal 8192 to 16320. With a
reaches
127,
it
rolls
back
to
0
and
up
Audio Tone Generator Using Verilog HDL Coding
again.
way,
"clkdivider"
have
a
value
ranging
from
25MHz input clock, that produces "speaker" from 765Hz to
a speaker through the 1KΩ resistor. By changing the IO
1525Hz. That gives us a high pitch siren.
frequency, the FPGA produces different sounds.
Results of simulation:
reg [22:0] tone;
I have perform my simulation work on ISim simulator of Xilinx,
always @(posedge clk) tone <= tone+1; wire [6:0] ramp = (tone[22] ? tone[21:15] :
the result of my output is shown below: 1. Simple beep:
~tone[21:15]); wire [14:0] clkdivider = {2'b01, ramp, 6'b000000}; reg [14:0] counter; always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1; reg speaker; always @(posedge clk) if(counter==0) speaker <= ~speaker;
The hardware
Fig: 3 Simulation output of simple beep
A Xilinx spartan-3 FPGA board, a speaker and a 1KΩ resistor are 2. Frequency of note ‘A’:
used for this project.
Fig: 1 practical setup
Fig: 4 Simulation output of Note ‘A’
A more formal representation looks like this: 3. Ambulance siren.
Fig: 2 Block diagram set up The oscillator provides a fixed frequency to the FPGA. The FPGA divides the fixed frequency to drive an IO. The IO is connected to Fig: 5 Simulation output of Ambulance siren
Audio Tone Generator Using Verilog HDL Coding
4. Police siren.
Fig: 6 Simulation output of Police siren.
Reference 1.
Project idea & design courtesy: http://www.fpga4fun.com/MusicBox.html
2.
Tools used : http://www.xilinx.com/
3.
Basic information courtesy: www.wikipedia.com
4.
Language Courtesy: www.verilog.com
5.
introduction to Verilog sample.pdf
Audio Tone Generator Using Verilog HDL Coding
