Aakansha Barnwal,VII sem.,E.C.E.,I.E.T.,Alwar.
Before, I get to think of things, I would like to add a few heart felt words for the people who are related directly or indirectly to me during the course of my training programme which titles "VLSI using Verilog HDL module" . First of all, I would like to thank respected, Mr. Vinit Mahajan, (trainer) who gave me the opportunity to carry out this training under his guidance. He provided me with all the necessary, which were required for the completion of my training. I also thank my college library staffs for providing me with the books related to the training. I also thank my college management for providing me with such an interesting training programme. A grateful acknowledgement goes to my project mates, who helped me with timely suggestions suggestions during the entire period of references and data collections. A bove bove all with wi thout out God' G od's s grace gr ace n othi oth i ng was poss possi ble bl e.
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Introduction
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History of VLSI
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Emergence of HDLs
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Hierarchical modelling concepts
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Verilog HDL syntax and semantics
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Modules and ports
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Gate level modelling
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Data level modelling
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Verilog operators
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Verilog behavioral modelling
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Tasks and functions
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Switch level modelling
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Art of writing test benches
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Logic synthesis with verilog HDL
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Verilog HDL synthesis
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Modelling memories and FSM
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Applications of Verilog HDL
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Conclusion
Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description language is a language used to describe a digital system. This just means that, by using a HDL one can describe any hardware (digital) at a ny level.
Source code: module d_ff ( d, clk, q, q_bar); input d, clk; ouput q, q_bar; always @ (posedge clk) begin q <= d; q_bar <= !d; end endmodule
One can describe a flip-flop as explained in above figure as well as one can describe a complicated design having 1 million gates. Verilog is one of the HDL languages available in the industry for designing the hardware.
Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first integrated (IC) chips were SSI (small scale integration) chips where the gate count was very small. As technologies became sophisticated, designers were able to place circuits with hundreds of gates on a chip, called MSI (medium scale integration) chips. Then there came LSI (large scale integration) chips. At this point, design processes started getting very complicated, this led to the evolution of CAD (computer aided design) techniques. With the advent of VLSI (very large scale integration) technology, designers could design single chips with more than 100,000 transistors. Because of the complexity of these circuits, it was not possible to verify these circuits on the breadboard. Computer aided techniques became critical for verification and design of VLSI digital circuits. As designers got larger and more complex, logic simulation assumed an important role in the design process. Designers could iron out functional bugs in the architecture before the chip was designed further. This led to the emergence of HDLs which came into existence after circuitry got complex. The emergence of HDLs is described in the next topic which is the same “emergence of HDLs”.
In the digital design field, designers felt the need for a standard language to describe digital circuits similar to the programming languages such as FORTRAN, Pascal and C were being used to describe computer programs that were sequential in nature. Thus Hardware Description Languages (HDLs) came into existence. HDLs allowed the designers to model the concurrency of processes found in hardware elements. Hardware Description Languages such as Verilog HDL and VHDL became popular. Verilog HDL originated in 1983 at Gateway Design Automation. Later, VHDL was developed under contract from DARPA. Both Verilog and VHDL simulators to simulate large digital circuits quickly gained acceptance from designers. Digital circuits could be described at a register transfer level (RTL) by use of an HDL. Thus, the designers had to specify how the data flows between registers and how the design processes the data. The details of gate and their interconnections to implement the circuit were automatically extracted by logic synthesis tools from the RTL description. Thus, logic synthesis pushed the HDLs into the forefront of digital design. Designers no longer had to manually place gates to build digital circuits . HDLs also began to be used for system-level design. HDLs were for simulation of system boards, interconnect buses, FPGAs (Field Programmable Gate Arrays), PALs (Programmable Array Logics).
Before we discuss the details of the Verilog language, we must first understand the basic hierarchical modelling concepts in digital design. There are two basic types of design methodologies: a top-down design methodology and a bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided.
Figure shows Top-down design methodology In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higherlevel blocks until we build the top-level block in the design.
Figure shows bottom-up design methodology Typically, a combination of top-down and bottom-up flows is used. Design architects define the specification of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. They build higherlevel cells by using these leaf cells.
To illustrate these hierarchical modelling concepts, let us consider the design of a negative edge 4-bit ripple counter.
Figure shows 4-bit ripple carry counter. Thus, the ripple carry counter is built in a hierarchical fashion by using building blocks. The diagram for the design hierarchy is shown below.
Figure shows design hierarchy for ripple counter.
In the top-down methodology, we first have to specify the functionality of the ripple carry counter, which is the top-level block. Then we implement the counter with T_FFs which we build from D_FFs and an additional inverter gate. Thus, we break bigger building blocks into smaller ones until we decide that we cannot break up the blocks any further. A bottom-up methodology flows in the opposite direction. We combine small building blocks and build bigger building blocks; e.g., we could build D_FF from and and or gates, or we could build a
custom D_FF from transistors. Thus, the bottom-up flow meets the top-down flow at the level of the D_FF.
Verilog provides the concept of module. A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality that is used at many places in design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designers to modify module internals without affecting the rest of the design. Syntax:-
module (); …. …. …. endmodule.
Verilog is both a behavioural and a structural language. Verilog provides four levels of abstraction. These levels of abstraction can be defined as follows: 1. 2. 3. 4.
Behavioural or algorithmic level, Dataflow level, Gate level, Switch level. An additional level is also there which is used very frequently in digital design. This level is Register-transfer level. o
o
o
BEHAVIOURAL LEVEL:This is the highest level of abstraction provided by Verilog HDL. Designing at this level is very similar to C programming. DATAFLOW LEVEL:At this level the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design. GATE LEVEL:-
o
o
The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gate-level logic diagram. SWITCH LEVEL:This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switch-level implementation details. REGISTER TRANSFER LEVEL:-
This is an additional level which is frequently used in Verilog. Designs using the register-transfer level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times. Modern definition of a RTL code is “ Any code that is synthesizable is called RTL code”.
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SPECIFICATION:-
This is the stage at which we define what are the important parameters of the system/design that you are planning to design. o
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HIGH-LEVEL DESIGN:This is the stage at which various blocks are defined in the design and how they communicate. Lets assume that we have to design a microprocessor, High level design means splitting the design into blocks based on their function, In our case various blocks are registers, ALU, Instruction Decode, Memory Interface,etc.
Micro Design/Low level design:-
Low level design or Micro design is the phase in which, designer describes how each block is implemented. It contains details of state machines, counters, Mux, decoders, Internal registers.
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SIMULATION:-
Simulation is a process of verifying the functional characteristics of models at any level of abstraction. to achieve simulation we need to write a testbench, which generates clk, reset and required test vectors. A sample testbench for a counter is as shown below.
Figure shows sample testbench of a counter. There is another kind of simulation known as timing simulation, which is done after synthesis or after P&R (Place and Route). Here we include the gate delays and wire delays and see if DUT (Device Under Test) works at rated clock speed. This is also called as SDF simulation or gate simulation.
Figure shows 4 bit up counter waveform. SYNTHESIS:Synthesis is the process of constructing a gate level netlist from a register-transfer level model of a circuit described in Verilog HDL.
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Figure shows the synthesis process. Synthesis tool after mapping the RTL to gates, also do the minimal amount of timing analysis to see if the mapped design meeting the timing requirements.
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PLACE AND ROUTE:-
Figure shows sample microprocessor placement.
Figure shows the place and route for J-K Flip-Flop.
NUMBERS IN VERILOG:Constant numbers can be specified in decimal, hexadecimal, octal, or binary format. Negative numbers are represented in 2‟s complement form. When used in a number, the question mark (?) character is the Verilog alternative for the z character. The underscore (_) is legal anywhere in the number except as the first character, where it is ignored. o INTEGER NUMBERS:-
Verilog HDL allows integer numbers to be specified as 1. 2. 3. 4.
Sized or Unsized numbers (unsized size is 32 bits), In a radix pf binary, octal, decimal, or hexadecimal, Radix is a case and hex digits (a,b,c,d,e,f) are insensitive, Spaces are allowed between the size, radix and value.
Syntax : ‟ o
REAL NUMBERS:-
1. 2. 3. 4.
Verilog supports real constants and variables. Verilog converts real numbers to integers to integers by rounding, Real numbers cannot contain „Z‟ and „X‟, Real numbers may b specified in either decimal or scientific notation, . E
5. Real numbers are rounded off to the nearest integer.
HIERARCHICAL IDENTIFIERS:Hierarchical path names are based on the top module identifier followed by module instant identifiers , separated by periods.
PORTS:o o o
Ports allow communication between a module and its environment, All but the top-level modules in a hierarchy have ports, Ports can be associated by order or by name.
You declare ports to be input, output or inout. The port declaration syntax is : Input [range_val:range_var]list _of_identifiers; Output [range_val:range_var]list _of_identifiers; Inout [range_val:range_var]list _of_identifiers;
DATATYPES:-
Verilog language has two primary data types Nets – represents structural connections between components. o Registers – represent variables used to store data. GATE PRIMITIVES:o
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Figure showing the gate primitives.
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TRANSMISSION GATE PRIMITIVES:-
Figure showing transmission gate primitives. o
SWITCH PRIMITIVES:-
Figure showing switch primitives.
DESIGNING USING PRIMITIVES:
AND GATE from NAND GATE
Verilog code:-
module and_from_nand(X,Y,F); input X,Y; output F; wire W; nand U1(X,Y,W); nand U2(W,W,F); endmodule.
Similarly many programs can be done by using Verilog. Many designs can be made using Verilog HDL language.
ARITHMETIC OPERATORS:-
+,-,*,/,% (the modulus operator)
RELATIONAL OPERATORS:<,>,<=(less than equal to),>=(greater than equal to) EQUALITY OPERATORS:===,!==,==,!= LOGICAL OPERATORS:!(logic negation),&&(logical and),||(logical or) BITWISE OPERATORS:~,&,|,^,^~,~^ REDUCTION OPERATORS:&,~&,|,~|,^,^~or ~^ SHIFT OPERATORS:<<,>> CONCATENATION OPERATORS:{ and } CONDITIONAL OPERATORS:Cond_expr? True_expr : false_expr.
OPERATORS
SYMBOLS
Unary, +, -, !, ~, *, /, Multiply,Divide,Modulus % Add,Subtract,Shift
+, -, <<, >>
Relation, Equality
Reduction
<, >, <=, >=, ==, !=, ===, !=== &, !&, ^, ^~, |, ~|
Logic
&&, ||
Condition
?:
PROCEDURAL BLOCKS:There are two types of procedural blocks
Initial: executes once in the starting at time zero, and
Always: executes over and over again.
If the procedural block contains more then one statement, those statements must be enclosed within
Sequential begin-end block
Parallel fork-join block
LOOPING STATEMENTS:Verilog programming language.
has
four
looping
Forever : forever loop executes continually syntax: forever
Repeat: Executes for a fixed number of time. Syntax: repeat ()
While:
statements
like
any
other
Executes as long as an expression evaluates true. Syntax: while ()
For: It is same as used in other programming languages. Syntax: for (;,)
It can be concluded from above that Verilog HDL is a language which is user-friendly and economic. Verilog provides designers to put their own designs and can easily simulate and synthesize the designs and then can implement it . Verilog HDL is a hardware description language which provided the RTL description of the designs for the digital designs. There are less chances of faults in the design which are designed using Verilog. So it helped in reducing faults also. Overall, Verilog HDL is a very useful language used for har dware designing.
