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Design of Parallel IN - Seri Serial al OUT OUT Shift Shift Register Register using Behavior Behavior Modeling Modeling Style (Veril og CODE). ~ Veril Verilog og Programming By Naresh Singh Dobal Dobal
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Design of Parallel IN - Ser ial ial OUT Shift OUT Shift Register using Behavior Modeling Style (Verilog (Verilog CODE). 23:36
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//----------------------------------------------------------------------------// // Title
: parallel_in_ser ial_out
// Design
: vhdl_upload2
// Author
: Naresh Singh Dobal
// Company
:
[email protected]
// Verilog HDL Program Program s & Exercise with Naresh Singh Dobal. // //----------------------------------------------------------------------------// // File
: Parallel IN - Serial OUT Shift Register.v
module parallel_in_serial_out ( din ,clk ,reset ,load ,dout ); output dout ; reg dout ; input [3:0] din ; wire [3:0] din ;
Demultiplexer Design using Gates (Verilog CODE).
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input clk ; wire clk ;
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Design of Parallel IN - Serial OUT Shift Register using Behavior Modeling Style (Veril og CODE). ~ Verilog Programming By Naresh Singh Dobal
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Design of Parallel IN Serial OUT Shift Register ...
temp <= 1; else if (load)
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temp <= din; else begin
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dout <= temp[3]; temp <= {temp[2:0],1'b0}; end
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end endmodule
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2 comments :
Manasa Hegde said... plzz give the testbench code for this... 22 October 2013 at 00:37
ANIL KUMAR said... plzz write the same code to run for 8 times 18 April 2014 at 01:50
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