8/9/20 8/9/2015 15 Design of Serial Serial In - Seri al Out Shift Shift Register using D Fli p Flop (Structural Modeli Modeling ng Style) Style) ( Verilog CODE). ~ Verilog Programming By Naresh Singh Singh Do…
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Design of Serial In - Serial Seria l Out Shift Shift Register using D Flip Flop (Structural Modeling Mo deling Style) Style) (Verilog CODE). 06:14
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Design of Serial IN - Serial OUT Shift Register using using D Flip Flop (Structural Modeling Style)..
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Verilog CODE -
▼ 2013 ( 108 ) ► November ( 8 )
//----------------------------------------------------------------------------// // Title
: siso
// Design
: upload_design1
// Author
: Naresh Singh Dobal
// Company
: nsd
// //----------------------------------------------------------------------------// // File
: Design of Serial In - Serial Out Shift Register using d_flip flop.v
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output dout ;
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input din ;
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module siso ( din ,clk ,reset ,dout );
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wire [2:0]s; d_flip_flop u0 (.din(din),
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// -------------- D flip flop design - -----------------------
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//----------------------------------------------------------------------------// // Title
: d_flip_flop
// Design
: upload_design1
// Author
: Naresh Singh Dobal
// Company
: nsd
// //----------------------------------------------------------------------------// // File
: d_flip_flop.v
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module d_flip_flop ( din ,clk ,reset ,dout ); output dout ; reg dout; input din ; input clk ; input reset ; always @ (posedge clk) begin if (reset) dout <= 1; else dout <= din; end endmodule
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2 comments :
cg thanes said... how to write the test bench for the shift register......please help me....
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