CA3162
®
A/D Converters for 3-Digit Display
April 2002
Features
Description
Dual Slope Slope A/D Conver Conversion sion
The The CA31 CA3162 62E E and and CA31 CA3162A 62AE E are I2L monoli monolithi thicc A/D converters that provide a 3 digit multiplexed BCD output. They are used with the CA3161E BCD-to-Seven-Segment Decoder/Driver and a minimum of external parts to implement a complete 3-digit display. The CA3162AE is identical to the CA3162E except for an extended operating temperature range.
• Multiplexed Multiplexed BCD Display • Ultra Stable Internal Band Gap Voltage Voltage Reference • Capable Capable of Reading 99mV Below Below Ground with Single Single Supply • Differential Differential Input
The CA3161E is described in the Display Drivers section of this data book.
• Internal Internal Timing Timing - No External Clock Clock Required Required • Choi Choice ce of Low Low Spee Speed d (4Hz) (4Hz) or High High Spee Speed d (96Hz (96Hz)) Conversion Rate
Ordering Information
• “Hold” Inhibits Inhibits Conversion Conversion but Maintains Maintains Delay • Overrange Overrange Indication Indication
PART NUMBER
- “EEE” “EEE” for Reading Reading Great Greater er than than +999m +999mV V, “-” for Reading Rea ding More Negati Negative ve than -99mV When When Use Used d With CA3161E
TEMP. RANGE (oC)
CA3162E
0 to 70
PACKAGE
16 Ld PDIP
PKG. NO.
E16.3
Pinout CA3162 (PDIP)
TOP VIEW
1
16 23
20
2
15 22
NSD
3
14 V+
MSD
4
13 GAIN ADJ
LSD
5
12
HOLD/ BYPASS
6
11 HIGH INPUT
GND
7
10 LOW INPUT
ZERO ADJ
8
9
BCD OUTPUTS
DIGIT SELECT OUTPUTS
21
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
BCD OUTPUTS
INTEGRATING CAP
ZERO ADJ
FN1080.3
CA3162 Functional Block Diagram
V+
V+ BCD OUTPUTS
ZERO ADJ
INTEGRATING CAP 8
9
12
21
20
22
23
V+
1
2
15
16
14
3 CONTROL LOGIC COUNTERS AND MULTIPLEX
DIGIT DRIVE
4
DIGIT SELECT OUTPUTS †
5
HIGH INPUT 11
V/I
LOW INPUT 10
CONVERTER
THRESHOLD DET.
REFERENCE CURRENT GENERATOR
BAND GAP REFERENCE
13
† MSD = MOST SIGNIFICANT DIGIT NSD = NEXT SIGNIFICANT DIGIT LSD = LEAST SIGNIFICANT DIGIT
GAIN ADJ
2
÷2048
÷96
OSC
HOLD/ BYPASS GATES
7
6
GND
4
= MSD
5
= LSD
3
= NSD
CONVERSION CONTROL
CA3162 Absolute Maximum Ratings
Thermal Information
DC Supply Voltage (Between Pins 7 and 14). . . . . . . . . . . . . . . +7V Input Voltage (Pin 10 or 11 to Ground). . . . . . . . . . . . . . . . . . . ±15V
θJA ( oC/W) Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150 oC Maximum Storage Temperature Range . . . . . . . . . . -65 oC to 150 oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 oC
Operating Conditions Temperature Range CA3162E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 75 oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details..
Electrical Specifications
TA = 25 oC, V+ = 5V, Zero Pot Centered, Gain Pot = 2.4k Ω , Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
Operating Supply Voltage Range, V+ Supply Current, I+
100k Ω to V+ on Pins 3, 4, 5
Input Impedance, Z I
MIN
TYP
MAX
UNITS
4.5
5
5.5
V
-
-
17
mA
-
100
-
MΩ
-
-80
-
nA
Input Bias Current, I IB
Pins 10 and 11
Unadjusted Zero Offset
V 11-V10 = 0V, Read Decoded Output
-12
-
+12
mV
Unadjusted Gain
V 11-V10 = 900mV, Read Decoded Output
846
-
954
mV
Linearity
Notes 1 and 2
-1
-
+1
Count
Slow Mode
Pin 6 = Open or GND
-
4
-
Hz
Fast Mode
Pin 6 = 5V
-
96
-
Hz
0.8
1.2
1.6
V
Conversion Rate
Conversion Control Voltage (Hold Mode) at Pin 6 Common Mode Input Voltage Range, V ICR
Notes 3, 4
-0.2
-
+0.2
V
BCD Sink Current at Pins 1, 2, 15, 16
V BCD ≥ 0.5V, at Logic Zero State
0.4
1.6
-
mA
Digit Select Sink Current at Pins 3, 4, 5
V DIGIT Select = 4V at Logic Zero State
1.6
2.5
-
mA
Zero Temperature Coefficient
V I = 0V, Zero Pot Centered
-
10
-
µV/ oV
Gain Temperature Coefficient
V I = 900mV, Gain Pot = 2.4kΩ
-
0.005
-
%/ o C
NOTES: 1. Apply 0V across V11 to V 10 . Adjust zero potentiometer to give 000mV reading. Apply 900mV to input and adjust gain potentiometer to give 900mV reading. 2. Linearity is measured as a difference from a straight line drawn through zero and positive full scale. Limits do not include ±0.5 count bit digitizing error. 3. For applications where low input pin 10is not operatedat pin 7 potential,a returnpathof not morethan100k Ω resistance must be provided for input bias currents. 4. The common mode input voltage above ground cannot exceed +0.2V if the full input signal range of 999mV is required at pin 11. That is, pin 11 may not operate higher than 1.2V positive with respect to ground or 0.2V negative with respect to ground. If the maximum input signal is less than 999mV, the common mode input voltage may be raised accordingly.
3
CA3162 reference constant current source of opposite polarity is connected. The number of clock counts that elapse before the charge is restored to its original value is a direct measure of the signal induced current. The restoration is sensed by the comparator, which in turn latches the counter. The count is then multiplexed to the BCD outputs.
Timing Diagram 200mV
12 5 (LSD) R E B M U4 (MSD) N N I P
500mV
The timing for the CA3162E is supplied by a 786Hz ring oscillator, and the input at pin 6 determines the sampling rate. A 5V input provides a high speed sampling rate (96Hz), and grounding or floating pin 6 provides a low speed (4Hz) sampling rate. When pin 6 is fixed at +1.2V (by placing a 12K resistor between pin 6 and the +5V supply) a “hold” feature is available. While the CA3162E is in the hold mode, sampling continues at 4Hz but the display data are latched to the last reading prior to the application of the 1.2V. Removal of the 1.2V restores continuous display changes. Note, however, that the sampling rate remains at 4Hz.
500mV
3 (NSD)
500mV
2ms/DIV.
FIGURE 1. HIGH SPEED MODE
Detailed Description
Figure 1 shows the timing of sampling and digit select pulses for the high speed mode. Note that the basic A/D conversion process requires approximately 5ms in both modes.
The Functional Block Diagram of the CA3162E shows the V/I converter and reference current generator, which is the heart of the system. The V/I converter converts the input voltage applied between pins 10 and 11 to a current that charges the integrating capacitor on pin 12 for a predetermined time interval. At the end of the charging interval, the V/I converter is disconnected from the integrating capacitor, and a band gap NOTE 2
NOTE 1
HOLD: V6 = 1.2V
9
+5V
0.1 µF
0.27µF
NORMAL 8 LOW SPEED MODE: V6 = GROUND OR OPEN
12
14
MSD
16
6
e
4
INPUTS LOW 10 13
7
e
c
b g
e
c d
c d
13 CA3161E
BCD OUTPUTS 11
a f
b g
d
DIGIT DRIVERS
CA3162E
a f
b g
3
GAIN ADJ
NSD
f
POWER 2N2907, 2N3906 OR EQUIV.
COMMON ANODE LED DISPLAYS LSD
a 5
HIGH SPEED MODE: V6 = 5V
HIGH
The “EEE” or “---” displays indicate that the range of the system has been exceeded in the positive or negative direction, respectively. Negative voltages to -99mV are displayed with the minus sign in the MSD. The BCD code is 1010 for a negative overrange (---) and 1011 for a positive overrange (EEE).
12 11
16
6
10
15
2
9
1
1
15
2
7
14 8
R1 150Ω
3 CA3162E PINS 3, 4, 5
10 kΩ
NOTES: 1. The capacitor used here must be a low dielectric absorption type such as a polyester or polystyrene type. 2. This capacitor should be placed as close as possibleto the power and ground Pins of the CA3161E.
R2 150Ω
CA3162E PINS 1, 2, 15, 16
1kΩ
75Ω
DIGIT DRIVER
BCD SEGMENT DRIVERS
FIGURE 2. BASIC DIGITAL READOUT SYSTEM USING THE CA3162E AND THE CA3161E
4
R3 150Ω
CA3162 capacitors and pull-up resistors connected to the MSD, NSD and LSD outputs are there to shorten the digit drive signal thereby providing proper timing for the CD4056B latches.
CA3162E Liquid Crystal Display (LCD) Application
Figure 3 shows the CA3162E in a typical LCD application. LCDs may be used in favor of LED displays in applications requiring lower power dissipation, such as battery-operated equipment, or when visibility in high-ambient-light conditions is desired.
Inverters G1 and G2 are used as an astable multivibrator to provide the AC drive to the LCD backplane. Inverters G3, G4 and G5 are the digit-select inverters and require pull-up resistors to interface the open-collector outputs of the Multiplexing of LCD digits is not practical, since LCDs must CA3162E to CMOS logic. The BCD outputs of the CA3162E be driven by an AC signal and the average voltage across may be connected directly to the corresponding CD4056B each segment is zero. Three CD4056B liquid-crystal inputs (using pull-up resistors). In this arrangement, the decoder/drivers are therefore used. Each CD4056B contains CD4056B decodes the negative sign (-) as an “L” and the an input latch so that the BCD data for each digit may be positive overload indicator (E) as an “H”. latched into the decoder using the inverted digit-select outputs of the CA3162E as strobes. The circuit as shown in Figure 3 using G7, G8 and G9 will decode the negative sign (-) as a negative sign (-), and the The capacitors on the outputs of inverters G3 and G4 filter positive overload indicator (E) as “H”. out the decode spikes on the MSD and NSD signals. The
+5V 0.047µF
16
1
G3 0.047µF
6 4
+5V
2
TO MSD OF LCD
CD4056B
3 5 7
6x 10kΩ
8
0.27µF ZERO 8 14
50kΩ
12 4 3
9 CA3162E “HOLD”
5 16 15 1
VIN+
11
2
VIN-
10 13
7
+5V
0.047 µF
MSD NSD LSD
16
1
G4
0.047µF
0.047 µF
23 22
6 4 2
21
TO NSD OF LCD
CD4056B
3
20
5 7
8
4x 100kΩ +5V
GAIN 10kΩ
G5 16
1 +5V
6 4 G9
G7
2
TO LSD OF LCD
CD4056B
3
G1 - G6: CD4049UB HEX INVERTER G7, G8, G9: CD4023B TRIPLE 3 INPUT NAND GATE
5 7
8 TO LCD BACKPLANE
G8
15kΩ
100kΩ
FIGURE 3. TYPICAL LCD APPLICATION
5
0.63µF
CA3162 The additional logic shown within the dotted area of Figure 4 restores the negative sign (-), allowing the display of Figure 4 shows the CA3162E connected to a CD4511B negative numbers as low as -99mV. Negative overrange is decode/driver to operate a common-cathode LED display. indicated by a negative sign (-) in the MSD position. The rest Unlike the CA3161E, the CD4511B remains blank for all of the display is blanked. During a positive overrange, only BCD codes greater than nine. After 999mV the display segment b of the MSD is displayed. One inverter from the blanks rather than displaying EEE, as with the CA3161E. CD4049B is used to operate the decimal points. By connectWhen displaying negative voltage, the first digit remains ing the inverter input to either the MSD or NSD line either blank, instead of (-), and during a negative or positive over- DP1 or DP2 will be displayed. range the display blanks. CA3162E Common-Cathode, LED Display Application
V+ DP1
100kΩ
22kΩ 1/
DP2
1/ CD4049UB 6
3
CD4049UB CD4012B
1/ 3
CD4049UB
1/ CD4049UB 6
V+ 1 B 2 C 100kΩ
100kΩ
V+
V+ 16 CD4511B
3 LT
g 14
4 BL
a 13
5 LE/STROBE b 12
100kΩ
100kΩ
6 D
c 11
7 A
d 10
8 GND
1.8k Ω
f 15
e 9
HP5082-7433 OR EQUI VALENT
1.2k Ω 1.8k Ω 1.2k Ω 1.8k Ω 12
11 10
1.8k Ω
f
9
a
8
g
7
b
c3
c
dP
1.8kΩ
V+ DP1 1 B 100 kΩ
100 kΩ
100 kΩ
CA3162E
2 A
c1
D 16
1
C 15
3 NSD
V+ 14
4 MSD
GAIN 13
5 LSD
INT 12 HIGH 11
7 GND
LOW 10
8 ZERO
3
DP2
c2 4
5
6
10kΩ GAIN
6 BUFFERS (1 CD4050B)
ZERO 9 V+
2
d
V+ 0.27µF
6 HOLD
e
INPUT
50kΩ
FIGURE 4. TYPICAL COMMON-CATHODE LED APPLICATION
6
CA3162 Die Characteristics DIE DIMENSIONS:
PASSIVATION:
101 mils x 124 mils x 20 mils ± 1 mil
Type: 3% PSG Thickness: 13kÅ ± 2.5kÅ
METALLIZATION:
Type: Al Thickness: 17.5kÅ ± 2.5kÅ
Metallization Mask Layout CA3162 T U P N I W O L
J J D D A A O O R R E E Z Z
D N G
HIGH INPUT HOLD/BYPASS
INTEGRATING CAP
LSD
MSD GAIN ADJ
+ V
2
2
1
3
2
2
0
2
D S N
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