So Do Nguyen Ly Dell

5

D

C

B

A

4

3

2

1

Enrico Caruso 14 Muxless Schematics Document Ivy Bridge & Sandy Bridge Intel PCH 2012-01-03 REV : X02 DY : PSL: UMA: OPS: Surge: GIGA: LPC : POP :

D

C

None Installed 10mW internal schematic UMA ONLY installed Optimus solution installed. For GO Rural config stuff. For GIGA LAN config stuff. Reserve for LPC debug card Reserve for solve "POP" sound iuuse

B

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Title

Cover Page

5

4

3

VRAM

gDDR3 gDDR3 900MHz 900MHz

1GB (128Mx16x4) 88,89,90,91

gDDR3 900MHz

Intel CPU Ivy Bridge & Sandy Bridge Bridge

DDRIII DDR III 1333 1333/16 /1600 00 Chann Channel el A

48 APL5916 INPUTS OUTPUTS

42~44 VT1318+1323 VT1318+1 323 INPUTS OUTPUTS

DCBATOUT

DCBATOUT

0D85V_S0

45 TPS51219 INPUTS OUTPUTS DCBATOUT

DCBATOUT

46 TPS51216R INPUTS OUTPUTS

10/100 /1000 LOM

DCBATOUT

Realtek RTL8111F (Giga LAN)

RJ45 CONN 59

C

802.11a/b/g

Mini-Card WLAN+BT3.064

PCIE x 1

PCIE PCI E

CRT CR T

Intel

50

49

HDMI HDM I

HDMI

Realtek RTS5138

USB 2.0 x 1

USB 2.0

USB2.0

Audio board board Internal Internal Analog Analog MIC

M/B USB x1 (Left) 61

USB 2.0 x 1

High High Definit Definition ion Audio Audio 6 SATA ports

LPC Bus

8 PCIE ports

AZALIA AZA LIA

I/O board board USB x2 (Right)

82

ACPI ACPI 4.0a 4.0a

24MHz 24M Hz

+DC_IN_S5 +PBATT

RT8068A

INPUTS

47

OUTPUTS 1D8V_S0

Switches INPUTS

KBC

DCBATOUT

SYSTEM DC/DC DC/DC

3D3V_S5

USB 2.0 x 2

33MHz

LPC I/F

Azalia CODEC

VGA_CORE

40 BQ24707 INPUTS OUTPUTS

CAMERA 49

12 USB 2.0/1.1 ports

32

C

VCC_GFXCORE VCC_GFXCORE

VGA DCBATOUT

HM75 HM75

B

B

93

OUTPUTS

17,18,19,20,21,22,23,24,25

58

Cirrus CS4213D

1D5V_S3

NUVOTO NUV OTON N NPCE885P

29

27

D/A

Thermal NCT7718W

HP1

PS/2

82

A T A S

MIC IN

s A p T b A G S 3

Touch PAD

HDD 56

ODD 56

Flash ROM 8MB 60

Int. KB

G991P

1D5V_S0

5V_S5

5V_S0

3D3V_S5

3D3V_S0

28

Thermal

Fan Control

69

58

PS/2

I P S

2CH SPEAKER A

USB 2.0 x 1

480Mbps

SD/MMC/MS/ MS Pro 74

DCBATOUT

TI CHARGER

51

CardReader

44 VT1318+1323 VT1318+1323 INPUTS OUTPUTS

92 ADP3211 INPUTS OUTPUTS

100MHz 2.5Gbps

PCH Panther Point BGA989

LVDS LVD S

LCD

1D5V_S3 0D75V_S0 DDR_VREF_S3

GFX DC/DC

31

Xtal=25MHz

DMIx4

5V_AUX_S5 3D3V_AUX_S5 5V_S5 3D3V_S5 15V_S5

SYSTEM DC/DC

Realtek RTL8105E-VD RTL8105E-VD (10M/100M) (10M/100M)

FDIx4x2

D

41 TPS51125 INPUTS OUTPUTS

83.84,85,86,87

PCIE x 1

1D05V_VTT

SYSTEM DC/DC

DDRIII Slot 1 14 1333/1600

4,5,6,7,8,9,10

VCC_CORE

SYSTEM DC/DC

DDRIII Slot 0 15 1333/1600

DDRIII DDR III 1333 1333/16 /1600 00 Chann Channel el B

(Discrete only)

CRT

CPU DC/DC

PCIe x 8

N13M-GS Xtal=27MHz

SYSTEM DC/DC

Vostro :91.4UA01.001 PCB P/N :48.4TY02.0SC Revision:11282-SC

4

D

1

Block Diagram code: (Discrete) Project Inspiron:91.4TY01.001

##OnMainBoard

Hynix:72.52G63.A0U (HT31P$AA (HT31P$AA)) Samsung:72.42164.D0U (JP0F2$AA (JP0F2$AA))

2

G709

28

28

PCB LAYER L1:Top L2:GND L3:Signal

69

L4:Signal L5:VCC L6:Bottom

A


Title

Block Diagram

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

XDP

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

(Blanking) C

C

B

B

A

A


Reserved

5

4

3

2

1

SSID = SDIO XD_D7

20 CLK_PCH_48M

1

TP3204 TPAD14-OP-GP

XD_D6/MS_BS

XD_D6/MS_BS 74

XD_D5/SD_D2/MS_D5

XD_D5/SD_D2/MS_D5 74

XD_D4/SD_D3/MS_D1

D

XD_D3/SD_D4/MS_D4 C3209 1

DY 2

XD_D4/SD_D3/MS_D1 74 D

1

TP3205 TPAD14-OP-GP

RREF

SC100P50V2JN-3GP R3201 1 2 6K2R2F-GP 3D3V_S0 USB_PN5_R USB_PP5_R

43mA P P G G 5 - 1 4 X 1 3 X 0 K 0 2 3 2 K 3 V 3 2 V C 3 C 0 2 DY 1 D 2 6 U U 1 7 D D C 4 S C S

C

3D3V_CARD_S0

V18

250mA P 8 G

0 1 2 X

3 K C 2 V 3 2 D 6 U 1 C S

U3201

4 3 2 1 0 9 2 2 2 2 2 1

4 3 2 1 N I 7 1 1 1 1 _ D _ P P P P K D L X S S S S SP10 RREF C DM GPIO0 DP SP9 3V3_IN SP8 CARD_3V3 SP7 # V18 SP6 D C _ 1 2 3 4 5 D P P P P P 25 GND X S S S S S RTS5138-GR-GP 7 8 9 0 1 2 1 1 1 1 2 3 4 5 6

XD_D2/SD_CMD CR_GPIO0 1 XD_D1/SD_D5/MS_D0 XD_D0/SD_CLK/MS_D2 XD_WP/SD_D6/MS_D61 XD_WE#/SD_CD#

18 17 16 15 14 13

XD_D2/SD_CMD 74 TP3201 TPAD14-OP-GP XD_D1/SD_D5/MS_D0 74 TP3206 TPAD14-OP-GP XD_WE#/SD_CD# 74

71.05138.003 C

Close to chip 3D3V_CARD_S0

Vendor recommand

P G 5 - 1 6 X 0 2 K 3 2 V C 0 2 1 U 1 D C S

P G 7 X 1 0 K 2 3 3 V C 3 D 2 6 U 7 D 4 C S

XD_ALE/SD_D7/MS_D3

XD_ALE/SD_D7/MS_D3 74

XD_CLE/SD_D0/MS_D7

XD_CLE/SD_D0/MS_D7 74

XD_CE#/SD_D1

XD_CE#/SD_D1 74

XD_RE#/MS_INS#

XD_RE#/MS_INS# 74

XD_RDY/SD_WP/MS_CLK_R XD_CD#

1

R3208

1 TP3203 TPAD14-OP-GP

X02 2

XD_RDY/SD_WP/MS_CLK

74

0R0402-PAD

XD_D0/SD_CLK/MS_D2

R3209

2

1

33R2J-2-GP

XD_D0/SD_CLK/MS_D2_R

74

For EMI Close U3201 B

USB_PN5_R CLK_PCH_48M

1 R3210 P G - DY 2 J 2 R 0 1 2 C L K _ P C H _ 4 8 M _ R P 1 G 4 C3210 N J 2 2 V 0 5 P 0 1 C S

R3206 1

USB_PP5_R R3207 1

2 0R0603-PAD

USB_PN5 18

2 0R0603-PAD

USB_PP5 18

B

X02 1229 changed R3206,R3207 to short pad, removed TR3201 CMC footprint

DY

A

A


Card Reader-RTS5138

A

B

C

D

E

4

4

3

3

(Blanking)

2

1

2

1


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

SSID = PWR.Support

Batt Connecter

D

D

BATT1

10 1 K

BT+

1

1

EC3904 SCD1U50V3KX-GP 2

2

AFTP3901 EC3903 SC2200P50V2KX-2GP

PD3902 DY SMF18AT1G-GP

1BAT_ALERT

A SRN33J-7-GP 27,40 27,40 27

4 3 2 1

BAT_SCL BAT_SDA BAT_IN#

PBAT_SMBCLK1 PBAT_SMBDAT1 PBAT_PRES1#

5 6 7 8

2 3 4 5 6 7 8 9 11

1

PN3901

ALP-CON9-4-GP-U AFTP3906

EC3901 EC3902

20.81507.009

1 P 1 P G 4

G 4

DY N DY N J J

2 2 2 2 V 0 5 P 0 1 C S

C

2nd = 20.81642.009

V 0 5 P 0 1 C S

AFTP3902 AFTP3903 AFTP3904 AFTP3905

C

3rd = 20.81684.009

1 1 1 1

PBAT_PRES1# PBAT_SMBDAT1 PBAT_SMBCLK1 BT+

For actual location, need to be swap all pin B

B

Placement: Close to Batt Connector

B A T _ I N #

X00

B A T _ S C L

B A T _ S D A

3

3

3

D3902 DA3X101F0L-GP

1

A

2

D3903 DA3X101F0L-GP

1

2

D3901 DA3X101F0L-GP

1

2

83.3X101.011 83.3X101.011 83.3X101.011 2nd = 83.00099.K11 2nd = 83.00099.K11 2nd = 83.00099.K11 3rd = 83.00099.M11 3rd = 83.00099.M11 3rd = 83.00099.M11

A

3D3V_AUX_KBC

Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size

Document Number

BATT CONN

Rev

5

4

3

2

1

SSID = PWR.Plane.Regulator_1p8v

APL5930 for 1D8V_S0 D

D

+1.8V_RUN Design current = 1.086A

3D3V_S5 5V_S5 1D8V_PWR C

1 PC4701 SC1U10V3KX-3GP 2 PU4701 19,45,46,93 RUNPWROK

19,27,36,37 PM_SLP_S3#

PR4701 1

2

6 7 8 9

1D8V_RUN_EN

0R2J-2-GP

1 PR4702 47KR2J-2-GP

DY 2

P 1 G 1 2 X 0 7 K 4 2 2 V C P 0 5 P 0 0 7 4 C S

VCNTL POK EN VIN#9

VIN#5 VOUT#4 VOUT#3 FB GND

5 4 3 2 1

APL5930KAI-TRG-GP

DY

74.05930.03D 2ND = 74.G9731.03D

PC4703 S C 1 1 0 U 6 D 2 3 V 3 M X G P

1D8V_S0 C

PG4709 1 2 GAP-CLOSE-PWR-3-GP

1D8V_PWR

PG4707 1 2 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP PG4708 1 2

B F _ N U R _ V 8 . 1 _ 2 1 9 5

PR4703 1 1 6 K 5 R 2 F -2 - 2 G P

PC4704 1 S C 6 8 P 2 5 0 V 2 J N -1 G P

1

GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP

1

PC4705 S C 2 2 U 6 D 3 V 5 M X -2 G P

DY 2

1 2

PC4706 S C 2 2 U 6 D 3 V 5 M X -2 G P

PR4704 13K3R2F-L1-GP B

A

2

B

Vout=0.8V*(R1+R2)/R2

A


APL5930 1D8V_S0

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

C

D

C

(Blanking)

B

A

B

A


LVDS_Switch

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

SSID = User.Interface

D

D

C

C

(Blanking)

B

A

B

A


ITP/Fan Connector

5

4

3

2

1

SSID = ESATA

D

D

C

C

(Blanking)

B

A

B

A


ESATA

5

4

3

2

1

SSID = AUDIO

D

Spea5er Connector

D

5 29 AUD_SPK_L-

1

29 AUD_SPK_L+ 29 AUD_SPK_R29 AUD_SPK_R+

2 3 4

SPK1 ACES-CON4-4-GP

6 1

1 1 1 EC5801 EC5802 EC5803 EC5804 P P P P G G G G 1 1 1 1 2 - 2 - 2 - 2 X X X X K K K K 2 2 2 2 V V V V 0 0 0 0 5 5 5 5 P P P P K K K K 1 1 1 1 C C C C S S S S

C

X02 1229 change EC5801 EC5802 EC5803 EC5804 to 1000P cap for EMI request X02 1230 stuff EC5801 EC5802 EC5803 EC5804 for EMI request

AFTP5805

1

20.F0765.004 2nd = 20.F1426.004 C

AFTP5801 AFTP5802 AFTP5803 AFTP5804

1 1 1 1

AUD_SPK_LAUD_SPK_L+ AUD_SPK_RAUD_SPK_R+

B

A

B

A


SPEAKER CONN

5

4

3

SSID = Flash.ROM

2

1

PCH

SPI SPI 3las7 R8)9,): ;or PCH BC

3D3V_S5 3D3V_S5

follow check list 1.5 D

C6001 SC10U6D3V5KX-1GP

8 7 6 5

1

1

DY

2

2

D

C6002 SCD1U10V2KX-5GP

RN6001 SRN3K3J-1-GP

1 2 3 4

SPI_HOLD_0# 3D3V_S5 U6001

21,27 SPI_CS0#_R 21 SPI_SO_R 0R2J-2-GP 1

1 2 R6003

DY

33R2J-2-GP1

27 EC_SPI_DI_C

SPI_SO SPI_WP#

2 R6001 33R2J-2-GP

R6002 6002 2 R

2 1

EC6002 SC4D7P50V2CN-1GP

DY

DY

2

R6009 4K7R2J-2-GP

1

1 2 3 4

S# DQ1 W#/VPP/DQ2 VSS

VCC HOLD#/DQ3 C DQ0

8 7 6 5

SPI_CLK_R 21,27 SPI_SI_R 21,27

1

N25Q064A13ESE40F-GP

72.25Q64.D01 2nd = 72.25Q64.C01

1

DY DY 2

2

EC6001 SC10P50V2JN-4GP

EC6003 SC4D7P50V2CN-1GP

3rd = 72.25Q64.B01 4th = 72.25640.D01

C

C

SSID = RBATT 3D3V_AUX_S5

RTC_AUX_S5

Q6001

2

+RTC_VCC

3

RTC1

2

1

C6003 SC1U6D3V2KX-GP 1

CH715FPT-GP

RTC_PWR

3 1

R6006 2 1KR2J-1-GP

4

83.R0304.B81

ACES-CON2-31-GP

2nd = 83.R2004.C81

20.F1606.002

Width=20mils

R 60 07 1

2nd = 20.F1871.002

2 10 0R 2J -2 -G P

DY

RTC_PWR B

X00

VccRTC is now connected to VccDSW3_3 through the Schottky diode instead of the 3.3V Sus well.

1 G

R6008 10MR2J-L-GP

2

S

1 2

D

B

RTC_DET# 22

Q6002 2N7002BK-GP

84.07002.I31 2nd = 84.2N702.W31 3rd = 84.2N702.J31

A

A


Flash/RTC

5

4

3

2

1

SSID = USB

USB20_VCCA 5V_S5

USB20_VCCA

U6102

1 2 3 4

D

1 C6102 SC1U10V3ZY-6GP

GND IN#2 IN#3 EN/EN#

OUT#8 OUT#7 OUT#6 OCB

USB2

100 mil

8 7 6 5

5 1

SY6288DCAC-GP

2

74.02000.B71

USB_OC#0_1

18

2nd = 74.06288.A79

1 C6103

1 C6104

1 TC6101

P G 2 3 X K 2 V 6 1 U 1 D

P G 2 5 X K 2 V 0 1 U 1 D

P G X M 6 V 3 D 6 U 0 0 1 C S

C S

2

C S

LOW ACTIVE TYPE!!

27 USB_PWR_EN#

1

DY TC6103

D

USB_PN1_R USB_PP1_R

P 2 G 5 1 M D V 3 D 6 U 0 2 2 T S

AFTP6102

2 3 4 6

1

SKT-USB6-16-GP

22.10321.S01 2nd = 22.10341.831

AFTP6101 AFTP6103 AFTP6104

1 1 1

USB20_VCCA USB_PN1_R USB_PP1_R

USB20_VCCB 5V_S5

U6103

1 2 3 4

C

1 C6107 SC1U10V3ZY-6GP

GND IN#2 IN#3 EN/EN#

OUT#8 OUT#7 OUT#6 OCB

8 7 6 5

100 mil C

1 C6105 P G

2 3 -

SY6288DCAC-GP

2

74.02000.B71

2nd = 74.06288.A79

USB_OC#8_9

18

X K 2 V 6 1 U 1 D C S

1 C6106 P G

2 5 -

1

DY

TC6102 P

2 G 5

1 M D V 3 D 6 U 0 2 2 T S

X K 2 V 0 1 U 1 D C S

LOW ACTIVE TYPE!! 27 USB_PWR_EN#

X02 1230 removed R6102,R6103 co-lay position B

B

USB_PP1_R USB_PN1_R

4

TR6101

1

3

USB_PP1 18

2

USB_PN1 18

FILTER-310-GP-U

69.10084.101 2nd = 69.10166.001

U6105 USB_PN1_R

1 2 3

ESD I/O1 GND DY ESD I/O2

ESD I/O4 VP ESD I/O3

6 5 4

USB_PP1_R 5V_S5

IP4220CZ6-GP

A

A


USB Power SW

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1


D

D

(Blanking) C

C

B

B

A

A


Bluetooth

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


RESERVED

5

4

SSID = Wireless

3

2

1

Mini Card Connector(802.11a/b/g) 3D3V_S0

D

D

WLAN1 3D3V_S0

53

1D5V_S0

1

C6502 P G 5 2 X K 2 V 0 1 U 1 D C S

1

C6503 P G 2 1 X K 5 V 3 D 6 U 0 1 C S

C6504 P G 5 2 X K 2 V 0 1 U 1 D C S

1

DY 2

1

Decap

1

1

C6505 P G 1 X K 5 V 3 D 6 U 0 1 C S

DY 2

AFTP6505

C6506 P G 5 X K 2 V 0 1 U 1 D C S

20 CLK_PCIE_WLAN# 20 CLK_PCIE_WLAN

27 27 20 20

WLAN_ACT P 1 C6508 G X K 2 V 2 DY 5 2 U 1 D C S

20 20 BT_ACT

C

WLAN_ACT BT_ACT

20 CLK_PCIE_WLAN_REQ#

5V_S5 P 1 C6501 G X K 2 V 2 DY 5 2 U 1 D C S

1

1R6511 2 0R2J-2-GP

5V_S5

PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4

3D3V_S0

1R6510

27 BLUETOOTH_EN

E51_RXD E51_TXD

1R6503

DY

2 0R2J-2-GP +5V_MINI_DEBUG 2 0R2J-2-GP

DY

1R6509 1R6508

20R2J-2-GP 20R2J-2-GP

DY

E51_RX E51_TX

1D5V_S0

NP1 2

3 5 7 9 11 13 15

4 6 8 10 12 14 16

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 NP2

WIFI_RF_EN 27 PLT_RST# 5,18,27,31,71,83 3D3V_S0 1D5V_S0 PCH_SMBCLK 14,15,20 PCH_SMBDATA 14,15,20 USB_PN11_R USB_PP11_R

CARD_WLAN_OUT# 27 CARD_WPAN_OUT# 27 1D5V_S0

C

3D3V_S0

54 TYCO-CONN52A-2-GP

20.F1743.052 2nd = 62.10043.A51 3rd = 62.10043.H01

18

USB_PP11

18

USB_PN11

R6506 1

R6505

1

2

2 0R0402-PAD

USB_PP11_R

0R0402-PAD

USB_PN11_R

X02 1229 changed R6505,R6506 to short pad, removed TR6501 CMC footprint

B

A

B

A


MINICARD (WLAN)/ITP CONN

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A


Title

Hall Sensor

5

4

3

2

1

D

D

PCH 0ebug Connector

Layout Note:

Place near trace separated point

X00 21,27 LPC_AD[3..0]

3D3V_S0

LPC_AD[3..0]

DB1 RN7101 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

8 7 6 5

1 2 3 4

LPC

SRN0J-7-GP 21,27 LPC_FRAME#

X00

R 710 3

1

2

LPC

LPC_LAD0_R LPC_LAD1_R LPC_LAD2_R LPC_LAD3_R LPC_FRAME#_R 5,18,27,31,65,83 0R 2J-2-G P

PLT_RST#

18 CLK_PCI_LPC

1 2 3 4 5 6 7 8 9 10 11 12

LPC

MLX-CON10-7-GP

20.D0183.110 C

C

B

B

A

A


Title

Debu g connector

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Title

Reserved

5

4

3

2

1

SSID = SDIO 3D3V_CARD_S0 CARD1

11 4

D

3D3V_CARD_S0

DY

20 3

32 XD_WE#/SD_CD# 32 XD_D4/SD_D3/MS_D1

P G P P P P 4 G 5 X G G G 0 5 0 K 1 1 5 - 1 2 5 - 1 3 5 - 1 4 - 1 4 3 7 X 7 V 0 X 0 X 0 X 4 K 4 K 4 K K C C 3 7 2 7 2 7 2 2 D V C V C V C V 6 0 2 0 2 0 2 0 2 2 U 1 1 1 1 2 U U U U D 1 1 1 1 2 D D D D C C C C C S S S S S

DY

DY


SD_VDD/MMC_VDD MS_VCC SD_CD SD_CD/DAT3/MMC_RSV

14 6

SD_CLK/MMC_CLK SD_CMD/MMC_CMD

32 XD_CLE/SD_D0/MS_D7 32 XD_CE#/SD_D1 32 XD_D5/SD_D2/MS_D5

18 19 1

SD_DAT0/MMC_DAT SD_DAT1 SD_DAT2

32 XD_RDY/SD_WP/MS_CLK

22

SD_WP/SW

32 XD_D0/SD_CLK/MS_D2_R 32 XD_D2/SD_CMD

NP1 NP2

NP1 NP2

MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3

12 13 10 7

MS_INS MS_BS MS_SCLK

8 15 5

GND GND

23 24

SD_GND

21

MS_VSS MS_VSS

2 16

SD_VSS/MMC_VSS1 SD_VSS/MMC_VSS2

9 17

XD_D1/SD_D5/MS_D0 32 XD_D1/SD_D5/MS_D0 XD_D4/SD_D3/MS_D1 XD_D4/SD_ D3/MS_D1 32 XD_D0/SD_CLK/MS_D2_ XD_D0/SD_ CLK/MS_D2_R R 32 XD_ALE/SD_D7/MS_D3 XD_ALE/SD_ D7/MS_D3 32


XD_RE#/MS_INS# XD_RE#/MS_ INS# 32 XD_D6/MS_BS XD_D6/MS_ BS 32 XD_RDY/SD_WP/MS_CLK XD_RDY/SD_WP/MS_CLK

D

32

CARD-PUSH-22P-GP

20.I0110.021 2nd = 20.I0133.001

X00 C

C

XD_ALE/SD_D7/MS_D3 XD_D1/SD_D5/MS_D0 XD_CLE/SD_D0/MS_D7 XD_CE#/SD_D1 XD_D5/SD_D2/MS_D5 XD_D4/SD_D3/MS_D1 XD_D2/SD_CMD XD_D0/SD_CLK/MS_D2_R XD_WE#/SD_CD# XD_RDY/SD_WP/MS_CLK

1

2

7 DY C N

7 DY C N

P 0 P 1 0 4 G 1 4 G

2

For EMI

P G 3 N

P G 4

7 V DY C

7 V DY C

N 1 0 1 0 4 B 4 C 2 2

P G 5

P G 6

P G 7

P G 8

P G 9

P G 0

7 V DY C

7 V DY C

7 V DY C

7 V DY C

7 V DY C

7 V DY C

N N N N N N 1 0 1 0 1 0 1 0 1 0 1 1 4 C 4 C 4 C 4 C 4 C 4 C 2 2 2 2 2 2

0 0 0 0 0 0 0 0 E E E 5 E 5 E 5 E 5 E 5 E 5 E 5 E 5 C C 2 2 P 2 P 2 P 2 P 2 P 2 P 2 P 2 P 7 V 2 V 2 8 8 8 8 8 8 8 0 0 D D D D D D D D 5 5 4 6 6 6 6 6 6 6 P P C C C C C C C C 8 8 S S S S S S S S D D 6 6 C C S S

B

A

B

A


Title

SD/XD/MS/MMC Card CONN

5

4

3

2

1

SSID = ExpressCard

D

D

C

C

B

B

A

A


Title

Ex press press Card

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1


D

D

C

C

(Blanking)

B

A

B

A


Free Fall Sensor

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


Reserved

5

4

3

2

1

SSID = USB X02 1230 removed R8203,R8204 co-lay position

IOBD1 is for USB board

D

D

USB20_VCCB

IOBD1

TR8202 USB_PP9_R

1

USB_PN9_R

4

17 2

USB_PP9 18

3

USB_PN9 18

1

FILTER-310-GP-U USB_PN9_R USB_PP9_R

69.10084.101 2nd = 69.10166.001

USB_PN8_R USB_PP8_R

X02 1230 removed R8201,R8202 co-lay position

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18

C

C

PTWO-CON16-1-GP

20.K0429.016

2nd = 20.K0460.016 TR8201 USB_PP8_R

1

2

USB_PP8 18

USB_PN8_R

4

3

USB_PN8 18

FILTER-310-GP-U

69.10084.101 2nd = 69.10166.001

B

SSID = Audio

B

IOBD2 is for Audio board IOBD2

17 29 INT_MIC_L_R 29 AUD_HP1_JACK_L2 29 AUD_HP1_JACK_R2 29 29

MIC_IN_L MIC_IN_R

29 EXT_MIC_JD# 29 AUD_HP1_JD# 27 LID_CLOSE# 3D3V_S5

A

MIC_IN_L 1 SC10P50V2JN-4GP MIC_IN_R 1 SC10P50V2JN-4GP AUD_HP1_JACK_L2 1 SC10P50V2JN-4GP AUD_HP1_JACK_R2 1 SC10P50V2JN-4GP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18

2

DY EC8201

PTWO-CON16-1-GP

DY EC8202

20.K0429.016

DY EC8203

2nd = 20.K0460.016

2 2 2

DY EC8204

A


IO Board Connector

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


GPU-VRAM5 ,6 (3/4)

5

4

3

2

1

D

D

C

C

(Blanking)

B

A

B

A


GPU-VRAM7 ,8 (4/4)

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A


LVDS_Switch

5

4

3

2

1

D

D

C

C

(Blanking)

B

B

A

A


CRT_Switch

5

4

3

2

1

SSID = SDIO

D

D

C

C

(Blanking)

B

A

B

A


TOUCH PANEL

5

4

3

2

1

DV14 MLK Chief River POWER UP SEQUENCE DIAGRAM 5V_S5

-6 AC

DCBATOUT

AD+

Adapter in

-3.1

Page38

-3.1

-3.1 VDDP

PWR_5V3D3V_ENC

D

3V_5V_EN

-3.2

VIN VOUT

S5_ENABLE

PM_SLP_S4#

-3.3

SWITCH

ENC

LL1

Page40

LL2

VREG5

TPS51125 DC/DC (3V/5V)

-6.1 DCBATOUT

VREG3

VIN

PGOOD

5V_S5

PUMP

3D3V_S5 5V_AUX_S5

15V_S5

3V_5V_POK

DDR_VREF_S3

TPS51216RUK VTT

3D3V_AUX_S5

D

EN REF

PWR_CHG_ACOK

1D5V_S3

3

0D75V_S0

-5 3

PGD

PM_SLP_S4#

-2

Page46

RUNPWROK

5

Page41

DC Battery

5 V_ S5

4

BQ24707

BT+

-3

SWITCH Page37

BJT

3D3V_AUX_KBC

VDD

-3.1

Page40 ACOK

GPIO34

GPIO70

PGD

KBC_PWRBTN#

GPIO6

Power Button

PM_SLP_S4#

GPIO43

GPIO44

PM_SLP_S3#

SLP_S4#

GPIO20

GPIO01

PM_PWRBTN#

11 RSMRST# PWRBTN#

S0_PWR_GOOD

Y

VDDPWRGOOD

SM_DRAMPWROK

A

H_CPUPWRGD_R

UNCOREPWRGOOD

12

Sandy Bridge & Ivy Bridge CPU

13 APWROK PWROK

SYS_PWROK

B

H_CPUPWRGD

PROCPWRGD

Pather Point PCH

AND GATE

0D75V_EN PM_DRAM_PWRGD

DRAMPWRGD

2 Page27

PLTRST#

PLT_RST#

BUF_CPU_RST#

RSTIN#

S V I D

V5IN

VIN VOUT

B

1D05_VTT S0_PWR_GOOD

TPS51219RTER EN

Page45

PGOOD

VIN VOUT

5a

1.05VTT_PWRGD

PGOOD

D85V_PWRGD

-8

6 D85V_PWRGD

7 IMVP_VR_ON

RTC battery

VIN

OUTPUT SVID

VR

3D3V_AUX_S5

+RTC_VCC

DCBATOUT

A

SYS_PWROK

RTC_AUX_S5

EN

8

Y B

-7

6

SVID

A

-5

0D85_S0

APL5916 Page48

IMVP_PWRGD

10

AND GATE

5a

5V_S5 DCBATOUT

VDDP

8

D CBA TO UT

5

1.05VTT_PWRGD

SVID

SYS_PWROK

10

RUNPWROK

C

5

SLP_S3#

-2.1 PM_RSMRST#

GPIO77

B

RUNPWROK

Page47

SWITCH

KBC NPCE885P

1D8V_S0

EN

Page37

1

5 V_S 5

VOUT

RT8068

1D5V_S0

C

-1

PM_SLP_S3#

Page37

AC_IN#

VIN

4

3D3V_S0 SWITCH

S5_ENABLE

-4

3 D3V _S 5

5V_S0

PM_SLP_S3#

Charger

Page39

OUTPUT

VCC_CORE VCC_GFXCORE

A

VT1318+1323 9 VR_ON

Page42 & 43 & 44 PGOOD

IMVP_PWRGD


Power Up Sequence: -8 ~ 13

Title

Power Se quence Diagram

5

4

Adapter

3

2

1

DCBATOUT

TPS51219DSCR

TPS51216RUKR

ADP3211

AO4407A

D

D

Charger 1D05V_VTT

BQ24707

Battery

1D5V_S3

+PBATT

AO4468

APL5916

1D05V_VGA_S0

0D75V_S0

TPCA8062

0D85V_S0

1D5V_S0

VGA_CORE

AO4468

1D5V_VGA_S0

C

C

TPS51125ARGER

15V_S5

3D3V_AUX_S5

5V_AUX_S5

5V_S5

G547F2P81

AO4468

3D3V_S5

VT1318+1323

VT1323

AO4468 RT8068

5V_USB2_S0

5V_S0

3D3V_S0 VCC_CORE

1D8V_S0

VCC_GFXCORE

AO3403

3D3V_LAN_S5

B

B

ODD_PWR_5V

G5285T11

LCDVDD

RTS5138

3D3V_CARD_S0

DMP2130L

3D3V_VGA_S0

Power Shape

A

Regulator

LDO

A

Wistron Corporation

Switch

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

Power Block Dia gram

A

B

C

PCH SMBus Block Diagra m 3D3V_S5

D

E

KBC SMBus Block Diagram

3D3V_S0

5V_S0

3D3V_S0 SRN2K2J-1-GP

SRN2K2J-1-GP

DIMM 1 1

SMBCLK

SMB_CLK

PCH_SMBCLK

SMBDATA

SMB_DATA

PCH_SMBDATA

3D3V_S5

SRN10KJ-5-GP

TouchPad Conn.

SCL SDA

SMBus Address:A0

PSDAT1

TPDATA

TPDATA

TPDATA

PSCLK1

TPCLK

TPCLK

TPCLK

1

2N7002SPT

3D3V_AUX_KBC 3D3V_S5

SRN2K2J-8-GP

DIMM 2 PCH_SMBCLK

SCL

PCH_SMBDATA SML1CLK

SDA

SML1_CLK

SML1DATA

SML1_DATA

SRN4K7J-8-GP

To KBC

SRN2K2J-1-GP

SMBus Address:A4

Battery Conn.

SRN100J-3-GP SML0CLK

SML0_CLK

SML0DATA

SML0_DATA

3D3V_S5

3D3V_S0

Minicard WLAN

PCH_SMBCLK

CLK_SMB

BATA_SDA_1

DAT_SMB

SMBus address:16

BQ24707

KBC NPCE885P

SML1CLK

SML1_CLK

THM_SML1_CLK

SML1DATA

SML1_DATA

THM_SML1_DATA

SCL

SCL SDA

SMBus address:12

Thermal 2

SDL

SMBus Address:98

2N7002SPT

PCH

BATA_SCL_1

BAT_SDA

SMB_DATA

SRN4K7J-8-GP

2

BAT_SCL

GPIO22/SDA1

SMB_CLK

PCH_SMBDATA

3D3V_S0

SRN2K2J-8-GP

GPIO17/SCL1

3D3V_VGA_S0

3D3V_VGA_S0

VGA

SML1_CLK

GPIO_VGA_04_CLK

GPIO_4_SMBCLK

SML1_DATA

GPIO_VGA_03_DATA

GPIO_3_SMBDATA

GPIO73/SCL2

SML1_CLK

SCL

GPIO74/SDA2

SML1_DATA

SDA

PCH

SMBus Address:9E

3D3V_S0

5V_HDMI_S0


SRN1K5J-GP

3

3

SDVO_CTRLCLK SDVO_CTRLDATA

PCH_HDMI_CLK

DDC_CLK_HDMI

PCH_HDMI_DATA

HDMI CONN

DDC_DATA_HDMI

2N7002DW-1-GP

3D3V_S0

SRN2K2J-1-GP

L_DDC_CLK

LVDS_DDC_CLK_R

LVDS_DDC_CLK

CLK

L_DDC_DATA

LVDS_DDC_DATA_R

LVDS_DDC_DATA

DATA

3D3V_S0

LCD CONN 5V_S0


SRN10KJ-6-GP

4

CRT_DDC_CLK CRT_DDC_DATA

CRT_DDC_CLK

CRT_DDCCLK_CON

CRT_DDC_DATA

CRT_DDCDATA_CON

4

CRT CONN


2N7002DW-1-GP Title

A

B

C

D

Thermal Block Diagram

E

Audio Block Diagram

1

1

3D3V_S5

3D3V_S0

PAGE28

PCH

D+

NCT7718_DXP

D-

NCT7718_DXN

MMBT3904-3-GP

SPKR_PORT_D_L-

SPEAKER

SC2200P50V2KX-2GP SPKR_PORT_D_R+

Pather Point SML1_DATA

THM_SML1_DATA

2N7002 SML1_CLK

UMA Thermal NCT7718

Place near CPU PWM CORE

Codec 92HD79B1

THM_SML1_CLK

MMBT3904-3-GP GPIO58

SDA

HP

HP1_PORT_B_L

T8

HP1_PORT_B_R GPIO75 PAGE20

SML1_DATA

3D3V_VGA_S0

SCL T_CRIT#

THERM_SYS_SHDN#

2N7002

PURE_HW_SHUTDOWN#

D

S

SML1_CLK

EN

OUT

3V/5V

3D3V_S0

G

Put under CPU(T8 HW shutdown)

2

PAGE27

GPIO74

KBC NPCE885P

2

PAGE85

GPIO73 GPIO_VGA_04_CLK

GPIO_4

GPIO_VGA_03_DATA

GPIO_3

2N7002

GPIO56

3

HP0_PORT_A_R

IN

VREFOUT_A_OR_F

1 H C A T _ N A F

C A D _ 1 N A F

MIC

HP0_PORT_A_L

Thames S3_Pro

GPIO4 GPIO94

VGA

Digital MIC

DMIC_CLK/GPIO1 DMIC0/GPIO2

TACH

FAN

VGA_THRM

3

TDR PAGE28 P2800_VGA_DXP

VIN

5V

N I V

VSET

VOUT

FAN CONTROL

P2793

DXP

VGA Thermal

THRMDA SC2200P50V2KX-2GP P2800_VGA_DXN

DXN

SC2200P50V2KX-2GP

VGA

THRMDC PORTC_L

Place near GPU(DISCRETE only).

P2800

Analog MIC

PORTC_R VREFOUT_C

MMBT3904-3-GP

PAGE28 PH OTZ

4

4


Thermal/Audio Block Dia

So Do Nguyen Ly Dell

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