FPGA Implementation Of Binary Search Y. Nesika1, T.Asha, P. !asmine " # $th year St%&ents, St%&ents,
'epartment of ()(, *ar (phraem )olle+e of (n+ineerin+
(mail i& nesika-iflin+mail.com nesika-ifli n+mail.com 1 , ashasteffy/+mail.com ashasteffy/+mail.com , pas%mathi-asmine+mail.com pas%mathi-asmine+mail.com". 0n&er the +%i&ance of *rs. ). !asmine, *. Tech, Ph .'2,
Abstract- This paper reports an FPGA implementation of binary search. Searching is an important function in memory architectures. Normally, binary search using software implementation is a slow process. Eisting har!ware implementation, "A# uses parallel search which results in high spee! but there are !isa!$antages li%e high power consumption an! area. The propose! har!ware architecture achie$es the balance between power consumption an! har!ware compleity.
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This is 3ase& on &esi+nin+ the 3inary search in har&4are 3ase& on FPGA. This is aime& to re&% re&%ce ce the the po4e po4err cons cons%m %mpt ptio ion n an& an& har& har&4a 4are re comple5ity an& to increase the spee&. In the e5istin+ )A* )ontent A&&ressa3le *emory2 3ase& 3inary search, the po4er cons%mption is 6ery hi+h. In or&er to re&%ce the po4er cons%mption 4e are +oin+ to &esi+n the 3inary search in har&4are. Binary search is a key task in net4ork application s%ch as net4ork sec%ri sec%rity ty.. Si+na Si+nat%r t%ree matchi matchin+ n+ in I'S I'S Intr Intr%si %sion on &etection system2 re7%ires searchin+, in 4hich 3inary search search can 3e appli applie&. e&. In this this paper paper,, 4e presen presentt FPGA 3ase& architect%re of 3inary search tar+etin+ &ecrea &ecrease se po4er po4er cons%m cons%mpti ption on 4ith 4ith less less har&4a har&4are re components. The e5istin+ har&4are implementation )A* )A* re7% re7%ir ires es hi+h hi+h po4e po4err 4ith 4ith hi+h hi+h har& har&4a 4are re comple5ity.
E+&ST&NG SSTE# 0nlike stan&ar& comp%ter memory ran&om access memory or 8A*2 in 4hich the %ser s%pplies a memory a&&ress an& the 8A* ret%rns the &ata 4or& store& at that a&&ress, a )A* is &esi+ne& s%ch that the %ser s%pplies a &ata 4or& an& the )A* searches its entire memory to see if that &ata 4or& is store& any4here in it. If the &ata 4or& is fo%n&, the )A* ret%rns a list of one or more stora+e a&&resses 4here the 4or& 4as fo%n& an& in some architect%re, it also ret%rns ret%rns the &ata 4or&, 4or&, or other associate& pieces of &ata2. Th%s, a )A* is the har&4are em3o&iment of 4hat in soft4are terms 4o%l& 3e calle& an associati6e array.. Beca%se a )A* is &esi+ne& to search its entire array memory in a sin+le operation, it is m%ch faster than 8A* in 6irt%ally all search applications. There are cost &isa&6anta+es to )A* ho4e6er. 0nlike a 8A* chip, 4hich has simple stora+e cells, each in&i6i&%al
memory 3it in a f%lly parallel )A* m%st ha6e its o4n associate comparison circ%it to &etect a match 3et4een the store& 3it an& the inp%t 3it. A&&itionally, A&&itionally, match o%tp%ts from each cell in the &ata 4or& 4or& m%st m%st 3e com3in com3ine& e& to yiel& yiel& a comple complete te &ata &ata 4or& match si+nal. The a&&itional circ%itry increases the physical si9e of the )A* chip 4hich increases man%fact%rin+ cost. The e5tra circ%itry also increases po4er &issipation since e6ery comparison circ%it is acti6e on e6ery clock cycle. So po4er cons%mption is hi+h in )A*.
P'(P(SE) SSTE#
A 3inary search locates an item in a sorte& array 3y repeate&ly &i6i&in+ the search inter6al in half. The initial inter6al incl%&es the entire array. If the 6al%e of the search key is less than the item in the mi&&le of the inter6al, then the ne5t inter6al 4ill 3e the lo4er half of the c%rrent inter6al. If the 6al%e of the search key is +reater than the mi&&le item, then the ne5t inter6al 4ill 3e the %pper half. The search process repeats %ntil the item is fo%n& or the search inte inter6 r6al al is empty empty.. Bina Binary ry Sear Search ch is an O (l (log og n) al+orithm, al+orithm, 4hich is more efficient efficient than a linear linear search for lar+e arrays. It is an efficient al+orithm for fin&in+ a sorte& array. S%ppose a search is 3e+%n 3y comparin+ the key 4ith the 6al%e in the mi&&le location of a sorte& array. If the mi&&le 6al%e is too lar+e then all 6al%es in the last half are too lar+e: hence, the search can 3e limite& to the first half. Similarly if the mi&&le 6al%e is too small, then the search can 3e limite& to the
secon& half. This approach can 3e contin%e&, each time narro4in+ the search to an inter6al half the si9e of pre6io%s inter6al.
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#AGN&T*)E "(#PA'AT(' It is a com3inational circ%it. =ere 4e are %sin+ a $ 3it ma+nit%&e comparator. The t4o inp%ts to the ma+nit%&e comparator are the startin+ an& the en&in+ a&&ress of the memory 4here 4e are +oin+ to search the tar+ete& &ata. The startin+ a&&ress an& the en&in+ a&&ress of the memory are +i6en to the comparator. It compares the t4o a&&resses an& +i6es an o%tp%t. If the o%tp%t is less than or e7%al, it is +i6en to the a&&er or else it &eci&es that the tar+et to 3e searche& is not in the memory.
A))E' =ere 4e are %sin+ a $ 3it a&&er. The a&&er no4 a&&s 3oth the startin+ an& en&in+ a&&resses an& pro&%ces an o%tp%t. This o%tp%t is +i6en to the &i6i&er.
)&&)E' =ere the o%tp%t of the a&&er is &i6i&e& 3y ?@.The o%tp%t of the &i6i&er is the ?mi&&le 6al%e@ that is the ?mi&&le a&&ress@ of the memory 4here the searchin+ is &one. 0sin+ this mi&&le 6al%e 4e can &i6i&e the memory into t4o hal6es.
#E#(' A 1 3it 8A* memory is %se&. The t4o inp%ts to the memory are a&&ress an& the clock inp%t an& the o%tp%t is the &ata o%tp%t. The mi&&le 6al%e is consi&ere& as the ?a&&ress@ of o%r tar+ete& &ata an& it is +i6en as the inp%t to the memory. The secon& inp%t to the memory is the );O)> inp%t 4hich is %se& for synchroni9ation. The o%tp%t of the memory is the &ata 4hich is store& in the mi&&le a&&ress.
#AS/ 'EG&STE' It is nothin+ 3%t a re+ister 4hich is %se& to store the ?tar+ete& &ata@ 4hich 4e are searchin+ in the memory.
#AGN&T*)E "(#PA'AT(' The t4o inp%ts to this ma+nit%&e comparator are the &ata o%tp%t from the memory an& tar+ete& &ata from the mask re+ister. If the t4o inp%ts are ?e7%al@, it in&icates that the tar+et &ata 4as fo%n& in the memory an& it is the re7%ire& o%tp%t. If the tar+ete& &ata is @+reater than@ the &ata o%tp%t from memory ,then it 4ill 3e +i6en to an a&&er an& here a+ain a startin+ a&&ress is calc%late& %sin+ Startin+ a&&ressCmi&&le 6al%eD1E.Then this res%lt is +i6en to the first ma+nit%&e comparator an& if the tar+ete& &ata is ?lesser than@ the &ata o%tp%t, then it is +i6en to the s%3traction an& a+ain an en&in+ a&&ress is calc%late& %sin+ (n&in+ a&&ressCmi&&le 6al%e#1E, then this 4ill +i6en to the first ma+nit%&e comparator. An& this proce&%re 4ill 3e repeate& %ntil o%r tar+ete& &ata is fo%n& in memory.
S(FT0A'E TE"1N&2*ES The soft4are %se& here is ilin5 S( .i. After &esi+n entry an& optional sim%lation, yo% r%n synthesis. The IS(H soft4are incl%&es ilin5 Synthesis Technolo+y ST2, 4hich synthesi9es =';, erilo+, or mi5e& lan+%a+e &esi+ns to create ilin5H#specific net list files kno4n as NG) files. 0nlike o%tp%t from other 6en&ors, 4hich consists of an ('IF file 4ith an associate& N)F file, NG) files contain 3oth lo+ical &esi+n &ata an& constraints. ST places the NG) file in yo%r pro-ect &irectory an& the file is accepte& as inp%t to the Translate NG'B%il&2 step of the Implement 'esi+n process.
1A')0A'E TE"1N&2*ES FPGAs are pro+ramma3le semicon&%ctor &e6ices that are 3ase& aro%n& a matri5 of )onfi+%ra3le ;o+ic Blocks );Bs2 connecte& thro%+h pro+ramma3le interconnects. As oppose& to Application Specific
Inte+rate& )irc%its ASI)s2, 4here the &e6ice is c%stom 3%ilt for the partic%lar &esi+n, FPGAs can 3e pro+ramme& to the &esire& application or f%nctionality re7%irements. Altho%+h One#Time Pro+ramma3le OTP2 FPGAs are a6aila3le, the &ominant type are S8A*#3ase& 4hich can 3e repro+ramme& as the &esi+n e6ol6es. FPGAs allo4 &esi+ners to chan+e their &esi+ns 6ery late in the &esi+n cycleJ e6en after the en& pro&%ct has 3een man%fact%re& an& &eploye& in the fiel&. In a&&ition, ilin5 FPGAs allo4 for fiel& %p+ra&es to 3e complete& remotely, eliminatin+ the costs associate& 4ith re#&esi+nin+ or man%ally %p&atin+ electronic systems.
'ES*3TS AN) )&S"*SS&(N 0sin+ the propose& metho&, the po4er cons%mption of the system can 3e re&%ce&, since only the ro4 in the memory 4here the tar+ete& &ata present 4ill 3e acti6e s4itch is ON2.So the po4er is s%pplie& only to that partic%lar ro4 in memory there3y re&%cin+ the po4er cons%mption of the system. For lo4 # cost applications, 4e can %se the propose& system instea& of %sin+ )A*)ontent A&&ressa3le *emory2,4hich is 6ery e5pensi6e since 3inary search is a sin+le small mo&%le %se& only for searchin+ of &ata in se6eral applications like si+nat%re matchin+ in net4ork sec%rity.
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In the propose& system, 4e are implementin+ the 3inary search in FPGA, 4hich is re#confi+%ra3le. So the &esi+n can 3e chan+e& 3ase& on o%r applications. The FPGA implementation is less e5pensi6e than the e5istin+ )A*, so for lo4# cost applications 4e can %se the propose& s ystem.
A"/N(03E)GE#ENT
'EFE'EN"ES Anar+yros >rikelis, )harles ).
=ann%m et al.. LL$2. System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state. 0.S. Patent ,/",$"$. A6aila3le 3y searchin+ at httpMMpatft.%spto.+o6MnetahtmlMPTOMsearch#3ool.html Pa+iamtis, >. Sheikholeslami, A. LL, *arch2. )ontent#A&&ressa3le *emory )A*2 )irc%its an& Architect%res A T%torial an& S%r6ey. IEEE ! of Solid"State #ircuits, $1"2, K1JKK.
