EE 2174 Lab 9 Counters
1 Objective Now that we have implemented some storage elements in the form of latches and flip-flops, we will start building more complicated systems with those elements. Specifically, we will building and using several counter registers. You will not be performing the entire lab; check the Pre-Lab to see which portions of the lab you are being asked to complete.
2 Equipment Everything in this lab will be done on the lab PCs with Quartus II and the DE2 Development Board.
3 Part I: A Synchronous Counter Consider the circuit in Figure 1. It is a 4-bit synchronous counter which uses four T-type flip-flops. The counter increments its count on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by using the Reset signal. You are to implement a 16-bit counter of this type.
Figure 1: A 4-bit Counter
1. Write a Verilog file that defines a 16-bit counter by using the structure depicted in Figure 1. Your code should include a T flip-flop module that is instantiated sixteen
times to create the counter. Compile the circuit. Answer the questions on the data sheet for this step. 2. Simulate your circuit to verify its correctness. As long as you are satisfied with the behavior, you do not need your TA’s verification of this. If you have any questions or concerns with your design, ask! 3. Augment your Verilog file to use the pushbutton KEY 0 as the Clock input, switches SW 1 and SW 0 as Enable and Reset inputs (respectively), and 7-segment displays HEX3–0 to display the hexadecimal count as your circuit operates. Make the necessary pin assignments needed to implement the circuit on the DE2 board, and compile the circuit. 4. Download your circuit into the FPGA chip and test its functionality by operating the implemented switches. Get your TA’s initials on the data sheet when the module behaves properly. 5. Modify your design to be just a 4-bit version. Use the Quartus II RTL Viewer to see how Quartus II software synthesized your circuit. Answer the question pertaining to this step on the data sheet.
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Part II: A Simpler Counter
One of the benefits of using an HDL is how it relieves the designer from the tedious, elementary details of a system — like specifying the behavior of something well-known (such as a T flip-flop) or instantiating a module sixteen times. (Realistically, if you do need sixteen copies of a module, you would use the generate command.) So let’s simplify your Verilog code so that the counter specification is based on an always block and the Verilog statement Q <= Q + 1;, where Q is a 16-bit signal. There is only one step in this part: 1. Create and compile a 16-bit version of a counter with this simpler specification. Simulate it to be sure that it works. Then answer the questions on the data sheet relevant to this design.
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Part III: An LPM Implementation
Use an LPM from the Library of Parameterized Modules to implement a 16-bit counter. Choose the LPM options to be consistent with the above design, i.e., with an enable and a synchronous clear. Answer the questions below concerning this step.
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Part IV: Using a Counter to Measure Time
Design and implement a circuit that successively flashes digits 0 through 9 on the 7-segment display HEX0. Each digit should be displayed for about one second. Use a counter to determine the one-second intervals. The counter should be incremented by the 50 MHz clock signal provided on the DE2 board. Do not derive any other clock signals in your design — make sure that all flip-flops in your circuit are clocked directly by the 50 MHz clock signal. Get your TA’s initials upon completion of this step.
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Part V: A Scrolling Message
Design and implement a circuit that displays the word HELLO, in ticker tape fashion, on the eight 7-segment displays HEX7–0. Make the letters move from right to left in intervals of about one second. The patterns that should be displayed in successive clock intervals are given in Figure 2.
Figure 2: Scrolling the word “HELLO” in ticker-tape fashion
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Pre-Lab Name: Section: For each of these questions, bring the Verilog files on a flash drive or some other storage you can access from the lab. Attach a printout of the code to this Pre-Lab sheet. 1. (2) Write a “first draft” of the Verilog module required in Part 1. You do not need to simulate it unless you so desire. 2. (3) Write a “first draft” of the Verilog module required in Part 2. You do not need to simulate it unless you so desire. 3. (3) Write a “first draft” of the Verilog module required in Part 4. You do not need to simulate it unless you so desire. 4. (2) Read through the file tutorial library modules verilog.pdf on the course website. This file discusses how to use LPMs in designs. Write a sequence of instructions to remind yourself how to instantiate an LPM for Part 3.
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Data Sheet Name: Section: There may be questions below that are asked pertaining to sections of the lab you are not completing. Ignore these questions. 1. Concerning the design from Part 1, step 1, how many logic elements (LEs) are used to implement your circuit? What is the maximum frequency, Fmax , at which your circuit can be operated? Use the RTL Viewer to see how Quartus synthesized your design and summarize what you observe.
2. With regards to the 4-bit counter you created in Part 1, step 5, what are the differences in comparison with Figure 1?
3. Pertaining to Part 2, step 1, compare the number of LEs needed and the Fmax that is attainable. Use the RTL Viewer to see the structure of this implementation and comment on the differences with the design from Part I.
4. How did the design in Part 3 compare to the other designs in the lab?
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9. Be sure to print out and turn in all Verilog modules developed for this lab.
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