MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
NAME:
Solutions Semester 2, 2016
STUDENT ID:
Answer all questions. Make sure you write your name and student ID number on both the cover page and also above. State your assumptions and show all relevant workings to answer ALL questions. Give indication of correct answer if you provide answers which can be ambiguous. DO NOT use red colour on your exam as it interferes with the marking process.
Question 1. (Total: 40 marks)
Difficulty: Easy Level (a) What is General/Global Interrupt Enabler (GIE) on an MSP430 and provide an example of two calls (in C or assembly) used in CCS to enable and disable GIE respectively? (10 marks) The GIE is a bit in the status register (SR) or register R2 within the register file, which
when set is able to enable maskable interrupt sources can be activated/deactivated via some of the following calls o o o o o o o o o o o o o o o
SR |= BIT3; // Enable interrupts i.e. GIE = 1 SR &= ~BIT3; // Disable interrupts i.e. GIE = 0 __eint(); // Intrinsic function call i.e. GIE = 1 __dint(); // Intrinsic function call i.e. GIE = 0 __enable_interrupt(); // Intrinsic function call i.e. GIE = 1 __disable_interrupt(); // Intrinsic function call i.e. GIE = 0 __bis_SR_register(GIE); // Intrinsic function call i.e. GIE = 1 __bic_SR_register(GIE); // Intrinsic function call i.e. GIE = 0 EINT ; Assembly: Emulated instruction i.e. GIE = 1 DINT ; Assembly: Emulated instruction i.e. GIE = 0 BIS #8,SR ; Assembly: Enable interrupts i.e. GIE = 1 BIC #8,SR ; Assembly: Disable interrupts i.e. GIE = 0 BIS #8,R2 ; Assembly: Enable interrupts i.e. GIE = 1 BIC #8,R2 ; Assembly: Disable interrupts i.e. GIE = 0 Any other equivalent implementation
(b) Draw the flowchart for a main program that uses polling (busy wait) and a flowchart of a periodic polling and provide explanation e xplanation comparing the differences between the two. The space provided is sufficient for your answer but there is additional space provided at the end of the exam paper if required. (30 marks)
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 1 of 6
MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
Solutions Semester 2, 2016
In the busy wait polling method on the left flowchart, the main program polls the I/O devices continuously whereas In periodic polling, a timer interrupt sets up I/O devices polling on a regular basis. Periodic polling is used in applications where I/O hardware cannot generate interrupts directly and to relegate I/O functions to the background process.
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 2 of 6
MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
Solutions Semester 2, 2016
We can also have the following acceptable flowchart diagrams as covered in the tutorials.
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 3 of 6
MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
Solutions Semester 2, 2016
Question 2. (Total: 60 marks)
Difficulty: Intermediate Intermediate Level (a) An empty loop takes 2 s to execute on an MCU consuming 20 clock cycles. Some user code is added into the empty loop whereby the total loop execution time consumes 140 clock cycles. Two XOR lines of code from the added user code are placed at the start and end of the code within the loop to perform an MCU pin toggling for oscilloscope measurement measuring 11.5 s. Estimate the effective-execution-time (excluding the two XOR lines) in s for the added code into the for loop, if an XOR line of code takes x clock cycles to execute? (20 marks)
Determine the time per clock cycle
μs 0.1 . 20 cycles c y c l e 2 μs
Added code takes 140 20 x 120 x cycles including one XOR line of code operation.
Determine a line of XOR code execution
μs 0.1 120 - x cycles cycle x 5 cycles. 11.5 μs
Added code effective-execution-time takes 140 20 2 x 140 20 2 5 110 cycles
μs 110 cycles 0.1 11 μs. cycle (b) What are the contents of register R5 after executing the last line of assembly code shown below? Complete Table 2 provided for the destination contents by making use of Table 1. (25 marks i.e 5 marks per correct entry) mov.w mov.w mov.w bic.b bis.b
#0xC2F0,R4 ; A memory location with write access to memory ; block starting at 0xC200 for MSP-EXP430FR5739 #0x1155,0(R4) #0xFFEE,R5 &0xC2F0,R5 #0x1144,R5
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 4 of 6
MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
Solutions Semester 2, 2016
Use the information below as guide for the assembly code given above. Instruction
Operation
bic src, dst
(src)' & dst
bis src, dst
src | dst
mov src, dst
src
Addressing Mode Syntax
Description
#
Immediate data
&
Absolute address
Rn
Register contents are operand
X(Rn)
(Rn+X) points to the operand
dst
→
dst
→
dst
→
Table 1 Description of Instruction and Addressing Mode Syntax mov.w mov.w mov.w bic.b bis.b
#0xC2F0,R4
; ; #0x1155,0(R4) ; #0xFFEE,R5 ; &0xC2F0,R5 ; #0x1144,R5 ;
A memory location with write access to memory block starting 0xC200 for MSP-EXP430FR5739 Store 0x1155 -> M(0xC2F0) Store 0xFFEE -> R5 (M(0xC2F0))' & R5 -> R5 (.b upper byte is zero) 0x1144 | R5 -> R5 (.b upper byte is zero)
Instruction
Destination
Result in Hexadecimal
mov.w
#0xC2F0,R4
R4
0xC2F0
mov.w
#0x1155,0(R4)
0(R4) Memory
0x1155
mov.w
#0xFFEE,R5
R5
0xFFEE
bic.b
&0xC2F0,R5
R5
0x00AA
bis.b
#0x1144,R5
R5
0x00EE
Table 2 Complete “Result in Hexadecimal” column
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 5 of 6
MICROCOMPUTERS CMPE2003 Department of Electrical and Computer Engineering
Solutions Semester 2, 2016
(c) Before an interrupt occurs in an MSP430, the content of Program Counter (PC) is 0x8000 and Stack Pointer (SP) is 0xC400. Complete Figure 1 below when an interrupt occurs (the Interrupt Service Routine points to 0xFFFA). (15 marks i.e 5 marks per correct entry) PC
Memory
SP
FFFA
8000
C3FE
Figure 1 Fill in the blanks The SP address defaulted to decrement by 2 bytes for byte/word push. When an interrupt is initiated, items are pushed onto the stack i.e. decremented because of last in first out (LIFO) scheme used by MSP430. Figure 1 indicates the return address 0x8000 in Memory (stack) already so SP holds the decremented Memory address 0xC3FE.
Curtin University is a trademark of Curtin University of Technology. Technology. CRICOS Provider Code 00301J (WA), 02637B (NSW)
Page 6 of 6
+ = =
=
