Combinational Logic Circuits
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Combinational Logic Circuits Unlike Sequential Logic Circuits whose outputs are dependant on both their present inputs and their previous output state giving them some form of Memory Memory,, the outputs of Combinationa Combinationall Logic Circuits Circuits are are only determined by the logical function of their current input state, logic "0" or logic "1", at any given instant in time as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. n other words, in a Combinational Logic Circuit, Circuit , the output is dependant at all times on the combination of its inputs and if one of its inputs condition changes state so does the output as combinational circuits have "no memory", "timing" or "feedback loops".
Combinational Logic
Combinational Logic Circuits are Circuits are made up from basic logic NAND, NOR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. !hese logic gates are the building blocks of combinational logic circuits. n n e#ample of a combinational circuit is a decoder, which converts the binary code data present at its input into a number of different output lines, one at a time producing an e$uivalent decimal code at its output. %ombinational logic circuits can be very simple or very complicated and any combinational circuit can be implemented with only NN& and N'R gates as these are classed as "universal" gates. !he three main ways of specifying the function of a combinational logic circuit are( •
1. )oolean lgebra * !his forms the algebraic e#pression showing the operation of the logic circuit for each input variable either !rue or +alse that results in a logic "1" output.
•
•
. !ruth !a !able ble * truth table defines the function of a logic gate by providing a concise list that shows all the output states in tabular form for each possible combination of input variable that the gate could encounter.
•
•
-. ogic &iagram * !his is a graph graphical ical representatio representation n of a logic circuit circuit that shows the wiring and connections of each individual logic gate, represented by a specific graphical symbol, that implements the logic circuit. and all three of these logic circuit representations are shown below.
s combinational logic circuits circuits are made up from individual logic gates gates only, only, they can also be considered considered as "decision making circuits" and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. %ommon combinational circuits made up from individual logic gates that carry out a desired application include Multiplexers Multiplexers,, De-multiplexers De-multiplexers,, Encoers Encoers,, Decoers Decoers,, !ull !ulland and "al# Aers etc. Aers etc.
Classi#ication o# Combinational Logic
'ne of the most common uses of combinational logic is in Multiplexer and De-multiplexer type type circuits. /ere, multiple inputs or outputs are connected to a common signal line and logic gates are used to decode an address to select a single data input or output switch. multiple#er consist of two separate components, a logic decoder and some solid state switches, but before we can discuss multiple#ers, multiple#ers, decoders and demultiple#ers in more detail we first need to understand how these devices use these "solid state switches" in their design.
Soli State S$itc%es tandard !! logic devices made up from Transistors can only pass signal currents in one direction only making them "unidirectional" devices and poor imitations of conventional electromechanical switches or relays. /owever, some %2' switching devices made up from !ET&s act as near perfect "bidirectional" switches making them ideal for use as solid state switches. olid state switches come in a variety of different types and ratings, and there are many different applications for using solid state switches. !hey can basically be subdivided into - different main groups for switching applications and in this combinational logic section we will only look at the Analogue Analogue type type of switch but the principal is the same for all types including digital.
Soli State S$itc% Applications •
3 nalog nalogue ue witches * Use Used d in &at &ata a w witc itchin hing g and %om %ommun munica icatio tions, ns, 4i 4ideo deo and u udio dio ig ignal nal witching, nstrumentation and 5rocess %ontrol %ircuits ...etc.
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•
witching and ignal Routing, 6thernet, N7s, U) 3 &igital witches * /igh peed &ata !ransmission, witching and erial !ransm !ransmissions issions ...etc.
•
•
3 5ower witches * 5ower upplies and 8eneral "tandby 5ower" witching pplications, witching of arger 4oltages and %urrents ...etc.
Analogue 'ilateral S$itc%es nalogue or "nalog" switches are those types that are used to switch data or signal currents when they are in their "'N" state and block them when they are in their "'++" state. !he rapid switching between the "'N" and the "'++" state is usually controlled by a digital signal applied to the control gate of the switch. n ideal analogue switch has 9ero resistance when "'N" :or closed;, and infinite resistance when "'++" :or open; and switches with R'N values of less than 1< are commonly available.
Soli State Analogue S$itc%
)y connecting an Nchannel 2'+6! in parallel with a 5channel 2'+6! allows signals to pass in either direction making it a 'i-irectional switch and as to whether the Nchannel or the 5channel device carries more signal current will depend upon the ratio between the input to the output voltage. !he two 2'+6!s are switched "'N" or "'++" by two internal noninverting and inverting amplifiers.
Contact Types =ust like mechanical switches, analogue switches come in a variety of forms or contact types, depending on the number of "poles" and "throws" they offer. !hus, terms such as "5!" :singlepole single throw; and "5&!" :single pole doublethrow; also apply to solid state analogue switches with "makebeforebreak" and "breakbeforemake" configurations available.
Analogue S$itc% Types
ndividual analogue switches can be grouped together into standard % packages to form devices with multiple switching configurations of 5! and 5&! as well as multi channel multiple#ers. !he most common and simplest analogue switch in a single % package is the >?/%?0@@ which has ? independent bidirectional "'NA'++" witches within a single package but the most widely used variants of the %2' analogue switch are those described as "2ultiway )ilateral witches" otherwise known as the "2ultiple#er" and "&emultiple#er" %Bs and these are discussed in the ne#t tutorial.
Combinational Logic Summary !hen to summarise, Combinational Logic Circuits consist of inputs, two or more basic logic gates and outputs. !he logic gates are combined in such a way that the output state depends entirely on the input states. %ombinational logic circuits have "no memory", "timing" or "feedback loops", there operation is instantaneous. combinational logic circuit performs an operation assigned logically by a )oolean e#pression or truth table. 6#amples of common combinational logic circuits include( half adders, full adders, multiple#ers, demultiple#ers, encoders and decoders all of which we will look at in the ne#t few tutorials.
T%e Multiplexer
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T%e Multiplexer
data selector, more commonly called a Multiplexer, shortened to "2u#" or "25C", are combinational logic switching devices that operate like a very fast acting multiple position rotary switch. !hey connect or control, multiple input lines called "channels" consisting of either , ?, D or 1@ individual inputs, one at a time to an output. !hen the Eob of a "multiple#er" is to allow multiple signals to share a single common output. +or e#ample, a single D channel multiple#er would connect one of its eight inputs to the single data output. 2ultiple#ers are used as one method of reducing the number of logic gates re$uired in a circuit or when a single data line is re$uired to carry two or more different digital signals. &igital Multiplexers are constructed from individual analogue s$itc%es encased in a single % package as opposed to the "mechanical" type selectors such as normal conventional switches and relays. 8enerally, multiple#ers have an even number of data inputs, usually an even power of two, n , a number of "control" inputs that correspond with the number of data inputs and according to the binary condition of these control inputs, the appropriate data input is connected directly to the output. n e#ample of a Multiplexer configuration is shown below.
(-to-) C%annel Multiplexer
ddressing b 0 0 1
a 0 1 0
1
1
nput elected ) % &
!he )oolean e#pression for this ?to1 Multiplexer above with inputs to & and data select lines a, b is given as(
F G ab H ab) H ab% H ab& n this e#ample at any one instant in time only 'N6 of the four analogue switches is closed, connecting only one of the input lines to & to the single output at F. s to which switch is closed depends upon the addressing input code on lines " a" and "b", so for this e#ample to select input ) to the output at F, the binary input address would need to be "a" G logic "1" and " b" G logic "0". !hen we can show the selection of the data through the multiple#er as a function of the data select bits as shown.
dding more control address lines will allow the multiple#er to control more inputs but each control line configuration will connect only 'N6 input to the output. !hen the implementation of this )oolean e#pression above using individual logic gates would re$uire the use of seven individual gates consisting of N&, 'R and N'! gates as shown.
( C%annel Multiplexer using Logic *ates
!he symbol used in logic diagrams to identify a multiple#er is as follows.
Multiplexer Symbol
2ultiple#ers are not limited to Eust switching a number of different input lines or channels to one common single output. !here are also types that can switch their inputs to multiple outputs and have arrangements or ? to , D to - or even 1@ to ? etc configurations and an e#ample of a simple &ual channel ? input multiple#er :? to ; is given below(
(-to-+ C%annel Multiplexer
/ere in this e#ample the ? input channels are switched to individual output lines but larger arrangements are also possible. !his simple ? to configuration could be used for e#ample, to switch audio signals for stereo preamplifiers or mi#ers.
A,ustable Ampli#ier *ain s well as sending parallel data in a serial format down a single transmission line or connection, another possible use of multichannel multiple#ers is in digital audio applications as mi#ers or where the gain of an analogue amplifier can be controlled digitally, for e#ample.
Digitally A,ustable Ampli#ier *ain
/ere, the voltage gain of the inverting amplifier is dependent upon the ratio between the input resistor,Rin and its feedback resistor, Rf as determined in the Op-amp tutorials. single ?channel :Fuad; 5! switch configured as a ?to1 channel multiple#er is connected in series with the resistors to select any feedback resistor to vary the value of Rf . !he combination of these resistors will determine the overall gain of the amplifier, : v;. !hen the gain of the amplifier can be adEusted digitally by simply selecting the appropriate resistor combination. &igital multiple#ers are sometimes also referred to as "&ata electors" as they select the data to be sent to the output line and are commonly used in communications or high speed network switching circuits such as NBs and 6thernet applications. ome multiple#er %Bs have a single inverting buffer : N'! 8ate; connected to the output to give a positive logic output :logic "1", /8/; on one terminal and a complimentary negative logic output :logic "0", 'I; on another different terminal. t is possible to make simple multiple#er circuits from standard AND and OR gates as we have seen above, but commonly multiple#ersAdata selectors are available as standard i.c. packages such as the common !! >?1J1 D input to 1 line multiple#er or the !! >?1J- &ual ?input to 1 line multiple#er. 2ultiple#er circuits with much higher number of inputs can be obtained by cascading together two or more smaller devices. !he Multiplexer is a very useful combinational device that has its uses in many different applications such as signal routing, data communications and data bus control. I hen used with a demultiple#er, parallel data can be transmitted in serial form via a single data link such as a fibreoptic cable or telephone line. !hey can also be used to switch either analogue, digital or video signals, with the switching current in analogue power circuits limited to below 10m to 0m per channel in order to reduce heat dissipation. n the ne#t tutorial about combinational logic devices, we will look at the reverse of the Multiplexer called the Demultiplexer which takes a single input line and connects it to multiple output lines.
T%e Demultiplexer
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T%e Demultiplexer !he data distributor, known more commonly as a Demultiplexer or "&emu#", is the e#act opposite of theMultiplexer we saw in the previous tutorial. !he demultiple#er takes one single input data line and then switches it to any one of a number of individual output lines one at a time. !he demultiplexerconverts a serial data signal at the input to a parallel data at its output lines as shown below.
)-to-( C%annel De-multiplexer
ddressing b
a
nput elected
0
0
0
1
)
1
0
%
1
1
&
!he )oolean e#pression for this 1to? Demultiplexer above with outputs to & and data select lines a, b is given as( + G ab H ab) H ab% H ab& !he function of the Demultiplexer is to switch one common data input line to any one of the ? output data lines to & in our e#ample above. s with the multiple#er the individual solid state switches are selected by the binary input address code on the output select pins "a" and "b" as shown.
s with the previous multiplexer circuit , adding more address line inputs it is possible to switch more outputs giving a 1ton data line outputs. ome standard demultiple#er %Bs also have an additional "enable output" pin which disables or prevents t he input from being passed to t he selected output. lso some have latches built into their outputs to maintain the output logic level after the address inputs have been changed. /owever, in standard decoder type circuits the address input will determine which single data output will have the same value as the data input with all other data outputs having the value of logic "0". !he implementation of the )oolean e#pression above using individual logic gates would re$uire the use of si# individual gates consisting of N& and N'! gates as shown.
( C%annel Demultiplexer using Logic *ates
!he symbol used in logic diagrams to identify a demultiple#er is as follows.
T%e Demultiplexer Symbol
tandard Demultiplexer % packages available are the !! >?1-D 1 to Doutput demultiple#er, the !! >?1-K &ual 1to? output demultiple#er or t he %2' %&?J1? 1to1@ output demultiple#er. nother type of demultiple#er is the ?pin, >?1J? which is a ?bit to 1@line demultiple#erAdecoder. /ere the individual output positions are selected using a ?bit binary coded input. ike multiple#ers, demultiple#ers can also be cascaded together to form higher order demultiple#ers. Unlike multiple#ers which convert data from a single data line to multiple lines and demultiple#ers which convert multiple lines to a single data line, there are devices available which convert data to and from multiple lines and in the ne#t tutorial about combinational logic devices, we will look at Encoers which convert multiple input lines into multiple output lines, converting t he data from one f orm to another.
riority Encoer
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T%e Digital Encoer Unlike a multiple#er that selects one individual data input line and then sends that data to a single output line or switch, a Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at a time and then converts them into a single encoded output. o we can say that a binary encoder, is a multiinput combinational logic circuit that converts the logic level "1" data at its inputs into an e$uivalent binary code at its output. 8enerally, digital encoders produce outputs of bit, -bit or ?bit codes depending upon the number of data input lines. n "nbit" binary encoder has n input lines and nbit output lines with common types that include ?to, Dtoand 1@to? line configurations. !he output lines of a digital encoder generate the binary e$uivalent of the input line whose value is e$ual to "1" and are available to encode either a decimal or he#adecimal input pattern to typically a binary or ).%.&. output code.
(-to-+ 'it 'inary Encoer
'ne of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one input present at logic level "1". +or e#ample, if we make inputs &1and & /8/ at logic "1" both at the same time, the resulting output is neither at "01" or at "10" but will be at "11" which is an output binary number that is different to the actual input present. lso, an output code of all logic "0"s can be generated when all of its inputs are at "0" 'R when input &0 is e$ual to one. 'ne simple way to overcome this problem is to "5rioritise" the level of each input pin and if there was more than one input at logic level "1" the actual output code would only correspond to the input with the highest designated priority. !hen this type of digital encoder is known commonly as a Priority Encoder or -encoer for short.
riority Encoer
!he Priority Encoder solves the problems mentioned above by allocating a priority level to each input. !he priority encoders output corresponds to the currently active input which has the highest priority. o when an input with a higher priority is present, all other inputs with a lower priority will be ignored. !he priority encoder comes in many different forms with an e#ample of an Dinput priority encoder along with its truth table shown below.
.-to-/ 'it riority Encoer
5riority encoders are available in standard % form and the !! >?1?D is an Dto- bit priority encoder which has eight active 'I :logic "0"; inputs and provides a -bit code of the highest ranked input at its output. 5riority encoders output the highest order input first for e#ample, if input lines " &", "&-" and "&J" are applied simultaneously the output code would be for input " &J" :"101"; as this has the highest order out of the - inputs. 'nce input "&J" had been removed the ne#t highest output code would be for input " &-" :"011";, and so on. !he truth table for a Dto- bit priority encoder is given as(
&igital nputs
)inary 'utput
&>
&@
&J
&?
&-
&
&1
&0
F
F1
F0
0
0
0
0
0
0
0
)
0
0
0
0
0
0
0
0
0
)
C
0
0
1
0
0
0
0
0
)
C
C
0
1
0
0
0
0
0
)
C
C
C
0
1
1
0
0
0
)
C
C
C
C
1
0
0
0
0
)
C
C
C
C
C
1
0
1
0
)
C
C
C
C
C
C
1
1
0
)
C
C
C
C
C
C
C
1
1
1
+rom this truth table, the )oolean e#pression for the encoder above with inputs &0 to &> and outputsF0, F1, F is given as( 'utput F0
'utput F1
'utput F
!hen the final )oolean e#pression for the priority encoder including the 9ero inputs is defined as(
n practice these 9ero inputs would be ignored allowing the implementation of the final )oolean e#pression for the outputs of the Dto- priority encoder above to be constructed using individual 'Rgates as follows.
Digital Encoer using Logic *ates
Encoer Applications 0eyboar Encoer 5riority encoders can be used to reduce the number of wires needed in a particular circuits or application that have multiple inputs. +or e#ample, assume that a microcomputer needs to read the 10? keys of a standard FI6R!L keyboard where only one key would be pressed either "/8/" or "'I" at any one time. 'ne way would be to connect all 10? wires from the keys directly to the computer but this would be impractical for a small home 5%, but another better way would be to use a priority encoder. !he 10? individual buttons or keys could be encoded into a standard % code of only >bits :0 to 1> decimal; to represent each key or character of the keyboard and then inputted as a much smaller >bit ).%.& code directly to the computer. Meypad encoders such as the >?%K- 0key encoder are available to do Eust that.
ositional Encoers nother more common application is in magnetic positional control as used on ships navigation or for robotic arm positioning etc. /ere for e#ample, the angular or rotary position of a compass is converted into a digital code by a >?1?D Dto- line priority encoder and inputted to the systems computer to provide navigational data and an e#ample of a simple D position to -bit output compass encoder is shown below. 2agnets and reed switches could be used at each compass point to indicate the needles angular position.
riority Encoer Na1igation
%ompass &irection
)inary 'utput F0
F1
F
North
0
0
0
North6ast
0
0
1
6ast
0
1
0
outh6ast
0
1
1
outh
1
0
0
outhIest
1
0
1
Iest
1
1
0
NorthIest
1
1
1
2nterrupt Requests 'ther applications especially for Priority Encoders may include detecting interrupts in microprocessor applications. /ere the microprocessor uses interrupts to allow peripheral devices such as the disk drive, scanner, mouse, or printer etc, to communicate with it, but the microprocessor can only "talk" to one peripheral device at a time. !he processor uses "nterrupt Re$uests" or "RF" signals to assign priority to the devices to ensure that the most important peripheral device is serviced first. !he order of importance of the devices will depend upon their connection to the priority encoder.
RF Number
!ypical Use
&escription
RF 0
ystem timer
nternal ystem !imer.
RF 1
Meyboard
Meyboard %ontroller.
RF -
%'2 %'2?
econd and +ourth erial 5ort.
RF ?
%'21 %'2-
+irst and !hird erial 5ort.
RF J
ound
ound %ard.
RF @
+loppy disk
+loppy &isk %ontroller.
RF >
5arallel port
5arallel 5rinter.
RF 1
2ouse
5A 2ouse.
RF 1?
5rimary &6
5rimary /ard &isk %ontroller.
RF 1J
econdary &6
econdary /ard &isk %ontroller.
)ecause implementing such a system using priority encoders such as the standard >?1?D priority encoder % involves additional logic circuits, purpose built integrated circuits such as the DJK 5rogrammable 5riority nterrupt %ontroller is available.
Digital Encoer Summary !hen to summarise, the Digital Encoder is a combinational circuit that generates a specific code at its outputs such as binary or )%& in response to one or more active inputs. !here are two main types of digital encoder. !he Binary Encoder and the Priority Encoder .
!he Binary Encoder converts one of n inputs into an nbit output. !hen a binary encoder has fewer output bits than the input code. )inary encoders are useful for compressing data and can be constructed from simple N& or 'R gates. 'ne of the main disadvantages of a standard binary encoder is that it would produce an error at its outputs if more than one input were active at the same time. !o overcome this problem priority encoders were developed. !he Priority Encoder is another type of combinational circuit similar to a binary encoder, e#cept that it generates an output code based on the highest prioritised input. 5riority encoders are used e#tensively in digital and computer systems as microprocessor interrupt controllers where they detect the highest priority input. n the ne#t tutorial about combinational logic devices, we will look at complementary function of the encoder called a Decoer which convert an nbit input code to one of its n output lines.
T%e 'inary Decoer
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'inary Decoer Decoder is the e#act opposite to that of an "6ncoder" we looked at in the last tutorial. t is basically, a combinational type logic circuit that converts the binary code data at its input into one of a number of different output lines, one at a time producing an e$uivalent decimal code at its output. Binary Decoders have inputs of bit, -bit or ?bit codes depending upon the number of data input lines, and a nbitdecoder has n output lines. !herefore, if a binary decoder receives n inputs :usually grouped as a binary or )oolean number; it activates one and only one of its n outputs based on that input with all other outputs deactivated. decoders output code normally has more bits than its input code and practical "binary decoder" circuits include, to?, -toD and ?to1@ line configurations. Binary Decoder converts coded inputs into coded outputs, where the input and output codes are different and decoders are available to "decode" either a )inary or )%& :D?1 code; input pattern to typically a &ecimal output code. %ommonly available )%&to&ecimal decoders include the !! >?? or the %2' ?0D. n e#ample of a to ? line decoder along with its truth table is given below. t consists of an array of four NN& gates, one of which is selected for each combination of the input signals and ).
A +-to-( 'inary Decoers3
n this simple e#ample of a to? line binary decoder, the binary inputs and ) determine which output line from &0 to &- is "/8/" at logic level "1" while the remaining outputs are held "'I" at logic "0" so only one output can be active :/8/; at any one time. !herefore, whichever output line is "/8/" identifies the binary code present at the input, in other words it "decodes" the binary input and these types of binary decoders are commonly used as Aress Decoers in microprocessor memory applications.
>?1-D )inary &ecoder ome binary decoders have an additional input labelled "6nable" that controls the outputs from the device. !his allows the decoders outputs to be turned "'N" or "'++" and we can see that the logic diagram of the basic decoder is identical to that of the basic demultiple#er. !hen, we can say that a binary decoder is a demultiple#er with an additional data line that is used to enable the decoder. n alternative way of looking at the decoder circuit is to regard inputs , ) and % as address signals. 6ach combination of , ) or % defines a uni$ue address which can access a location having that address. ometimes it is re$uired to have a Binary Decoder with a number of outputs greater than is available, or if we only have small devices available, we can combine multiple decoders together to form larger decoder networks as shown. /ere a much larger ?to1@ line binary decoder has been implemented using two smaller -toD decoders.
A (-to-)4 'inary Decoer Con#iguration3
nputs , ), % are used to select which output on either decoder will be at logic "1" :/8/; and input &is used with the enable input to select which encoder either the first or second will output the "1".
Memory Aress Decoer3 Binary Decoders are most often used in more comple# digital systems to access a particular memory location based
on an "address" produced b y a computing device. n modern microprocessor systems the amount of memory re$uired can be $uite high and is generally more than one single memory chip alone. 'ne method of overcoming this problem is to connect lots of individual memory chips together and to read the data on a common "&ata )us". n order to prevent the data being "read" from each memory chip at the same time, each memory chip is selected individually one at time and this process is known as Aress Decoing. n this application, the address represents the coded data input, and the outputs are the particular memory element select signals. 6ach memory chip has an input called C%ip Select or CS which is used by the 25U to select the appropriate memory chip and a logic "1" on this input selects the device and a logic "0" on the input deselects it. )y selecting or deselecting each chip, allows us to select the correct memory device for a particular address and when we specify a particular memory address, the corresponding memory location e#ists 'NL in one of the chips. +or e#ample, ets assume we have a very simple microprocessor system with only 1Mb of R2 memory and 10 address lines. !he memory consists of 1D#Dbit :1D#D G 10? bytes; devices and for 1Mb we will need D individual memory devices but in order to select the correct memory chip we will also re$uire a -toD line binary decoder as shown below.
Memory Aress Decoing3
!he binary decoder re$uires - address lines, : 0 to ; to select each one of the D chips :the lower part of the address;, while the remaining > address lines : - to K; select the correct memory location on that chip :the upper part of the address;. /aving selected a memory location using the address bus, the information at the particular internal memory location is sent to the "&ata )us" for use by the microprocessor. !his is of course a simple e#ample but the principals remain the same for all types of memory chips or modules. Binary Decoders are very useful devices for converting one digital format to another, such as binary or )%& type data
into decimal or octal etc and commonly available decoder %7s are the !! >?1-D -toD line binary decoder or the >?1J? ?to1@ line decoder. !hey are also very useful for interfacing to >segment displays such as the !! >??> which we will look at in the ne#t tutorial.
Display Decoer
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'CD to 5-Segment Display Decoer s we saw in the previous tutorial, a Digital Decoder %, is a device which converts one digital format into another and one of the most commonly used device for doing this is called the )inary %oded &ecimal :)%&; to >egment &isplay &ecoder. >segment LED :ight 6mitting &iode; or LCD :i$uid %rystal &isplay; type displays, provide a very convenient way of displaying information or digital data in the form of numbers, letters or even alphanumerical characters. !ypically >segment displays consist of seven individual coloured 6&7s :called the segments;, within one single display package. n order to produce the re$uired numbers or /6C characters from 0 to Kand to + respectively, on the display the correct combination of 6& segments need to be illuminated and B"D to #$segment Display Decoders such as the >??> do Eust that. standard >segment 6& display generally has D input connections, one for each 6& segment and one that acts as a common terminal or connection for all the internal display segments. ome single displays have also have an additional input pin to display a decimal point in their lower right or left hand corner. n electronics there are two important types of >segment 6& digital display. •
1. !he %ommon %athode &isplay :%%&; * n the common cathode display, all the cathode connections of the 6&7s are Eoined together to logic "0" or ground. !he individual segments are illuminated by application of a "/8/", logic "1" signal to the individual node terminals.
•
•
. !he %ommon node &isplay :%&; * n the common anode display, all the anode connections of the 6&7s are Eoined together to logic "1" and the individual segments are illuminated by connecting the individual %athode terminals to a "'I", logic "0" signal.
Common Cat%oe an Common Anoe !ormat
6lectrical connection of the individual diodes for a common cathode display and a common anode display and by illuminating each light emitting diode individually, they can be made to display a variety of numbers or characters.
5-Segment Display !ormat
o in order to display the number - for e#ample, segments a, b, c, d and g would need to be illuminated. f we wanted to display a different number or letter then a different set of segments would need to be illuminated. !hen for a >segment display, we can produce a truth table giving the segments that need to be illuminated in order to produce the re$uired character as shown below.
Trut% Table #or a 5-segment isplay
Individual Segments a
b
c
d
e
f
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× ×
×
×
×
×
×
Display
b
c
d
e
f
g
0
×
×
×
×
×
×
×
8
1
×
×
×
×
×
×
9
×
2
×
×
×
×
×
×
×
3
×
×
×
×
b
×
×
4
×
×
×
×
×
×
5
×
×
×
×
6
×
×
×
×
×
Individual Segments a
×
g
Display
× ×
×
×
! ×
d
×
"
×
×
×
#
×
×
×
×
$
>egment &isplay 6lements for all Numbers. t can be seen that to display any single digit number from to K or letter from to +, we would need > separate segment connections plus one additional connection for the 6&7s "common" connection. lso as the segments are basically a standard light emitting diode, the driving circuit would need to produce up to 0m of current to illuminate each individual segment and to display the number D, all > segments would need to be lit resulting a total current of nearly 1?0m, :D # 0m;. 'bviously, the use of so many connections and power consumption is impractical for some electronic or microprocessor based circuits and so in order to reduce the number of signal lines re$uired to drive Eust one single display, display decoders such as the )%& to >egment &isplay &ecoder and &river %7s are used instead.
'inary Coe Decimal 'inary Coe Decimal :)%& or "D?1" )%&; numbers are made up using Eust ? data bits :a nibble or half a byte; similar to the "exaecimal numbers we saw in the binary tutorial, but unlike he#adecimal numbers that range in full from 0 through to +, )%& numbers only range from 0 to K, with the binary number patterns of 1010 through to 1111 : to +; being invalid inputs for this type of display and so are not used as shown below.
Decimal %!D %ina&y 'atte&n 8 4 2 1
Decimal
0
0
0
0
0
0
1
0
0
0
1
1
2
0
0
1
0
2
3
0
0
1
1
3
4
0
1
0
0
4
5
0
1
0
1
5
6
0
1
1
0
6
#
0
1
1
1
#
%ina&y 'atte&n
8 4 2 1
%!D
8
1
0
0
0
8
9
1
0
0
1
9
10
1
0
1
0 Invalid
11
1
0
1
1 Invalid
12
1
1
0
0 Invalid
13
1
1
0
1 Invalid
14
1
1
1
0 Invalid
15
1
1
1
1 Invalid
'CD to 5-Segment Display Decoers binary coded decimal :)%&; to >segment display decoder such as the !! >??> or >??D, have ? )%& inputs and > output lines, one for each 6& segment. !his allows a smaller ?bit binary number :half a byte; to be used to
display all the denary numbers from 0 to K and by adding two displays together, a full range of numbers from 00 to KK can be displayed with Eust a single byte of D data bits.
'CD to 5-Segment Decoer
!he use of pac6e )%& allows two )%& digits to be stored within a single byte :Dbits; of data, allowing a single data byte to hold a )%& number in the range of 00 to KK. n e#ample of the ?bit )%& input : 0100 ; representing the number ? is given below.
Example No)
n practice current limiting resistors of about 1J0< to 0< would be connected in series between the decoderAdriver chip and each 6& display segment to limit the ma#imum current flow. &ifferent display decoders or drivers are
available for the different types of display available, e.g. >??D for commoncathode 6& types, >??> for commonanode 6& types, or the %2' %&?J?- for li$uid crystal display :%&; types. i$uid crystal displays :%&Bs; have one maEor advantage over similar 6& types in that they consume much less power and nowadays, both %& and 6& displays are combined together to form larger &ot2atri# lphanumeric type displays which can show letters and characters as well as numbers in standard Red or !ricolour outputs.
T%e 'inary Aer
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T%e 'inary Aer nother common and very useful combinational logic circuit which can be constructed using Eust a few basic logic gates and adds together binary numbers is the Binary %dder circuit. !he )inary dder is made up from standard N& and 6#'R gates and allow us to "add" together single bit binary numbers, a and b to produce two outputs called the U2 of the addition and a %RRL called the%arryout, : % out ; bit. 'ne of the main uses for the Binary %dder is in arithmetic and counting circuits. %onsider the addition of two denary :base 10; numbers below.
1-
:ugend;
H >DK
)
:ddend;
K1
U2
6ach column is added together starting from the right hand side and each digit has a weighted value depending upon its position in the c olumns. s each column is added together a carry is generated if the result is greater or e$ual to ten, the base number. !his carry is then added to the result of the addition of the ne#t column to the left and so on, simple school math7s addition. !he adding of binary numbers is basically the same as that of adding decimal numbers but this time a carry is only generated when the result in any column is greater or e$ual to "", the base number of binary.
'inary Aition Binary %ddition follows the same basic rules as for the denary addition above e#cept in binary there are only
two digits and the largest digit is "1", so any "U2" greater than 1 will result in a "%RRL". !his carry 1 is passed over to the ne#t column for addition and so on. %onsider the single bit addition below.
0
0
1
1
H0
H1
H0
H1
0
1
1
10
!he single bits are added together and "0 H 0", "0 H 1", or "1 H 0" results in a sum of "0" or "1" until you get to "1 H 1" then the sum is e$ual to "". +or a simple 1bit addition problem like this, the resulting carry bit could be ignored which would result in an output truth table resembling that of an Ex-OR *ate as seen in the ogic 8ates section and whose result is the sum of the two bits but without the carry.
n 6#'R gate only produces an output "1" when either input is at logic "1", but not both. /owever, all microprocessors and electronic calculators re$uire the carry bit to correctly calculate the e$uations so we need to rewrite them to include bits of output data as shown below.
00
00
01
01
H 00
H 01
H 00
H 01
00
01
01
10
+rom the above e$uations we know that an Ex-OR gate will only produce an output "1" when "6!/6R" input is at logic "1", so we need an additional output to produce a carry output, "1" when ")'!/" inputs "" and ")" are at logic "1" and a standard AND *ate fits the bill nicely. )y combining the 6#'R gate with the N& gate results in a simple digital binary adder circuit known commonly as the ""al# Aer " circuit.
T%e "al# Aer Circuit )-bit Aer $it% Carry-Out ymbol
!ruth !able
)
U2
%RRL
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
)oolean 6#pression( um G
⊕
)
%arry G 3 )
+rom the truth table we can see that the U2 :; output is the result of the 6#'R gate and the %arryout :%out; is the result of the N& gate. 'ne maEor disadvantage of the /alf dder circuit when used as a binary adder, is that there is no provision for a "%arryin" from the previous c ircuit when adding together multiple data bits. +or e#ample, suppose we want to add together two Dbit bytes of data, any resulting carry bit would need to be able to "ripple" or move across the bit patterns starting from the least significant bit :);. !he most complicated operation the half adder can do is "1 H 1" but as the half adder has no carry input the resultant added value would be incorrect. 'ne simple way to overcome this problem is to use a &ull %dder type binary adder circuit.
T%e !ull Aer Circuit !he main difference between the &ull %dder and the previous seen 'alf %dder is that a full adder has three inputs, the same two single bit binary inputs and ) as before plus an additional Carry-In :%in; input as shown below.
!ull Aer $it% Carry-2n
ymbol
!ruth !able
)
%in
um
%out
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
)oolean 6#pression( um G
⊕ ) ⊕ %in
!he 1bit &ull %dder circuit above is basically two half adders connected together and consists of three6# 'R gates, two N& gates and an 'R gate, si# logic gates in total. !he truth table for the full adder includes an additional column to take into account the %arryin input as well as the summed output and carryoutput. ?bit full adder circuits are available as standard % packages in the f orm of the !! >?D- or the >?D- which can add together two ?bit binary numbers and generate a U2 and a%RRL output. )ut what if we wanted to add together two nbit numbers, then n 1bit full adders need to be connected together to produce what is known as the (ipple "arry %dder.
T%e (-bit 'inary Aer !he (ipple "arry Binary %dder is simply n, full adders cascaded together with each full adder represents a single weighted column in the long addition with the carry signals producing a "ripple" effect t hrough the binary adder from right to left. +or e#ample, suppose we want to "add" together two ?bit numbers, the two outputs of the first full adder will provide the first place digit sum of the addition plus a carryout bit that acts as the carryin digit of the ne#t binary adder. !he second binary adder in the chain also produces a summed output :the nd bit; plus another carryout bit and we can keep adding more full adders to the combination to add larger numbers, linking the carry bit output from the first full binary adder to the ne#t full adder, and so forth. n e#ample of a ?bit adder is given below.
A (-bit 'inary Aer
'ne main disadvantage of "cascading" together 1bit )inary adders to add large binary numbers is that if inputs and ) change, the sum at its output will not be valid until any carryinput has "rippled" through every full adder in the chain. %onse$uently, there will be a finite dela y before the output of a adder responds to a change in its inputs resulting in the accumulated delay especially in large multibit binary adders becoming prohibitively large. !his delay is called ropagation elay. lso "overflow" occurs when an nbit adder adds two numbers together whose sum is greater than or e$ual to n 'ne solution is to generate the carryinput signals directly from the and ) inputs rather than using the ripple arrangement above. !his then produces another type of binary adder circuit called a "arry *oo+ %,ead Binary %dder were the speed of the parallel adder can be gr eatly improved using carrylook ahead logic.
T%e (-bit 'inary Subtractor Now that we know how to "&&" together two ?bit binary numbers how would we subtract two ?bit binary numbers, for e#ample, ) using the circuit above. !he answer is to use Oscomplement notation on all the bits in ) must be complemented :inverted; and an e#tra one added using the carryinput. !his can be achieved by inverting each )input bit using an inverter or N'!gate. lso, in the above circuit for the ?bit binary adder, the first carryin input is held 'I at logic "0", for the circuit to perform subtraction this input needs to be held /8/ at "1". Iith this in mind a ripple carry adder can with a small modification be used to perform half subtraction, full subtraction andAor comparison. !here are a number of ?bit fulladder %s available such as the >?D- and %&?00D. which will add two ?bit binary number and provide an additional input carry bit, as well as an output carry bit, so you can cascade them together to produce Dbit, 1bit, 1@bit, etc. adders.
Digital Comparator
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T%e Digital Comparator nother common and very useful combinational logic circuit is that of the Digital "omparator circuit. &igital or )inary %omparators are made up from standard N&, N'R and N'! gates that compare the digital signals present at their input terminals and produce an output depending upon the condition of those inputs. +or e#ample, along with being able to add and subtract binary numbers we need to be able to compare them and determine whether the value of input is greater than, smaller than or e$ual to the value at input ) etc. !he digital comparator accomplishes this using several logic gates that operate on the principles of )oolean algebra. !here are two main types of Digital "omparator available and these are. •
1. dentity %omparator an Identity Comparator is a digital comparator that has only one output terminal for when G ) either "/8/" G ) G 1 or "'I" G ) G 0
•
•
. 2agnitude %omparator a Magnitude Comparator is a type of digital comparator that has three output terminals, one each for e$uality, G ) greater than, P ) and less than Q ) !he purpose of a Digital "omparator is to compare a set of variables or unknown numbers, for e#ample :1, , -, .... n, etc; against that of a constant or unknown value such as ) :)1, ), )-, .... )n, etc; and produce an output condition or flag depending upon the result of the comparison. +or e#ample, a magnitude comparator of two 1bits, : and ); inputs would produce the following three output conditions when compared to each other.
Ihich means( is greater than ), is e$ual to ), and is less than ) !his is useful if we want to compare two variables and want to produce an output when an y of the above three conditions are achieved. +or e#ample, produce an output from a counter when a certain count number is reached. %onsider the simple 1bit comparator below.
)-bit Digital Comparator
!hen the operation of a 1bit digital comparator is given in the following !ruth !able.
Trut% Table
nputs
'utputs
)
P)
G)
Q)
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
Lou may notice two distinct features about the comparator from the above truth table. +irstly, the circuit does not distinguish between either two "0" or two "1"7s as an output G ) is produced when they are both e$ual, either G ) G "0" or G ) G "1". econdly, the output condition for G ) resembles that of a commonly available logic gate, the 6#clusiveN'R or 6#N'R function :e$uivalence; on each of the nbits giving( F G ⊕ ) &igital comparators actually use 6#clusiveN'R gates within their design for comparing their respective pairs of bits. Ihen we are comparing two binary or )%& values or variables against each other, we are comparing the "magnitude" of these values, a logic "0" against a logic "1" which is where the term Magnitude "omparator comes from. s well as comparing individual bits, we can design larger bit comparators by cascading together n of these and produce a nbit comparator Eust as we did for the nbit adder in the previous tutorial. 2ultibit comparators can be constructed to compare whole binary or )%& words to produce an output if one word is larger, e$ual to or less than the other. very good e#ample of this is the ?bit Magnitude "omparator . /ere, two ?bit words :"nibbles"; are compared to each other to produce the relevant output with one word connected to inputs and the other to be compared against connected to input ) as shown below.
(-bit Magnitue Comparator
ome commercially available digital comparators such as the !! >?DJ or %2' ?0@- ?bit magnitude comparator have additional input terminals that allow more individual comparators to be "cascaded" together to compare words larger than ?bits with magnitude comparators of "n"bits being produced. !hese cascading inputs are connected directly to the corresponding outputs of the previous comparator as shown to compare D, 1@ or even -bit words.
.-bit 7or Comparator
Ihen comparing large binary or )%& numbers like the e#ample above, to save time the comparator starts by
comparing the highestorder bit :2); first. f e$uality e#ists, G ) then it compares the ne#t lowest bit and so on until it reaches the lowestorder bit, : );. f e$uality still e#ists then the two numbers are defined as being e$ual. f ine$uality is found, either P ) or Q ) the relationship between the two numbers is determined and the comparison between any additional lower order bits stops. Digital "omparator are used widely in nalogueto&igital converters, :&%; and rithmetic ogic Units, :U; to perform a variety of arithmetic operations.
