8. Asynchronous Sequential Logic
8-1
Chapter 8. Asynchronous Sequential Logic (Brief Introduction) Introduction B
An asynchronous sequential circuit is a sequential circuit whose behavior depends only on the order in which its input signals change and can be affected at any instant of time. 6
In addition to the FFs, a register may have combinational gates that control when and how new information is transferred into the register.
Combinational
input
output
Logic
state
excitation Delay
Figure 1: Asynchronous sequential circuit model.
:
input variables
:
output variables
:
state variables (present state) :
excitation variables (next state)
State transition occurs when there is an input change (no clock pulses).
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
8. Asynchronous Sequential Logic
8-2
Memory (delay) elements are either latches (unclocked) or time-delay elements (instead of clocked FFs as in a synchronous sequential circuit).
An asynchronous sequential circuit quite often resembles a combinational circuit with feedback.
Faster and often cheaper than synchronous ones, but more difficult to design, verif ve rify y, or te test st (d (due ue to po possi ssibl blee tim timing ing pr prob oblem lemss in invo volv lved ed in th thee fee feedb dbac ack k pa path) th)..
B
Steady-state condition: 6
B
To ensure proper operation, simultaneous changes of 2 or more input variables are usually prohibited.
Fundamental-mode Fundamentalmode operat operation ion:: on only ly one in inpu putt var ariab iable le can ch chan ange ge at an any y time, and the time between 2 input changes must be longer than the time it takes the circuit to reach a stable state.
Analysis Procedure The analysis consists consists of obtaini obtaining ng a table or a diagram that describes describes the sequen sequence ce of internal states and outputs as a function of changes in the input variables. 1. Determine all feedback loops. 2. Desi Design gnate ate ea each ch fe feed edba back ck-lo -loop op ou outp tput ut wit with h an and d its co corre rresp spon ondi ding ng inp input ut wit with h for , where is the number of feedback loops. 3. Derive the boolean functions for all
’s.
4. Plot the transition table from the equatio equations. ns.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
8. Asynchronous Sequential Logic
8-3
.
0 1 00 00 01
.
01 11 01
.
11 11 10 10 00 10 Transition table
Excitation variables:
and
Secondary variables:
and
The delay associated with each feedback loop is obtained from the propagation delay between each input and its corresp corresponding onding output.
In an asynchronous sequential circuit, the internal state can change immediately after a change in the input.
B
Total state: internal state + input value.
B
transiti sition on table in whic which h stat states es are nam named ed by let letter ter symbols symbols Flow table: a tran instead of specific binary values. 6
B
Primitive flow table: one that has only one stable state in each row. 6
B
The flow table also includes the output values of the circuit for each stable state.
To obtain the circuit described by a flow table, it is necessary to assign to each state a distinct binary value, which converts the flow table into a transition table.
when n 2 or more binary binary sta state te variable variabless cha change nge value value in reRace condition: whe sponse to a change in an input variable.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
8. Asynchronous Sequential Logic 6
8-4
May cause the state variables to change in an unpredictable manner.
B
Noncritical race: final stable state does not depend on the order in which the state variables change.
B
Critical race: final stable state depends on the order in which the state variables change. 6
For proper operation, critical races must be avoided. avoided.
6
Races may be av avoided oided by making a proper state assignm assignment. ent.
6
Races can be avoided by directing the circuit through intermediate unstable states with a unique state-variable change.
Design Procedure 1. Obtain a primitive flow table. 2. Reduce the flow table. 3. Assign binary binary state variables variables to obtain the transition transition table. 4. Assign output values to the dashes to obtain the output maps. 5. Simplify the excitation and output functions. 6. Draw the logic diagram. We will design a gated latch circuit with 2 inputs, (gate (gate)) and (data), and one output, . The binary value at the input is transferred to the output when and only when . When falls to 0, the latch retains the value at the output, which does not change even if changes. The table of total states and the corresponding primitive flow table is shown shown below. below. Note that both inputs are not allowed to change simultaneously ( entries in the table).
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
8. Asynchronous Sequential Logic Inputs
State
Output
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Comments 00
0 1 0 1 1 0
1 1 0 0 0 0
0 1 0 0 1 1
After
01
11
10
or
After After or After
Table of Total States
Primitive Flow Table
states to be merged
The next step is to reduce the primitive primitive flow table, which is shown below. below. Then, 00
01
11
10
00
01
11
10
following state assignment, we convert the flow table into a transition table (by assigning and ). From the table, the simplified O/P function ( ) and the excitation function ( ) with respect to , , and can be derived using the K-map method. Note that the don’t-cares are assigned such that .
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
