Introduction to CMOS Logic Circuits
Digital circuit Design : An Overview
Digital IC technologies and logic circuit families
Logic families Bipolar – Uses bipolar junction transistors – npn or pnp silicon structure – Small current into very thin base layer controls large currents
between emitter and collector – Base currents limit integration density MOS
- Uses nMOS nMOS and pMOS pMOS Metal Oxide Semiconductor Field Effect Transistors – nMOS and pMOS MOSFETS – Voltage applied to insulated gate controls current between source and drain – Low power allows very high integration
Transistor Evolution Transistor –Bardeen et.al. (Bell Labs) in 1947
Bipolar transistor – Shockley in 1949
First bipolar digital logic gate – Harris in 1956
First monolithic IC – Jack Kilby in 1958
First commercial IC logic gates – Fairchild 1960
TTL – 1962 into the 1990’s
ECL – 1974 into the 1980’s
MOS Technology Evolution • MOSFET transistor - Lilienfeld (Canada) in 1925 and
Heil (England) in 1935 • CMOS – 1960’s, but plagued with manufacturing problems (used in watches due to their power limitations) • PMOS in 1960’s (calculators) • NMOS in 1970’s (4004, 8080) – for speed • CMOS in 1980’s – preferred MOSFET technology
because of power benefits • BiCMOS, Gallium-Arsenide, Silicon-Germanium • SOI, Copper-Low K, strained silicon, High-k gate oxide...
Bipolar • TTL (Transistor-transistor logic) had been used for many
years . • ECL (Emitter –Coupled Logic) : basic element is the differential BJT pair. • BiCMOS : combines the high speed of BJT’s with low power dissipation of CMOS . • GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .
CMOS • Replaced NMOS (much lower power dissipation) • Small size, ease of fabrication • Channel length has decreased significantly (as short as • • • •
0.06 µm or shorter) Low power dissipation than bipolar logic circuits ( can pack more) . High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) High levels of integration for both logic (chapter 10) and memory circuits. Dynamic logic to further reduce power dissipation and to increase speed performance .
Features to be Considered • Interface circuits for different families • Logic flexibility • Speed • Complex functions • Noise immunity • Temperature • Power dissipation • Co$t
Design Abstraction Levels SYSTEM
MODULE
+ GATE
CIRCUIT
DEVICE
G D
S n+
n+
N-type and P-type
MOS Structure NMOS
L – Distance between the source and the drain (Channel length) Channel
W – Width of the channel n+ - Silicon doped with higher concentration p - Silicon substrate doped with p+ - Silicon doped with higher concentration
Introduction to CMOS Logic Circuits •
CMOS stands for Complementary Metal Oxide Semiconductor – Complementary: there are N-type and P-type transistors. N-type transistors use electrons as the current carriers. P-type transistors use holes as the current carriers. •
Electrons are free carriers in the conduction band with energy of Ec or just above the conduction band edge. Free electrons are generated by doping the silicon with an N-type impurity such as phosphorous or arsenic.
•
A hole is a current carrier due to the absence of an electron in a covalent bond state, i.e. a missing electron which would otherwise be part of a silicon-to-silicon bond. Holes are free carriers in the valence band with energy of Ev o r just below the valence band edge. Holes are generated by doping the silicon with a P-type impurity such as boron.
– Metal: the gate of the transistor was made of aluminum metal in the early days, but is made of polysilicon today (for the past 25 years or more). – Oxide: silicon dioxide is the material between the gate and the channel – Semiconductor: the semiconductor material is silicon, a type IV element in the periodic chart. Each silicon atom bonds to four other silicon atoms in a tetrahedral crystal structure.
CMOS NMOS and PMOS Transistors oxide
oxide
gate
gate
N + N
source
N+
P substrate
P+
drain
N channel device
source
P+
N well
drain
P channel device
• N channel device: built directly in the P substrate with N-doped source and drain junctions and normally N-doped gate conductor – Requires positive voltage applied to gate and drain (with respect to source) for electrons to flow from source to drain (thought of as positive drain current)
•
P channel device: built in an N-well (a deep N-type junction diffused into the P substrate) with P-doped source and drain junctions and N or P-doped gate – Requires negative voltage applied to gate and drain (with respect to source) for electrons to flow from drain to source (thought of as negative d rain current)
N-FET and P-FET Devices as Switches • NMOS Device: positive voltage (“ 1” or high) on gate relative to source turns device ON and allows positive current to flow from drain to source (switch closed) – zero volts on gate (“ 0” or low) turns device OFF (open circuit) – Source (vs drain) is the most negative terminal –
oxide gate
N + N source
N+
P substrate
drain
N channel device
gate
source
drain substrate
N-FET device schematic
oxide gate
source
P+
P+
N well
gate
drain
P channel device
source
drain substrate
P-FET device schematic
•
PMOS Device: – Negative voltage (“0” or low) on gate relative to source turns device ON and allows (negative) current to flow from drain to source (closes switch) – Zero volts on gate relative to source (“1” or high) turns device OFF (closes switch) – source (vs drain) is the most positive terminal
3-D view of an NMOS
polysilicon gate W tox n+
L p-type body
n+
SiO2 gate oxide (good insulator, ox = 3.9)
Symbols NMOS
Vg + Vgd -
+ Vgs Vs
-
Vds
+
Vd
Vgs = Vg – Vs Vgd = Vg – Vd Vds = Vd – Vs = Vgs - Vgd
Operation Three regions of operation •Cutoff •Linear •Saturation
Cut-Off Mode Vgs = 0
+ -
g
s
d
n+
n+ p-type body b
No channel formed
+ -
Vgd
=0
Operation Linear Mode Vgs > Vt
+ -
g
+ -
s
d
n+
n+
Vgd = Vgs
Vds = 0
p-type body b
Vgs > Vt
+ -
g
s
+ d
n+
n+ p-type body b
Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt
Operation Saturation Mode Vgs > Vt
+ -
g
+ -
Vgd < Vt
d Ids
s
n+
n+ p-type body b
• The voltage drop at the induced channel (from the pinch-off point to the source remains fixed at Vgs – Vt
Vds > Vgs-Vt
pMOS Transistor • Similar, but doping and voltages reversed – Body tied to high voltage (VDD) – Gate low: transistor ON – Gate high: transistor OFF – Bubble indicates inverted behavior Source
Gate
Drain
Polysilicon SiO2
p+
p+ n
bulk Si
Power Supply Voltage • GND = 0 V • In 1980’s, VDD = 5V • VDD has decreased in modern processes – High VDD would damage modern tiny
transistors – Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0 , …
Transistors as Switches • We can view MOS transistors as electrically controlled
switches • Voltage at gate controls path from source to drain g=0 d nMOS
pMOS
d
g=1 d
OFF
g s
s
d
d
g
ON s d OFF
ON s
s
s
MOS Transistors Voltage-controlled resistance
PMOS
NMOS
MOSFET as Switches
MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor
nFET: an n-channel MOSFET that uses negatively charged electrons for electrical current flow
pFET: a p-channel MOSFET that uses positive charges for current flow
In many ways, MOSFETs behave like the idealized switches introduced in the previous section
The voltage applied to the gate determines the current flow between the source and drain terminals
(a) nFET symbol
(b) pFET symbol Figure 1 Symbols used for nFETs and pFETs
MOSFET as Switches
Early generations of silicon MOS logic circuits used both positive and negative supply voltages as Figure 2 showing
In modern designs require only a single positive voltage V DD and the ground connection, e.g. V DD = 5 V and 3.3 V or lower
Figure 2 Dual power supply voltages
The relationship between logic variables x and it’s voltages V x 0 V x
x
V DD
(1)
0 means that V x
0V
x 1 means that V x
V DD
(2)
(a) Power supply connection (b) Logic definitions Figure 3 Single voltage power supply
Switching Characteristics of MOSFET
In general,
»
Low voltages correspond to logic 0 values High voltages correspond to logic 1 values The transition region between the highest logic 0 voltage and the lowest logic 1 voltage is undefined
(b) Closed
Figure 4 nFET switching characteristics
nFET y x A which is valid iff A 1
(a) Open
(3)
pFET y x A which is valid iff A 0
(4)
(a) Open
(b) Closed
Figure 5 pFET switching characteristics
nMOS FET Threshold Voltages
An nFET is characterized by a threshold voltage V Tn that is positive, typical is around V Tn = 0.5 V to 0.7 V If V GSn V Tn , then the transistor acts like an open (off ) circuit and there is no current flow between the drain and source
If V GSn V Tn , then the nFET drain and source are connected and the equivalent switch is closed ( on)
Thus, to define the voltage V A that is associated with the binary variable A V A
V GSn
(5)
(a) Gate-source voltage
(b) Logic translation Figure 6 Threshold voltage of an nFET
pMOS FET Threshold Voltages
An pFET is characterized by a threshold voltage V Tp that is negative, typical is around V Tp = – 0.5 V to – 0.8 V If V SGp V Tp , then the transistor acts like an open ( off ) switch and there is no current flow between the drain and source
»
(a) Source-gate voltage
If V SGp V Tp , then the pFET drain and source are connected and the equivalent switch is closed ( on)
»
Thus, to the applied voltage V A we first sum voltage to write V A V SGp
V A V DD
V DD
(6)
V DD V SGp
(7)
V Tp
V A
0 V
V A
V DD
(8) Note that the transition between a logic 0 and a logic 1 is at (8) !
(9) (b) Logic translation Figure 7 pFET threshold voltage
nFET Pass Characteristics
An ideal electrical switch can pass any voltage applied to it
As Figure 8 (b), the output voltage V y is reduced to a value V 1 »
V DD V Tn
(10)
since
V GS n
V Tn
(a) Logic 0 transfer
Which is less than the input voltage VDD, called threshold voltage loss
Thus, we say that the nFET can only pass a weak logic 1; in other word, the nFET is said to pass a strong logic 0 can pass a voltage in the range [0, V 1]
(b) Logic 1 transfer Figure 8 nFET pass characteristics
Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V DD or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
Static CMOS V DD
In1 In2
PUN
PMOS Only
In3
F = G In1 In2
PDN
NMOS Only
In3
V SS
PUN and PDN are Dual Networks
Simple CMOS Circuits: The Inverter Gate • Vdd
Inverter Schematic
– NMOS & PMOS gates are connected together as the input
PMOS source
– NMOS & PMOS drains are connected together as the output
P-MOS
– NMOS & PMOS sources are connected to Gnd and Vdd, respectively.
PMOS drain Vout
Vin
– NMOS substrate is normally connected to Gnd for all NMOS devices in the circuit
NMOS drain
N-MOS NMOS source
Gnd
The simplest complementary MOS (CMOS) circuit is the inverter:
– PMOS well is normally connected to Vdd (most positive voltage in circuit) for all PMOS devices
•
Operation: – If Vin is down (0 volts), NMOS is OFF and PMOS is ON pulling Vout to Vdd (high = 1) – If Vin is up (at Vdd), NMOS is ON hard and PMOS is OFF pulling Vout low to Gnd (“0”)
Inverter Symbol
– With Vin at 0 or Vdd, no dc current flows in inverter
CMOS Inverter A 0 1
VDD
Y
A A
Y
Y
GND
CMOS Inverter A 0
Y
1
0
VDD OFF A=1
Y=0
ON A
Y
GND
CMOS Inverter A
Y
0
1
1
0
VDD ON A=0
Y=1
OFF A
Y
GND
Series connected MOSFETS
Parallel Connected MOSFETS
Series and Parallel
nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel : either can be ON
a
a 0
g1 g2
(a)
g2
b
OFF
OFF
OFF
ON
a
a
a
a
0
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
(c)
a
b
1 b
1
b
g2
0 b
1
a
g1
1
1
0
(b)
g2
1
0
b
g1
a
b
a g1
a
0
0 b
(d)
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
Pull-up / Pull-down Model • Typical CMOS gate can be viewed as
consisting of two parts – pull-up network and pull-down network VDD A B C
Pull-up output
A B C
Pulldown GND
Pull-up / Pull-down Model • High level inputs to the PDN cause
switches to close • If there is a closed switch path thru PDN, then output is low • Low level inputs to the PUN cause switches to close • If there is a closed switch path thru PUN, then output is high
CMOS NAND Gate A 0 0 1 1
B 0 1 0 1
Y
Y A B
CMOS NAND Gate A
B
0
0
0 1 1
1 0 1
Y ON
1
ON Y=1
A=0 B=0
OFF OFF
CMOS NAND Gate A 0
B 0
Y 1
0
1
1
1 1
0 1
OFF
ON Y=1
A=0 B=1
OFF ON
CMOS NAND Gate A 0 0
B 0 1
Y 1 1
1
0
1
1
1
ON
OFF Y=1
A=1 B=0
ON OFF
CMOS NAND Gate A 0 0 1
B 0 1 0
Y 1 1 1
1
1
0
OFF
OFF Y=0
A=1 B=1
ON ON
CMOS NOR Gate A 0 0 1 1
B 0 1 0 1
Y 1 0 0 0
A B Y
3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0
3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 Y A B C
Logic Identities
Logic Analysis -Inverter
Logic Analysis –NAND Gate
Logic Analysis –NOR Gate
Pull-up / Pull-down Model A A and ( B or C) B
C
Since hign level signals on the inputs cause the PDN to close switches, we get a Boolean expression for the input which creates a closed path thru PDN
If a closed path exists in PDN, then the output is pulled low. Thus the logic function realized is the complement (inverted) version of the Boolean expression. output A B C
Pulldown GND
not (A and ( B or C))
Pull-up / Pull-down Model What happens when the Boolean expression is false? Vdd
Since there is no path thru PDN, the output could float. In order to make the output high, the PUN must have a path which connects VDD to the output. Observe: take the expression for PDN and use DeMorgans Law to write it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of the PUN In this case: not A or ( not B and not C)
B
A
C
Example Gate: COMPLEX CMOS GATE
OUT = D + A (B+C) •
Example Gate: COMPLEX CMOS GATE VDD B A C D
OUT = D + A (B+C) •
A D B
C
VDD B A C D
OUT = D + A (B+C) •
A D B
C
Examples of pull-down networks
Examples of pull-up networks
VDD PMOSs A B
Out
C NMOSs NMOSs GND
B
A
C
E
D
Vcc
F
Gnd
B
Vcc C
E
A
C
E
D Vcc
D F A
B
F Gnd
A
B
C
D
E
Gnd
Stick Diagram, Interconnected
83
Two Versions of C (A +B) •
A
C
B
A
B
C
VDD
VDD X
GND
Line of diffusion layout – abutting source-drain connections Note crossover eliminated by A B C ordering
X
GND
• Example: x y + x z + x v = x (y + z + v) • 5 operations: • 1 AND, 2 OR • # txs = ___?
3 operations: 3 AND, 2 OR # txs = ___?
Construct a CMOS logic gate to implement the function: F = a • (b + c)
14 transistors (cascaded gates)
Construct a CMOS logic gate to implement the function: F = a • (b + c)
Complex gates in CMOS logic • A complex logic gate is one that implements a function
• • • •
•
that can provide the basic NOT, AND and OR operation but integrates them into a single circuit. CMOS is ideally suited for creating gates that have logic equations by exhibiting the following, 1) AND-OR-INVERT - AOI form 2) OR-AND-INVERT - OAI form An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is equivalent to a complemented POS structure. In CMOS, output always produces NOT operation acting on input variable
AOI Logic Function (OR) Design of XOR gate using CMOS logic. • AND-OR-INVERT logic function(AOI)
implements operation in the order AND,OR,NOT. For example , • Let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D))
The AOI logic gate implementation for Y
CMOS implementation for Y • Step 1: Draw A.B (AND) function first by connecting 2 nMOS transistors in series.
Step 2: Draw C.D implementation, by using 2 nMOS transistors in series.
Step 3:
Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw parallel
connection. So, A.B series connected in parallel with C.D as shown in figure.
Step 4: Draw pMOS connection, I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in parallel. II. In nMOS C,D connected in series. So, in pMOS side, C.D should be connected inparallel. III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side, A.B and C.D networks should be connected in series. IV. In pMOS multiplication should be drawn in parallel, then addition should be drawn in series as shown in figure.
Step 5: Take output at the point in between nMOS and pMOS networks.
CMOS implementation for Y
Example: x = ab+cd
OAI Logic Function (OR) Design of XNOR gate using CMOS logic. • OR-AND-INVERT logic function(AOI)
implements operation in the order OR,AND,NOT. For example , • Let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))
CMOS implementation for Y
OAI22 Logic Graph A
C
B
D X = (A+B)•(C+D)
C
D
A
B
A B C D
Structured Logic Design (1/4)
CMOS logic gates are intrinsically inverting »
Output always produces a NOT operation acting on the input variables
Figure 2.42 Origin of the inverting characteristic of CMOS gates
Structured Logic Design (2/4)
(a) Series-connected nFETs
(b) Parallel-connected nFETs Figure 2.43 nFET logic formation
Figure 2.44 nFET AOI circuit
Figure 2.45 nFET OAI circuit
Structured Logic Design (3/4)
(a) Parallel-connected pFETs
(a) pFET AOI circuit
(b) pFET OAI circuit (b) Series-connected pFETs Figure 2.46 pFET logic formation
Figure 2.47 pFET arrays for AOI and OAI gates
Structured Logic Design (4/4)
(a) AOI circuit
(b) OAI circuit
Figure 2.48 Complete CMOS AOI and OAI circuits
Bubble Pushing
(a) NAND - OR (a) Parallel-connected pFETs
(b) NOR - AND Figure 2.52 Bubble pushing using DeMorgan rules (b) Series-connected pFETs Figure 2.51 Assert-low models for pFETs
XOR and XNOR gates
XOR and XNOR Gates
An important example of using an AOI circuit is constructing Exclusive-OR (XOR) and Exclusive-NOR circuits a
b
a b a b
(2.71)
a
b
a b a b
(2.72)
a
b
(a
b)
a b a b
a
b
a b a b
(2.73) (2.74)
(a) Exclusive-OR
(b) Exclusive-NOR
Figure 2.57 AOI XOR and XNOR gates
(a) AOI22
(b) AOI321
(c) AOI221
Figure 2.58 General naming convention Figure 2.56 XOR
A
B
C
D
E Vcc
F
Gnd
logic cascade in cmos
Half-Adder Logic Equations Truth Table
x 0 0 1 1
y 0 1 0 1
C 0 0 0 1
S 0 1 1 0
C = x • y S = x y
Schematic
Full Adder •
Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sumbit S and a carry out C-out bit.
Sum S
X XY
0
Full Adder Truth Table Outputs
I nputs
X 0 0 0 0 1 1 1 1
Y 0 0 1 1 0 0 1 1
C-in 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
00
C-in
C-out 0 0 0 1 0 1 1 1
S(X,Y, C-in) = (1,2,4,7) C-out(x, y, C-in) = (3,5,6,7)
0
01
11 6
2
10 4
1 3
1
1
1 5
7
1
C-in
1 Y
S = X’Y’(C -in) + XY’(C -in)’ + XY’(C -in)’ + XY(C -in)
S= X
Y
(C-in)
Carry C-out
X
XY
00
C-in
0
0
11 6
2
10 4
1 1
1
01
3
5
7
1
1
1
C-in
Y
C-out = XY +X(C-in) +Y(C-in)
Addition of Binary Numbers Full Adder. The full adder is the fundamental building block of most arithmetic circuits:
ai bi
Full Adder
Cout
Cin
si The sum and carry outputs are described as:
si
ci
1
aibi ci
ai bi ci
aibi ci
ai bi ci
aibi ci
ai bi ci
aibi ci
ai bi ci
ai bi
ai ci
bi ci
Full Adder Circuit Using AND-OR X’
X
Y’
X’
X
C-in X’
Y
Y
Sum S
X Y
C-in C-in’
C-in
X’YC -in’
C-in’
Y’
Y
X’Y’C-in
C-in’
XY’C-in’
X Y C-in’
X
Y
X
XYC-in
XY
Y
C-out
Full Adder
C-in
X
XC-in
C-in Y
S
C-in
YC-in
C-out
Cont..
Addition of Binary Numbers Inputs
Outputs
ci
ai
bi
si
ci+1
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1 Generate
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Propagate
Propagate Generate
PGK
For a full adder, define what happens to carries »
Generate: Cout =1 independent of C
»
Propagate: Cout =C
»
G =A • B P =A
B
Kill: Cout =0 independent of C
K =~A • ~B
Full-Adder Implementation Full Adder operations is defined by equations:
si
ci
1
aibi ci
aibi ci
aibi ci
aibi ci
ai
aibi ci aibi ci aibi g i pi ci
Carry-Propagate: pi and Carry-Generate
g i
ai
bi
ci
pi
ci
ai bi
bi
ai bi cout
cin
One-bit adder could be implemented as shown
si
High-Speed Addition ci ai
g i
1
g i
pi ci
bi
pi
ai bi 0
cout
si
pi
ci
cin
s 1
One-bit adder could be implemented more efficiently because MUX is faster
si
ai
bi
Multiplexers
2:1 multiplexer chooses between two inputs
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
S
Y
D0
0 Y
D1
1
Multiplexers
2:1 multiplexer chooses between two inputs
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
S D0
0 Y
D1
1
Gate-Level Mux Design
Y
SD1 SD0 (too many transistors)
How many transistors are needed?
Gate-Level Mux Design
Y
SD1 SD0 (too many transistors)
How many transistors are needed? 20
D1 S D0
D1 S D0
Y
4
2 4
2
4
2
2
Y
Inverting Mux
Inverting multiplexer »
Use compound AOI22
»
Or pair of tristate inverters
»
Essentially the same thing
Noninverting multiplexer adds an inverter
D0 S
S
S
D1 Y
S
D0
0 Y
S D1
1
Tristate Inverter
Tristate inverter produces restored output »
Violates conduction complement rule
»
Because we want a Z output
A EN Y EN
Tristate Inverter
Tristate inverter produces restored output »
Violates conduction complement rule
»
Because we want a Z output
A
A
A EN Y
Y
Y
EN = 0 Y = 'Z'
EN = 1 Y=A
EN
D0
D1
S
S
S Y
S
D0
0 Y
S D1
1
Inverting Mux
Inverting multiplexer »
Use compound AOI22
»
Or pair of tristate inverters
»
Essentially the same thing
Noninverting multiplexer adds an inverter D0 S
S D1
D0
D1
S
S
Y S
S
S Y
S
D0
0 Y
S D1
1
Complimentary Static CMOS Full Adder V DD V DD A
C i
A
B
B A
B B
C i
V DD
A X
C i
C i S
A C i
A
B
B
V DD A
B
C o
28 Transistors
C i
A
B
A Better Structure: The Mirror Adder VDD VDD A
B
A
VDD A
B
B
Ci
B
Kill "0"-Propagate
A
Ci
Co
Ci
S Ci
A
"1"-Propagate
Generate A
B
B
A
B
Ci
A B
24 transistors and 2 inverter Total 24+4 =28 Transistors
Mirror Adder Stick Diagram V DD
A
B
C i
B
A C i
C o
C i
C o S GND
139
A
B
OAI/AOI duality A B
A
Vdd
OUT
B
C
C
C
B
A Out B
A
C Gnd
OUT
Review: Construction of PDN • NMOS devices in series implement a NAND function A•B A B
• NMOS devices in parallel implement a NOR function A+B A
B
• Scale both W and L • – no effective change in W/L • – increases gate capacitance
• Series Transistors
• – increases effective L
• Parallel
• increases effective W
Transistors
Analysis of CMOS gates
Represent “on” transistors as resistors
1 W
R
1
W
R
1
W
R
• Transistors in series → resistances in series • Effective resistance = 2R • Effective width = ½ W
Analysis of CMOS gates, cont • Represent “on” transistors as resistors W W
0
W
R
R
0 0
• Transistors in parallel → resistances in parallel • Effective resistance = ½ R • Effective width = 2W
R
CMOS gate design
Designing a CMOS gate:
Find pulldown NMOS network from logic function or by inspection Find pullup PMOS network - By inspection - Using logic function
- Using dual network approach Size transistors using equivalent inverter - Find worst-case pullup and pulldown paths - Size to meet rise/fall or threshold requirements
Equivalent inverter: effective width to length ratios (model I) Parallel combination
For the NOR gate the effective width of the drivers transistors
doubles. That means the effective aspect ratio is increased.
Series combination
For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased. .
Exercise: Design and compare two input NAND and NOR gates
Find W/L relationship between NMOS and PMOS transistors
Assume K'n=2K'p
NAND gate NOR gate
Cmos inverter : summary
1.
2. 3.
4. F or an inverter the (W/L) of the NMOS is (W/L)n and that for the PMOS is (W/L)p for Fall time = Rise Time. For the worst case design of the NAND gate, you should set the W/L ratio of the NMOS transistors to 2*(W/L)n (i.e. twice that of the inverter) and that of the PMOS to (W/L)p (i.e. equal to that of the inverter)
Transistor sizing CMOS NOR
CMOS NAND Gates A
B
A
A • B
B
Adding transistors in series (without sizing) slows down the circuit
Optimized NAND Gates W/L ratio of PMos and NMos transistors
Size Devices for the Worst Case
Series transistors: Increase Increase W to reduce Reff .
Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.
Transistor Sizing Without Velocity Saturation
Assumption: Equal rise delay and an d fall delay Consideration: Effective Resistance
Trade-Off
Increase W to reduce the effective Resistance for the pull down network. The area is increased.
i input CMOS NAND
i WP /LP =2.5 WN /LN
Two input CMOS NAND
2 WP /LP =2.5 WN /LN
i input CMOS NOR
WP /LP =2.5 i WN /LN
TWO input CMOS NOR
WP /LP =2.5 (2) WN /LN = 5 WN /LN
Transistor Sizing Without Velocity Saturation
Total area of the NMOS and PMOS channels is seen as L=2u w=4u ratio 2.5 times CMOS NAND 2 input gate 2( 8u)(2u) + 2 (10u)(2u) = 72um2 CMOS INVERTER gate ( 4u)(2u) + (10u)(2u) = 28um2
WN LN + WP LP
CMOS NOR 2 input gate 2( 4u)(2u) + 2 (20u)(2u) = 96um2
Example
Total area of the NMOS and PMOS channels is seen as
WN LN + WP LP
L=2u w=4u ratio 2.5 time
CMOS NAND gate -2 input gate
2( 8u)(2u) + 2 (10u)(2u) = 72um2
CMOS NOR 2 input gate 2( 4u)(2u) + 2 (20u)(2u) = 96um2
Cmos inverter: Charging
Cmos inverter : Discharging
A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance of the transistor The latter is achieved by increasing the W/L ratio of the device
Symmetrical propagation delay
Input Pattern Effects on Delay-I
Rp A
Rp
Delay is dependent on the pattern of inputs
Low to high transition
B Rn
- delay is 0.69 Rp/2 CL since two p-resistors are on in parallel
CL
A Rn
both inputs go low
one input goes low - delay is 0.69 Rp CL
Cint
B
High to low transition
both inputs go high - delay is 0.69 2Rn CL
Adding transistors in series (without sizing) slows down the circuit
Delay Dependence on Input Patterns-II The reason for difference in low to high transition is due to internal node capacitance and high to low is Due to initial state of the internal nodes .
2-input NAND with NMOS = 0.5 m/0.25 m PMOS = 0.75 m/0.25 m CL = 10 fF
3
A=B=1
2.5
0
2
A=1
1.5
V , e 1 g a t l o 0.5 V
0, B=1
A=1, B=1 0
Rp A
Rp B
0 0 -0.5
100
200
300
400
Rn
A time, psec Conclusions: Estimates of delay can be fairly R n complex – have to consider internal node B capacitances and the data patterns
CL
Cint
Input Data
Delay
Pattern
(psec)
A=B=0 1
69
A=1, B=0 1
62
A= 0 1, B=1
50
A=B=1 0
35
A=1, B=1 0
76
A= 1 0, B=1
57
Transistor Sizing a Complex CMOS Gate
A
B
8 6
C
8 6
4 3
D
4 6 OUT = D + A • (B + C)
A D
2
1 B
2C
2
Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc.
