Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
solutions for chapter 2 a) The truth table for a + b ⋅ c is
s ol ut io n 2 .1
a
b
c
a+b⋅c
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 0 1 1 1 1
b) The truth table for x ⊕ y ⊕ z is x
y
z
x ⊕y ⊕z
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
c) The truth table for ( a + b ) ⋅ ( c + d ) is a 0 0 0 0 0 0 0
b 0 0 0 0 1 1 1
c 0 0 1 1 0 0 1
d 0 1 0 1 0 1 0
a+b 0 0 0 0 1 1 1
c + d 1 0 0 0 1 0 0
( a + b ) ⋅ ( c + d )
0 0 0 0 1 0 0
5
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
6
solutions for chapter 2
a 0 1 1 1 1 1 1 1 1
b 1 0 0 0 0 1 1 1 1
s ol ut io n 2 .2
c 1 0 0 1 1 0 0 1 1
d 1 0 1 0 1 0 1 0 1
a+b 1 1 1 1 1 1 1 1 1
c + d 0 1 0 0 0 1 0 0 0
0 1 0 0 0 1 0 0 0
a) The schematic diagram for a + b ⋅ c is: a b c
b) The schematic diagram for x ⊕ y ⊕ z is: x
y z
c) The schematic diagram for ( a + b ) ⋅ ( c + d ) is: a b c d s ol ut io n 2 .3
( a + b ) ⋅ ( c + d )
f
=
a⋅b⋅c+a⋅b⋅c+a⋅b⋅c
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
7
s o lu t i on s f o r c ha pt e r 2
The sum-of-minterms equation can be implement-
s ol ut io n 2 .4
ed directly as shown below left. A simplified equation, f can be implemented as shown below right.
=
a ⋅ b ⋅ c + b ⋅ c,
a b
a b c
c
f
The truth table is
s ol ut io n 2 .5
x
y
z
f
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 1 1 0 0 1
The Boolean equation derived directly from the
s ol ut io n 2 .6
circuit is: f
=
x ⋅ y + (y ⊕ z)
The Boolean equation in the form of a sum of minterms is: f
=
x⋅y⋅z+x⋅y⋅z+x⋅y⋅z+x⋅y⋅z The truth table is
s ol ut io n 2 .7
a
b
c
M
0 0 0
0 0 1
0 1 0
0 0 0
f
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
8
solutions for chapter 2
a
b
c
M
0 1 1 1 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
a) The truth table for x ⋅ ( y ⋅ z ) and x ⋅ y + x ⋅ z is shown below. Since the values in each row for the two expressions are the same, the expressions are equivalent. s ol ut io n 2 .8
x 0 0 0 0 1 1 1 1
y 0 0 1 1 0 0 1 1
z 0 1 0 1 0 1 0 1
x ⋅ (y ⋅ z ) 0 0 0 0 1 1 1 0
x⋅y+x⋅z 0 0 0 0 1 1 1 0
b) The truth table for x ⊕ y and x ⊕ y is shown below. Since the values in each row for the two expressions are the same, the expressions are equivalent. x 0 0 1 1
y 0 1 0 1
x⊕y 1 0 0 1
x⊕y 1 0 0 1
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
One arrangement for the buffer tree is:
s ol ut io n 2 .9
A reduced truth table is:
s ol ut io n 2 .1 0
x 0 0 1
y 0 1 –
z – – –
f 1 0 1
The augmented truth table is:
s ol ut io n 2 .1 1
a
b
c
f
f0
f 1
f 2
f 3
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 – – 1 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 0
0 1 0 0 1 1 1 0
0 1 0 1 1 1 1 0
9
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
10
solutions for chapter 2
In the following, the top two circuits are equivalent, and the bottom two circuits are equivalent: s ol ut io n 2 .1 2
x x
y
y
x
z z
x x
y
y
x
z z
The identity law 2.13 can be proven as follows:
s ol ut io n 2 .1 3
x+1
= x+x+x
by complement law 2.9
= (x + x) ⋅ 1 + x
by identity law 2.8
= (x + x) ⋅ (x + x) + x
by complement law 2.9
= x + ( x ⋅ x) + x = x+0+x
by distributive law 2.5 by complement law 2.10
= x+x
by identity law 2.7
=1
by complement law 2.9
Law 2.14 follows, since it is the dual of law 2.13. The absorption law 2.15 can be proven as follows: x + ( x ⋅ y)
= x ⋅ 1 + (x ⋅ y)
by identity law 2.8
= x ⋅ (1 + y) = x ⋅ (y + 1) = ... = x⋅1 =x
by distributive law 2.6 by commutative law 2.1 using same steps as proof of identity law 2.13 by identity law 2.8
Law 2.16 follows, since it is the dual of law 2.15. s ol ut io n 2 .1 4
(w + y) ⋅ (x + z)
The transformation is: = (w ⋅ y) ⋅ (x + z) = w⋅y⋅x+w⋅y⋅z
DeMorgan Law Distributive Law
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
s ol ut io n 2 .1 5
One possible proof is:
a ⋅b⋅ c +a ⋅b ⋅c +a ⋅b ⋅c +a ⋅b ⋅c =
a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c
Idempotence twice
=
a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c+a⋅b⋅c
Commutative
=
a⋅b⋅c+a⋅b⋅c+b⋅a⋅c+b⋅a⋅c+c⋅a⋅b+c⋅a⋅b
Commutative
=
(a + a) ⋅ b ⋅ c + (b + b) ⋅ a ⋅ c + ( c + c) ⋅ a ⋅ b
=
1⋅b⋅c+1⋅a⋅c+1⋅a⋅b
=
b⋅c+a⋅c+a⋅b
Distributive Complement Identity Commutative
a⋅b+b⋅c+a⋅c s ol ut io n 2 .1 6
a) The module definition is:
module exercise_2_16_a ( output m, input a, b, c ); assign m = a & b | b & c | a & c; endmodule
b) The module definition is: module exercise_2_16_b ( output s, input x, y, z ); assign s = ~(x | y) & (x | ~z); endmodule
c) The module definition is: module exercise_2_16_c ( output y, input a, b, c ); assign y = (a ^ b) & (a | c); endmodule
Since there are seven values to be represented, a minimal-length code has log 2 7 = 3 bits. One possible code is ons ol ut io n 2 .1 7
hook: (0, 0, 0), dial-tone: (0, 0, 1), dialing: (0, 1, 0), busy: (0, 1, 1), connected: (1, 0, 0), disconnected: (1, 0, 1), ringing: (1, 1, 0).
11
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12
solutions for chapter 2
s ol ut io n 2 .1 8
Given the code bits ( p 2 , p 1 , p 0 ), the equation
can be expressed as a sum-of-minterms by inspecting the code words for the off-hook states: off-hook
=
p 2 ⋅ p 1 ⋅ p 0 + p2 ⋅ p1 ⋅ p0 + p2 ⋅ p1 ⋅ p0 + p2 ⋅ p1 ⋅ p0 + p 2 ⋅ p 1 ⋅ p 0
Since there are seven values to be represented, a one-hot code has seven bits. One possible code is: s ol ut io n 2 .1 9
on-hook: (1, 0, 0, 0, 0, 0, 0) dial-tone: (0, 1, 0, 0, 0, 0, 0) dialing: (0, 0, 1, 0, 0, 0, 0) busy: (0, 0, 0, 1, 0, 0, 0) connected: (0, 0, 0, 0, 1, 0, 0) disconnected: (0, 0, 0, 0, 0, 1, 0) ringing: (0, 0, 0, 0, 0, 0, 1) s ol ut io n 2 .2 0
The module definition is:
module hook_detector ( output input [2:0] assign off_hook = ~p[2] & ~p[1] & ~p[2] & p[1] & ~p[2] & p[1] & p[2] & ~p[1] & p[2] & ~p[1] & endmodule
off_hook, p ); p[0] | ~p[0] | p[0] | ~p[0] | p[0];
The equations for green and yellow are unchanged, since they only activate the respective lights on valid one-hot code words. The equation for red must be revised to include only the first term that activates the red light on the valid one-hot code word for red. The equations are: s ol ut io n 2 .2 1
green = s_red · s_yellow · s_green yellow = s_red · s_yellow · s_green red = s_red · s_yellow · s_green Since odd parity is the logical negation of even parity, we can form the parity trees for odd parity by negating the output of the parity trees for even parity. We can do this by substituting an s ol ut io n 2 .2 2
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
13
s o lu t i on s f o r c ha pt e r 2
XNOR gate for the XOR gate that produces the output of the tree. The odd-parity generator (left) and checker (right) are: a0 a1 a2 a3 a4 a5 a6 a7
p
a0 a1 a2 a3 a4 a5 a6 a7 p
Suppose we have a code word 00000000. Augmenting this with an even parity bit gives 000000000 and with an odd parity bit gives 00000001. (The parity bit is the rightmost bit in both cases.) Now suppose the leftmost two bits of each augmented code word are flipped. The corrupted code words are 110000000 and 110000001, which have even and odd parity, respectively, as expected for uncorrupted code words. Thus, the errors are not detected. s ol ut io n 2 .2 3
For an encoded 3-bit input signal, ( i2, i1, i0), the Boolean equations for the decoded outputs are: s ol ut io n 2 .2 4
s ol ut io n 2 .2 5
z1
=
i2 ⋅ i1 ⋅ i0
z2
=
i2 ⋅ i1 ⋅ i0
z3
=
i2 ⋅ i1 ⋅ i0
z4
=
i2 ⋅ i1 ⋅ i0
z5
=
i2 ⋅ i1 ⋅ i0
z6
=
i2 ⋅ i1 ⋅ i0
z7
=
i2 ⋅ i1 ⋅ i0
z8
=
i2 ⋅ i1 ⋅ i0
The module definition is:
module alarm_decoder ( output input assign z[1] = ~i[2] & ~i[1] assign z[2] = ~i[2] & ~i[1] assign z[3] = ~i[2] & i[1]
[1:8] z, [2:0] i ); & ~i[0]; & i[0]; & ~i[0];
error
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
14
solutions for chapter 2
assign z[4] assign z[5] assign z[6] assign z[7] assign z[8] endmodule
= ~i[2] & i[1] & i[0]; = i[2] & ~i[1] & ~i[0]; = i[2] & ~i[1] & i[0]; = i[2] & i[1] & ~i[0]; = i[2] & i[1] & i[0];
The Boolean equations to produce a 3-bit encod-
s ol ut io n 2 .2 6
ed signal (c2, c1, c0) are: c2
yellow ⋅ light_cyan ⋅ light_magenta
=
c1
=
c0
cyan ⋅ magenta ⋅ light_magenta =
black ⋅ magenta ⋅ light_cyan
For pairs of inputs both being 1, the resulting code words are: black and cyan: (0, 1, 1) = magenta black and magenta: (0, 1, 1) = magenta black and yellow: (1, 0, 1) = light_cyan black and light_cyan: (1, 0, 1) = light_cyan black and light_magenta: (1, 1, 1) = illegal code word cyan and magenta: (0, 1, 1) = magenta cyan and yellow: (1, 1, 0) = light_magenta cyan and light_cyan: (1, 1, 1) = illegal code word cyan and light_magenta: (1, 1, 0) = light_magenta magenta and yellow: (1, 1, 1) = illegal code word magenta and light_cyan: (1, 1, 1) = illegal code word magenta and light_magenta: (1, 1, 1) = illegal code word yellow and light_cyan: (1, 0, 1) = light_cyan yellow and light_magenta: (1, 1, 0) = light_magenta light_cyan and light_magenta: (1, 1, 1) = illegal code word Since no priority ordering is specified, we assume the following order, from highest to lowest priority: black, cyan, magenta, yellow, light cyan, light magenta. For the inputs, color[1] is black, color[2] is cyan, etc. s ol ut io n 2 .2 7
module ink_encoder (output [2:0] encoded_color, output valid, input [1:6] color); assign encoded_color = color[1] color[2] color[3] color[4] color[5]
? ? ? ? ?
3'b001 3'b010 3'b011 3'b100 3'b101
: : : : :
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
color[6] ? 3'b110 : 3'b000;
assign valid = color[1] | color[2] | color[3] | color[4] | color[5] | color[6]; endmodule
For a 4-bit BCD input signal, ( i3, i2, i1, i0), the Boolean equations for the decoded outputs are: s ol ut io n 2 .2 8
y0
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y1
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y2
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y3
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y4
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y5
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y6
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y7
=
i3 ⋅ i2 ⋅ i1 ⋅ i0
y8
=
i3 ⋅ i0
y9
=
i3 ⋅ i0
We assume here that invalid input code words cannot occur, and so we have simplified the equations for y8 and y9. A circuit for the decoder is:
15
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
16
solutions for chapter 2
i0 i1 i2 i3
y0 y1 y2 y3 y4 y5 y6 y7 y8 y9
s ol ut io n 2 .2 9
The module definition is:
module bcd_decoder ( output [0:9] y, input [3:0] i ); assign assign assign assign assign assign assign assign assign assign endmodule
y[0] y[1] y[2] y[3] y[4] y[5] y[6] y[7] y[8] y[9]
= = = = = = = = = =
~i[3] ~i[3] ~i[3] ~i[3] ~i[3] ~i[3] ~i[3] ~i[3] i[3] i[3]
& & & & & & & &
~i[2] ~i[2] ~i[2] ~i[2] i[2] i[2] i[2] i[2]
& & & & & & & &
~i[1] ~i[1] i[1] i[1] ~i[1] ~i[1] i[1] i[1]
& & & & & & & & & &
~i[0]; i[0]; ~i[0]; i[0]; ~i[0]; i[0]; ~i[0]; i[0]; ~i[0]; i[0];
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
For a multiplexer with data inputs a0 and a1, select input s, and data output y, the Boolean equation is: s ol ut io n 2 .3 0
y
=
s ⋅ a0 + s ⋅ a1
A circuit to implement a multiplexer is: a0 y
a1 s
s ol ut io n 2 .3 1
The circuit is
x y a b c enable sel
s ol ut io n 2 .3 2
0 1
The module definition is:
module expression_mux ( output z, input enable, sel, a, b, c, x, y ); assign z = enable & ~sel ? a & (b | ~c) : x ^ y; endmodule
17
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
18
solutions for chapter 2
s ol ut io n 2 .3 3
The circuit is: a0(0) a1(0) a2(0) a3(0)
0 1 2 3
z(0)
0 1 2 3
z(1)
0 1 2 3
z(2)
a0(1) a1(1) a2(1) a3(1) a0(2) a1(2) a2(2) a3(2) sel(1...0)
s ol ut io n 2 .3 4
The module definition is:
module mux_3bit_4_to_1 ( output reg [0:2] z, input [0:2] a0, a1, a2, a3, input [1:0] sel ); always @* case (sel) 2'b00: z 2'b01: z 2'b10: z 2'b11: z endcase endmodule
= = = =
a0; a1; a2; a3;
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
s ol ut io n 2 .3 5
The revised circuit is:
>30°C
vat 0
>25°C
low level 0
buzzer
1
>30°C +V
vat 1
select vat 1
>25°C
select vat 0 low level
s ol ut io n 2 .3 6
The revised structural model is:
module vat_buzzer_n_struct ( output buzzer_n, input above_25_0, above_30_0, low_level_0_n, input above_25_1, above_30_1, low_level_1_n, input select_vat_1 ); wire low_level_0, below_25_0, temp_bad_0, wake_up_0; wire low_level_1, below_25_1, temp_bad_1, wake_up_1; wire buzzer; // components for vat 0 not inv_0a (low_level_0, low_level_0_n); not inv_0b (below_25_0, above_25_0); or or_0a (temp_bad_0, above_30_0, below_25_0); or or_0b (wake_up_0, temp_bad_0, low_level_0); // components for vat 1 not inv_1a (low_level_1, low_level_1_n); not inv_1b (below_25_1, above_25_1); or or_1a (temp_bad_1, above_30_1, below_25_1); or or_1b (wake_up_1, temp_bad_1, low_level_1); mux2 select_mux (buzzer, select_vat_1, wake_up_0, wake_up_1);
19
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
20
solutions for chapter 2
not
inv_out
(buzzer_n, buzzer);
endmodule
The revised behavioral model is: module vat_buzzer_n_behavior ( output buzzer_n, input above_25_0, above_30_0, low_level_0_n, input above_25_1, above_30_1, low_level_1_n, input select_vat_1 ); assign buzzer_n = ~(select_vat_1 ? ~low_level_1_n | (above_30_1 | ~above_25_1) : ~low_level_0_n | (above_30_0 | ~above_25_0)); endmodule s ol ut io n 2 .3 7
A testbench for the structural vat buzzer design
in Example 1.5 is: `timescale 1ms/1ms module vat_buzzer_testbench; wire buzzer; reg above_25_0, above_30_0, low_level_0, above_25_1, above_30_1, low_level_1, select_vat_1;
task apply_test ( input above_25_0_test, above_30_0_test, low_level_0_test, above_25_1_test, above_30_1_test, low_level_1_test, select_vat_1_test ); begin above_25_0 = above_25_0_test; above_30_0 = above_30_0_test; low_level_0 = low_level_0_test; above_25_1 = above_25_1_test; above_30_1 = above_30_1_test; low_level_1 = low_level_1_test; select_vat_1 = select_vat_1_test; #1000; end endtask
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher. s o lu t i on s f o r c ha pt e r 2
vat_buzzer_struct duv ( .buzzer(buzzer), .above_25_0(above_25_0), .above_30_0(above_30_0), .low_level_0(low_level_0), .above_25_1(above_25_1), .above_30_1(above_30_1), .low_level_1(low_level_1), .select_vat_1(select_vat_1) );
initial begin // normal operation: buzzer should be 0 apply_test(1, 0, 0, 1, 0, 0, 0); apply_test(1, 0, 0, 1, 1, 0, 0); apply_test(1, 0, 0, 0, 0, 1, 0); apply_test(1, 0, 0, 1, 0, 0, 1); apply_test(1, 1, 0, 1, 0, 0, 1); apply_test(0, 0, 1, 1, 0, 0, 1); // alarm operation: buzzer should be 1 apply_test(1, 1, 0, 1, 0, 0, 0); apply_test(0, 0, 0, 1, 0, 0, 0); apply_test(1, 0, 1, 1, 0, 0, 0); apply_test(1, 0, 0, 1, 1, 0, 1); apply_test(1, 0, 0, 0, 0, 0, 1); apply_test(1, 0, 0, 1, 0, 1, 1); // sensor fault operation: buzzer should be 1 apply_test(0, 1, 0, 1, 0, 0, 0); apply_test(1, 0, 0, 0, 1, 0, 1); $finish; end
always @( above_25_0, above_30_0, low_level_0, above_25_1, above_30_1, low_level_1, select_vat_1 ) begin #10 if (!select_vat_1) if (above_25_0 & !above_30_0 & !low_level_0) begin if (buzzer) $display("Error: buzzer on for vat 0"); end else begin if (!buzzer) $display("Error: buzzer off for vat 0"); end else if (above_25_1 & !above_30_1 & !low_level_1) begin if (buzzer)
21
Peter J. Ashenden, Digital Design: An Embedded Systems Approach Using Verilog — 21 September 2007. © 2007 by Elsevier Inc. Reproduced with permission from the publisher.
22
solutions for chapter 2
$display("Error: buzzer on for vat 1"); end else if (!buzzer) begin $display("Error: buzzer off for vat 1"); end
end endmodule
The testbench for the behavioral design in Example 1.6 is the same, except that the module name “ vat_buzzer_struct ” is replaced by “vat_buzzer_behavior” in the instantiation of the design under verification.
