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10/7/2010
EBB 323 Semiconductor Testing (wafer sorting)
Dr. Pung Pung Swee Swee Yong Yong
School of Materials & Mineral Resources Engineering Univer Universit sitii Sains Sains Malays Malaysia ia
Topics Outcome
At the end of the lecture, student will be able:
and test structures
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Introduction After wafer fabrication, each of the
die need to be electrically tested for . (i) Mechanism for assessing IC yield (ii) Indicator of product performance (iii) Quality Quality Assurance Assurance – checked at various stages of manufacturing through in-line measurement on
After wafer fabrication,
Special parametric test dies are placed at a number of sites on the wafer. rocess on ro on ors (PCMs)
In product wafers
In die sites or
In the scribe lines between dies.
Configuration of products and PCMs on a typical semiconductor wafer.
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PCMs can be
Single transistors
Single lines of conducting materials
capac pac ors
Interconnect monitors
Able to inferred by the presence of short circuits or open circuits using simple resistance measurement.
Purpose of PCMs To assess impact of the presence of defects on semiconductor wafer.
Configuration of products and PCMs on a typical semiconductor wafer.
testing sequence: (i) Screen Screening ing test test on proc process ess contro controll module module (PCM) (ii) (ii) Functi Functiona onall test test on each each die die
Screening test
DC tests are performed performed to verify verify that basic process process parameters fall within acceptable limits.
Very fine needle probes are contacted with wit h the pads on the test die (PCM).
If the device parameters are within specification, functional testing of each die begins
Functional testing (Final testing)
To ensure all products perform to the specification for which they were designed.
Automated test equipment (ATE)
easu easure re + reco recorr
3 major functions:
e resu resu s
Input pattern generation
Pattern application
Output response detection
Expression of test results
Shmoo Shmoo Plot Plot
Cell map.
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Example of two-dimensional voltage shmoo plot for a bipolar IC.
Cell map showing example of failure patterns and defect types.
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After wafer sorting,
defective dies are marked with a drop of ink
when the dies are separated from the wafer, any die with an ink spot is discarded
