CHAPTER 1
INTRODUCTION 1.1 AIM The main goal of this project is to design high speed area efficient brent kung adder using hdl.
1.2 MOTIVATION Ripple carry adder is the motivation of brent kung adder. In the 4 bit ripple ripple carry adder has 4 full adders Each full adder generate a carry, the carry of first full adder act as a input to the next full adder Here time delay takes place. For avoiding this time delay we are using “high speed area efficient brent kung adder using hdl” .
1.3 OBJECTIVE The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for n-bit RCA and n-bit Brent – Kung, Kogge – Stone, Ladner Fischer, and Han – Carlson Carlson adders. We – Kung, – Fischer, further show that the Brent – Kung adder has lower delay than the best existing adder designs as – Kung well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent – Kung adder is fairly well-suited to changes in time-related parameters as well – Kung as temperature. Detailed simulations using QCA Designer are presented. Microprocessors and application specific integrated circuits are largely based on the complementary metal oxide semiconductor (CMOS) technology
1.4 ORGANIZATION Chapter 2, reviews principle of operation. It provides an overview of working working of project project with block diagram. It also gives applications and advantages of the project. 1
Chapter 3, this chapter explains about the hardware components used in the design of the system. It gives complete detailed matter about each and every component with description, working, features, applications and neat diagram. Chapter 4, it gives the information about the software used in the project, verilog is explained in detail with the diagram. Chapter 5, this gives the implementations and results. synthesis and simulation results are explained. Chapter 6, this gives the summary and conclusion of the project. For further development of the project some future directions directions also been discussed.
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Chapter 3, this chapter explains about the hardware components used in the design of the system. It gives complete detailed matter about each and every component with description, working, features, applications and neat diagram. Chapter 4, it gives the information about the software used in the project, verilog is explained in detail with the diagram. Chapter 5, this gives the implementations and results. synthesis and simulation results are explained. Chapter 6, this gives the summary and conclusion of the project. For further development of the project some future directions directions also been discussed.
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CHAPTER 2
PRINCIPLE OF OPERATION This chapter deals with the operation of complete structure of high speed area efficient brent kung adder
2.1 INTRODUCTION Brent kung adder is fastest than half adder , full adder ,CLA. In electronics, an adder or summer is a digital a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar. similar. Although adders can be constructed for many numerical representations, such as binaryas binarycoded decimal or excess-3, excess-3, the most common adders operate on binary numbers. In cases where two's where two's complement or ones' ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder subtractor. Other signed number representations – subtractor. require a more complex adder. 2.1.1 Half adder and full adder
The half adder adds two one-bit binary numbers A and B. It has two outputs, S and C (the value theoretically carried on to the next addition); the final sum is 2C + + S . The simplest half-adder design, pictured on the right, incorporates an XOR an XOR gate for S and and an AND an AND gate for C . With the addition of an OR gate to combine their carry outputs, two half adders can be
combined to make a full adder A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and C in in; A and B are the operands, and C in in is a bit carried in from the next less significant stage. The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers.
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A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and . In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, Cout can be implemented as
.
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C i to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and C i, and C out could be made the three-bit majority function of A, B, and C i. 2.1.2
Ripple carry adder
It is possible to create a logical circuit using multiple full adders to add N -bit numbers. Each full adder inputs a C in, which is the C out of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder. The layout of a ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to carry in first adder) + 31 * 2 (for carry propagation in later adders) = 65 gate delays. A design with alternating carry polarities and optimized AND-OR-Invert gates can be about twice as faster.
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2.1.3 CLA
As seen in the ripple-carry adder, its limiting factor is the time it takes to propagate the carry. The carry look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. The result is a reduced carry propagation time. To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G in a fulladder, is given as: Pi = Ai Bi Carry propagate Gi = Ai Bi Carry generate Notice that both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay. The new expressions for the output sum and the carryout are given by: Si = Pi Ci-1 Ci+1= Gi + PiCi These equations show that a carry signal will be generated in two cases: 1) if both bits Ai and Bi are 1 2) if either Ai or Bi is 1 and the carry-in Ci is 1. Let's apply these equations for a 4-bit adder: C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 and C3 The general expression is Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 ….P1P0C0. This is a two level Circuit. In CMOS however the delay of the function is non linearly dependent on its fan in. Therefore large fan in gates are not practical. 5
Carry look-ahead adder ’s structure can be divided into three parts: the propagate/generate generator , sum generator, carry generator
Figure-2.1 Carry look ahead adder
As n increases, the block size has to be limited as well as ripple through delay accumulates. It is no longer practical to use standard look-ahead method. Instead a two level carry look-ahead adder is used. In this design, the first levels of CLAs generate the sums as well as second level generates and propagate signals. These signals then are fed to the 2nd level CLA with carryout of each level to produce the carryout signal
2.2 BLOCK DIAGRAM &DISCRIPTION Brent kung one of the parallel prefix adder. In this we are using grey box and block box. According to grey box and block box it will perform. Brent-Kung prefix tree is a wellknown structure with relatively sparse network. grey box: Block box: The Brent-Kung tree computes prefixes for 2-bit groups. These are used to find prefixes for 4-bit groups, which in turn are used to find prefixes for 8-bit groups, and so forth. The 6
prefixes then fan back down to compute the carries-in to each bit. The tree requires 2(log2N) 1 stages. The fanout is limited to 2 at each stage. The diagram shows buffers used to minimize the fanout and loading on the gates, but in practice, the buffers are generally omitted. The fan out is among the minimum as f = 0. So is the wire tracks where t = 0. The cost is the extra L - 1 logic levels. A 16-bit example is shown in Figure 3.13. The critical path is shown in the _gure with a thick gray line. Brent-Kung prefix tree is a well-known structure with relatively sparse network. The fan out is among the minimum as f = 0. So is the wire tracks where t = 0. The cost is the Brent-Kung prefix tree is a bit complex to build because it has the most logic levels.
Figure-2.2: Block diagram of Brent kung adder
2.3 ADVANTAGES
The brent kung adder is good balance between area and power cost. It takes less area to implement than the kogge-stone adder and has wiring congestion
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2.4 APPLICATIONS
Brent kung adder mostly used in DSP oriented systems
It integrated in calculators
It can be used in op amp circuits that are as comparators or differentiators.
It can be used in ALU, processors, calculate address.
2.5 CONCLUSION In terms of area or cost between the two PPAs, the BKA proves to be a better choice. Even though the BKA’s area rises as the bit size increase, it does not rise as drastically as KSA. The
higher the number of bits supported by the PPAs, the bigger is the adder in terms of area. In terms of computational delay or time propagation delay (tpd), KSA is a better choice. Although BKA has lower tpd for bit size of 8 bits, the KSA has very low tpd compared to BKA when the bit size is more than 16 bits. Therefore, only at bit size less than 16 bits the KSA has longer tpd. The KSA is widely-known as a PPA that performs fast logical addition.
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CHAPTER 3
HARDWARE DESCRIPTION
3.1 INTRODUCTION TO VLSI The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale systems design - in short, due to the advent of VLSI. The number of applications of integrated circuits in high performance computing, telecommunications, and consumer electronics has been rising steadily, and at a very fast pace. Typically, the required computational power (or, in other words, the intelligence) of these applications is the driving force for the fast development of this field. gives an overview of the prominent trends in information technologies over the next few decades. The current leading-edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability.
Figure-3.1:overview of the prominent trends in information technologies This trend is expected to continue, with very important implications on VLSI and systems design. One of the most important characteristics of information services is their 9
increasing need for very high processing power and bandwidth (in order to handle real-time video, for example). The other important characteristic is that the information services tend to become more and more personalized (as opposed to collective services such as broadcasting), which means that the devices must be more intelligent to answer individual demands, and at the same time they must be portable to allow more flexibility/mobility ERA
DATE
COMPLEXITY
Single transistor
1959
less than 1
Unit logic (one gate)
1960
1
Multi-function
1962
2-4
Complex function
1964
5-20
Medium Scale Integration
1967
20 - 200
(MSI)
Large Scale Integration
1972
200 - 2000
(LSI)
Very Large Scale Integration
1978
2000 - 20000
(VLSI)
Ultra Large Scale Integration
1989
20000 – 200k
(ULSI)
Table-3.1: Evolution of logic complexity in integrated circuits.
The most important message here is that the logic per chip has been (and still is) increasing exponentially. The monolithic integration of complexity a large number of functions on a single chip usually provides:
Less area/volume and therefore, compactness
Less power consumption
Less testing requirements at system level
Higher reliability, mainly due to improved on-chip interconnects
Higher speed, due to significantly reduced interconnection length
Significant cost savings
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Figure-3.2: Evolution of integration density and minimum feature size, as seen in the early 1980s.
Therefore, the current trend of integration will also continue in the foreseeable future. Advances in device manufacturing technology, and especially the steady reduction of minimum feature size (minimum length of a transistor or an interconnect realizable on chip) support this trend. Figure 3.2 shows the history and forecast of chip complexity - and minimum feature size over time, as seen in the early 1980s. At that time, a minimum feature size of 0.3 microns was expected around the year 2000. The actual development of the technology, however, has far exceeded these expectations. A minimum size of 0.25 microns was readily achievable by the year 1995. As a direct result of this, the integration density has also exceeded previous expectations - the first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip containing more than 3 million transistors were already available by 1994, pushing the envelope of integration density. When comparing the integration density of integrated circuits, a clear distinction must be made between the memory chips and logic chips. Figure 3.3 shows the level of integration over time for memory and logic chips, starting in 1970. It can be observed that in terms of transistor 11
count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular and thus more cells can be integrated with much less area for interconnects.
Figure-3.3: Level of integration over time, for memory chips and logic chips.
Generally speaking, logic chips such as microprocessor chips and digital signal processing (DSP) chips contain not only large arrays of memory (SRAM) cells, but also many different functional units. As a result, their design complexity is considered much higher than that of memory chips, although advanced memory chips contain some sophisticated logic functions. The design complexity of logic chips increases almost exponentially with the number of transistors to be integrated. This is translated into the increase in the design cycle time, which is the time period from the start of the chip development until the mask-tape delivery time. However, in order to make the best use of the current technology, the chip development time has to be short enough to allow the maturing of chip manufacturing and timely delivery to customers.
3.2 VLSI DESIGN FLOW The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not 12
possible or too costly, then the revision of requirements and its impact analysis must be considered. The Y-chart illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter Y.
Figure-3.4: Typical VLSI design flow in three domains (Y-chart representation).
The Y-chart consists of three major domains, namely:
behavioral domain,
structural domain,
geometrical layout domain.
The design flow starts from the algorithm that describes the behavior of the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning. The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the inter connects 13
area and signal delays. The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement & routing program. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use. The VLSI design flow shown in figure 3.4. taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process.
Figure-3.5: A more simplified view of VLSI design flow. 14
Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip designer defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom up) as early as possible. In the following, we will examine design methodologies and structured approaches which have been developed over the years to deal with both complex hardware and software projects. Regardless of the actual size of the project, the basic principles of structured design will improve the prospects of success. Some of the classical techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality.
3.3 DESIGN HIERARCHY The use of hierarchy, or divide and conquer technique involves dividing a module into sub- modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable. This approach is very similar to the software case where large programs are split into smaller and smaller sections until simple subroutines, with welldefined functions and interfaces, can be written. we have seen that the design of a VLSI chip can be represented in three domains. Correspondingly, a hierarchy structure can be described in each domain separately. However, it is important for the simplicity of design that the hierarchies in different domains can be mapped into each other easily. As an example of structural hierarchy, shows the structural decomposition of a CMOS four-bit adder into its components. The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates. At this lower level of the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of the hierarchy. 15
In the physical domain, partitioning a complex system into its various functional blocks will provide a valuable guidance for the actual realization of these blocks on chip. Obviously, the approximate shape and size (area) of each sub-module should be estimated in order to provide a useful floor plan. The hierarchical decomposition of a four-bit adder in physical description (geometrical layout) domain, resulting in a simple floor plan.
Figure-3.6: Structural decomposition of a four-bit adder circuit, showing the hierarchy down to gate level.
Figure-3.7: Regular design of a 2-1 MUX, a DFF and an adder, using inverters and tri-state buffers.
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3.4 VLSI DESIGN STYLES Several design styles can be considered for chip implementation of specified algorithms or logic functions. Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the functionality at low cost. 3.4.1 Field Programmable Gate Array (FPGA)
Fully fabricated FPGA chips containing thousands of logic gates or even more, with programmable interconnects, are available to users for their custom hardware programming to realize desired functionality. This design style provides a means for fast prototyping and also for cost-effective chip design, especially for low-volume applications. A typical field programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs), and programmable interconnect structures. The programming of the interconnects is implemented by programming of RAM cells whose output terminals are connected to the gates of MOS pass transistors. A general architecture of FPGA from XILINX is shown in Fig. 3.8. A more detailed view showing the locations of switch matrices used for interconnect routing is given in Fig. 3.9. A simple CLB (model XC2000 from XILINX) is shown in Fig. 3.10. It consists of four signal input terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an SR-latch, and a look-up table (LUT). The LUT is a digital memory that stores the truth table of the Boolean function. Thus, it can generate any function of up to four variables or any two functions of three variables. The control terminals of multiplexers are not shown explicitly . The CLB is configured such that many different logic functions can be realized by programming its array. More sophisticated CLBs have also been introduced to map complex functions. The typical design flow of an FPGA chip starts with the behavioral description of its functionality, using a hardware description language such as VHDL. The synthesized architecture is then technology-mapped (or partitioned) into circuits or logic cells. At this stage, the chip design is completely described in terms of available logic cells. Next, the placement
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and routing step assigns individual logic cells to FPGA sites (CLBs) and determines the routing patterns among the cells in accordance with the net list. After routing is completed, the on-chip-
Figure-3.8: General architecture of Xilinx FPGAs.
Figure-3.9: Detailed view of switch matrices and interconnection routing between CLBs 18
Figure-3.10: XC2000 CLB of the Xilinx FPGA.
Performance of the design can be simulated and verified before downloading the design for programming of the FPGA chip. The programming of the chip remains valid as long as the chip is powered-on, or until new programming is done. In most cases, full utilization of the FPGA chip area is not possible - many cell sites may remain unused. The largest advantage of FPGA-based design is the very short turn-around time, i.e., the time required from the start of the design process until a functional chip is available. Since no physical manufacturing step is necessary for customizing the FPGA chip, a functional sample can be obtained almost as soon as the design is mapped into a specific technology. The typical price of FPGA chips are usually higher than other realization alternatives (such as gate array or standard cells) of the same design, but for small-volume production of ASIC chips and for fast prototyping, FPGA offers a very valuable option. 3.4.2 Gate Array Design
In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. While the design implementation of the FPGA chip is done with user programming, that of the gate array is done with metal mask design and processing. Gate array implementation requires a two-step manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can 19
be stored for later customization, which is completed by defining the metal interconnects between the transistors of the array .
.Figure-3.11: Basic processing steps required for gate array implementation.
Figure-3.12: A corner of a typical gate array chip.
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Figure 3.13 shows a magnified portion of the internal array with metal mask design (metal lines highlighted in dark) to realize a complex logic function. Typical gate array platforms allow dedicated areas, called channels, for intercell routing as shown in Figs. 3.12 and 3.13 between rows or columns of MOS transistors. The availability of these routing channels simplifies the interconnections, even using one metal layer only. The interconnection patterns to realize basic logic gates can be stored in a library, which can then be used to customize rows of uncommitted transistors according to the netlist. While most gate array platforms only contain rows of uncommitted transistors separated by routing channels, some other platforms also offer dedicated memory (RAM) arrays to allow a higher density where memory functions are required. Figure 3.14 shows the layout views of a conventional gate array and a gate array platform with two dedicated memory banks.
Figure-3.13: Metal mask design to realize a complex logic function on a channeled GA platform. 21
With the use of multiple interconnect layers, the routing can be achieved over the active cell areas; thus, the routing channels can be removed as in Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and pMOS transistors. As in the gate array case, neighboring transistors can be customized using a metal mask to form basic logic gates. For intercell routing, however, some of the uncommitted transistors must be sacrificed. This approach results in more flexibility for interconnections, and usually in a higher density.
Figure-3.14: Layout views of a conventional GA chip and a gate array with two memory banks.
Figure-3.15: The platform of a Sea-of-Gates (SOG) chip.
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In general, the GA chip utilization factor, as measured by the used chip area divided by the total chip area, is higher than that of the FPGA and so is the chip speed, since more customized design can be achieved with metal mask designs. The current gate array chips can implement as many as hundreds of thousands of logic gates.
Figure-3.16: Comparison between the channeled (GA) vs. the channel less (SOG) approaches.
3.4.3
Standard-Cells Based Design
The standard-cells based design is one of the most prevalent full custom design styles which require development of a full custom mask set. The standard cell is also called the poly cell. In this design style, all of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops. Each gate type can have multiple implementations to provide adequate driving capability for different fan outs.The characterization of each cell is done for several different categories. It consists of
delay time vs. load capacitance
circuit simulation model 23
timing simulation model
fault simulation model
cell data for place-and-route
mask data
To enable automated placement of the cells and routing of inter-cell connections, each cell layout is designed with a fixed height, so that a number of cells can be abutted side-by-side to form rows. The power and ground rails typically run parallel to the upper and lower boundaries of the cell, thus, neighboring cells share a common power and ground bus. The input and output pins are located on the upper and lower boundaries of the cell. Figure 3.16 shows the layout of a typical standard cell. Notice that the nMOS transistors are located closer to the ground rail while the pMOS transistors are placed closer to the power rail.
Figure-3.17: A standard cell layout example.
Figure 3.18 shows a floor plan for standard-cell based design. Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells. Between cell rows are channels for dedicated inter-cell routing. As in the case of Sea-of-Gates, with over-the- cell routing, the channel areas can be reduced or even removed provided that the cell rows offer sufficient routing space
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Figure-3.18: A simplified floor plan of standard-cells-based design.
If a number of cells must share the same input and/or output signals, a common signal bus structure can also be incorporated into the standard-cell-based chip layout. The simplified symbolic view of a case where a signal bus has been inserted between the rows of standard cells. Note that in this case the chip consists of two blocks, and power/ground routing must be provided from both sides of the layout area. Standard-cell based designs may consist of several such macro-blocks, each corresponding to a specific unit of the system architecture such as ALU, control logic, etc.
Figure-3.19: Simplified floor plan consisting of two separate blocks and a common signal bus.
After chip logic design is done using standard cells in the library, the most challenging task is to place individual cells into rows and interconnect them in a way that meets stringent 25
design goals in circuit speed, chip area, and power consumption. Many advanced CAD tools for place-and-route have been developed and used to achieve such goals. Also from the chip layout, circuit models which include interconnect parasitics can be extracted and used for timing simulation and analysis to identify timing critical paths. For timing critical paths, proper gate sizing is often practiced to meet the timing requirements. In many VLSI chips, such as microprocessors and digital signal processing chips, standard-cells based design is used to implement complex control logic modules. Some full custom chips can be also implemented exclusively with standard cells. Finally, Fig. 3.20 shows the detailed mask layout of a standard-cell-based chip with an un interrupted single block of cell rows, and three memory banks placed on one side of the chip. Notice that within the cell block, the separations between neighboring rows depend on the number of wires in the routing channel between the cell rows. If a high interconnect density can be achieved in the routing channel, the standard cell rows can be placed closer to each other, resulting in a smaller chip area. The availability of dedicated memory blocks also reduces the area, since the realization of memory elements using standard cells would occupy a larger area.
Figure-3.20: Mask layout of a standard-cell-based chip with a single block of cells and three memory banks.
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3.4.4 Full Custom Design
Although the standard-cells based design is often called full custom design, in a strict sense, it is somewhat less than fully custom since the cells are pre-designed for general use and the same cells are utilized in many different chip designs. In a fuller custom design, the entire mask design is done anew without use of any library. However, the development cost of such a design style is becoming prohibitively high. Thus, the concept of design reuse is becoming popular in order to reduce design cycle time and development cost. The most rigorous full custom design can be the design of a memory cell, be it static or dynamic. Since the same layout design is replicated, there would not be any alternative to high density memory chip design. For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip, such as standard cells, data-path cells and PLAs. In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer, design productivity is usually very low typically 10 to 20 transistors per day, per designer.
Figure-3.21: Overview of VLSI design styles
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In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high performance microprocessors and FPGA masters. Figure 3.21 shows the full layout of the Intel 486 microprocessor chip, which is a good example of a hybrid full-custom design. Here, one can identify four different design styles on one chip: Memory banks (RAM cache), data-path units consisting of bit-slice cells, control circuitry mainly consisting of standard cells and PLA blocks.
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CHAPTER 4
SOFTWARE DESCRIPTION
In the semiconductor and electronic design industry, Verilog is a hardware description language(HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level of abstraction. It is also used in the verification of analog and mixed-signal circuits.
4.1Overview Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables (in any general programming language we need to define some temporary storage spaces for the operands to be operated on subsequently; those are temporary storage variables). Since these concepts are part of Verilog's language semantics, designers could quickly write descriptions of large circuits in a relatively compact and concise form. At the time of Verilog's introduction (1984), Verilog represented a tremendous productivity improvement for circuit designers who were already using graphical capture software and specially-written software programs to document and simulate electronic circuits. A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following: net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But the blocks themselves are executed concurrently, qualifying Verilog as a dataflow language. 29
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of shared signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the wire's (readable) value is resolved by a function of the source drivers and their strengths.
4.2 History 4.2. 1 Beginning
Verilog was the first modern hardware description language to be invented. It was created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this process was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added. 4.2.2 Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. 4.2.3 Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 13642001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8 bit addition required an explicit description of the Boolean algebra to determine its correct 30
value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/end generate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision operators (case/if/else). Using generate/ end generate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability (e.g. always @*, named parameter override, C-style function/task/module header declaration). Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. 4.2.4 Verilog 2005
Verilog 2005 (IEEE Standard
1364-2005)
consists of minor
corrections, spec
clarifications, and a few new language features (such as the uwire keyword).A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog. 4.2.5 System Verilog
SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design verification and design modeling. As of 2009, the System Verilog and Verilog language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009). In the late 1990s, the Verilog Hardware Description Language (HDL) became the most widely used language for describing hardware for simulation and synthesis. However, the first two versions standardized by the IEEE (1364-1995 and 1364-2001) had only simple constructs for creating tests. As design sizes outgrew the verification capabilities of the language, commercial Hardware Verification Languages (HVL) such as Open Vera and e were created. Companies that did not want to pay for these tools instead spent hundreds of man-years creating their own custom tools. This productivity crisis (along with a similar one on the design side) led to the creation of Accellera, a consortium of EDA companies and users who wanted to create the next generation of Verilog. The donation of the Open-Vera language formed the basis for
31
the HVL features of SystemVerilog.Accellera’s goal was met in November 2005 with the
adoption of the IEEE standard P1800-2005 for SystemVerilog, IEEE (2005). Some of the typical features of an HVL that distinguish it from a Hardware Description Language such as Verilog or VHDL are
Constrained-random stimulus generation
Functional coverage
Higher-level structures, especially Object Oriented Programming
Multi-threading and inter process communication
Support for HDL types such as Verilog’s 4-state values
Tight integration with event-simulator for control of the design
There are many other useful features, but these allow you to create test benches at a higher level of abstraction than you are able to achieve with an HDL or a programming language such as C.System Verilog provides the best framework to achieve coverage-driven verification (CDV). CDV combines automatic test generation, self-checking test benches, and coverage metrics to significantly reduce the time spent verifying a design. The purpose of CDV is to:
Eliminate the effort and time spent creating hundreds of tests.
Ensure thorough verification using up-front goal setting.
Receive early error notifications and deploy run-time checking and error analysis to simplify debugging.
4.2 Examples Ex1: A hello world program looks like this module main; initial begin
$display("Hello world!"); $finish; end endmodule 32
Ex2: A simple example of two flip-flops follows module toplevel(clock,reset); input clock; input reset;
reg flop1; reg flop2;
always @ (posedge reset or posedge clock) if (reset) begin
flop1 <= 0; flop2 <= 1; end else begin
flop1 <= flop2; flop2 <= flop1; end endmodule
The "<=" operator in Verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. Its action doesn't register until the next clock cycle. This means that the order of the assignments are irrelevant and will produce the same result: flop1 and flop2 will swap values every clock. The other assignment operator, "=", is referred to as a blocking assignment. When "=" assignment is used, for the purposes of logic, the target variable is updated immediately. In the above example, had the statements used the "=" blocking operator instead of "<=", flop1 and flop2 would not have been swapped. Instead, as in traditional programming, the compiler would 33
understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant logic to set flop2 equal to flop1.) Ex3: An example counter circuit follows module Div20x (rst, clk, cet, cep, count, tc);
// TITLE 'Divide-by-20 Counter with enables' // enable CEP is a clock enable only // enable CET is a clock enable and // enables the TC output // a counter using the Verilog language parameter size = 5; parameter length = 20; input rst; // These inputs/outputs represent input clk; // connections to the module. input cet; input cep; output [size-1:0] count; output tc; reg [size-1:0] count; // Signals assigned
// within an always // (or initial)block // must be of type reg
wire tc; // Other signals are of type wire
// The always statement below is a parallel // execution statement that // executes any time the signals // rst or clk transition from low low to high always @ (posedge clk or posedge rst)
(rst) // This causes reset of the cntr if (rst) 34
count <= {size{1'b0}}; else
(cet && cep) // Enables both true if (cet begin
(count == length-1) if (count count <= {size{1'b0}}; else
count <= count + 1'b1; end
// the value of tc is continuously assigned // the value of the expression
len gth-1)); assign tc = (cet && (count == length-1)); endmodule Ex4: An example of delays reg a, b, c, d; wire e;
... always @(b or e) begin
a = b & e; b = a | b; #5 c = b; d = #6 c ^ e; end
The always clause above illustrates the other type of method of use, i.e. the always clause executes any time any of the entities in the list change, i.e. the b or e change. When changes, immediately a is assigned a new value, and due to the blocking assignment b is assigned a new value afterward (taking into account the new value of a.) After a delay of 5 time 35
units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away. Constants
The definition of constants in Verilog supports the addition of a width parameter. The basic syntax is: '< > Examples:
12'h123 - Hexadecimal 123 (using 12 bits)
20'd44 - Decimal 44 (using 20 bits b its - 0 extension is automatic)
4'b1010 - Binary 1010 (using 4 bits)
6'o77 - Octal 77 (using 6 bits)
4.3 Synthesizable Synthesizable Constructs There are several statements in Verilog that have no analog in real hardware, e.g. $display. Consequently, much of the language cannot be used to describe hardware. The examples presented here are the classic subset of the language that has a direct mapping to real gates. // Mux examples - Three ways to do the same thing. // The first example uses continuous assignment wire out; assign out = sel ? a : b;
// the second example uses a procedure // to accomplish the same thing. one of these
reg out;
always @(a or b or sel) begin case(sel)
1'b0: out = b; 36
1'b1: out = a; endcase end
// Finally - you can use if/else in a // procedural structure. reg out; always @(a or b or sel) if (sel)
out = a; else
out = b;
4.4 Initial Vs Always: There are two separate ways of declaring a Verilog process. These are the always and the initial keywords. The always keyword indicates a free-running process. The initial keyword indicates a process executes exactly once. Both constructs begin execution at simulator time 0, and both execute until the end of the block. Once an always block has reached its end, it is rescheduled (again). It is a common misconception to believe that an initial block will execute before an always block. In fact, it is better to think of the initial-block as a special-case of the always-block, one which terminates after it completes for the first time. //Examples initial begin
a = 1; // Assign a value to reg a at time 0 #1; // Wait 1 time unit b = a; // Assign the value of reg a to reg b end always @(a or b) // Any time a or b CHANGE, run the process begin if (a) 37
c = b; else
d = ~b; end // Done with this block, now return to the top (i.e. the @ event-control)
always @(posedge a) // Run whenever reg a has a low to high change
a <= b; These are the classic uses for these two keywords, but there are two significant additional uses. The most common of these is an alwayskeyword without the @(...) sensitivity list. It is possible to use always as shown below: always begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0 #1; // Wait for 1 time unit clk = 1; // Set clk to 1 #1; // Wait 1 time unit end // Keeps executing - so continue back at the top of the begin
The always keyword acts similar to the "C" construct while(1) {..} in the sense that it will execute forever.The other interesting exception is the use of the initial keyword with the addition of the forever keyword.
4.5 Race Condition The order of execution isn't always guaranteed within Verilog. This can best be illustrated by a classic example. Consider the code snippet below initial
a = 0; initial
b = a; initial begin 38
#1; $display("Value a=%b Value of b=%b",a,b); end
What will be printed out for the values of a and b? Depending on the order of execution of the initial blocks, it could be zero and zero, or alternately zero and some other arbitrary uninitialized value. The $display statement will always execute after both assignment blocks have completed, due to the #1 delay.
4.6 Operators Note: These operators are not shown in order of precedence.
Operator
Bitwise
Logical
Reduction
Operator
Operation performed
~
Bitwise NOT (1's complement)
&
Bitwise AND
|
Bitwise OR
^
Bitwise XOR
~^ or ^~
Bitwise XNOR
!
NOT
&&
AND
||
OR
&
Reduction AND
~&
Reduction NAND
|
Reduction OR 39
Arithmetic
Relational
Shift
~|
Reduction NOR
^
Reduction XOR
~^ or ^~
Reduction XNOR
+
Addition
-
Subtraction
-
2's complement
*
Multiplication
/
Division
**
Exponentiation (*Verilog-2001)
>
Greater than
<
Less than
>=
Greater than or equal to
<=
Less than or equal to
==
Logical equality (bit-value 1'bX is removed from comparison)
!=
Logical inequality (bit-value 1'bX is removed from comparison)
===
4-state logical equality (bit-value 1'bX is taken as literal)
!==
4-state logical inequality (bit-value 1'bX is taken as literal)
>>
Logical right shift
<<
Logical left shift
>>>
Arithmetic right shift (*Verilog-2001) 40
Arithmetic left shift (*Verilog-2001)
<<< Concatenation { , }
Concatenation
Replication
{n{m}}
Replicate value m for n times
Conditional
?:
Conditional Table 4.1: operators
4.7 System Tasks: System tasks are available to handle simple I/O, and various design measurement functions. All system tasks are prefixed with $ to distinguish them from user tasks and functions. This section presents a short list of the most often used tasks.
4.8 MODELSIM Model Sim is a verification and simulation tool for VHDL, V erilog, SystemVerilog, andmixed language designs. Basic simulation flow
Project flow
Multiple library flow
Debugging tools.
The following diagram shows the basic steps for simulating a design in ModelSim.
Figure-: 4.1 Basic Simulation Flow - Overview Lab 41
4.8.1 Creating the Working Library Model Sim, all designs are compiled into a library. You typically start a new simulation in Model Sim by creating a working library called "work," which is the default library name used by the compiler as the default destination for compiled design units.
4.8.2 Compiling Your Design After creating the working library, you compile your design units into it. The Model Sim Library format is compatible across all supported platforms. You can simulate your design on any platform without having to recompile your design. 4.8.3
Loading the Simulator With Your Design And Running The Simulation With the design compiled, you load the simulator with your design by invoking the
simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you enter a run command to begin simulation.
4.8.4 Debugging Your Results If you don’t get the results you expect, you can use Model Sim’s robust debugging
environment to track down the cause of the problem.
4.9 CODE 4.9.1 Ripple carry adder
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date:
17:22:09 05/16/2013
// Design Name: // Module Name:
ripple
// Project Name: 42
// Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////////
module ripplecarry(A,B,Cin,SUM,Cout); input [15:0]A,B; input Cin; output [15:0]SUM; output Cout; wire [15:0]c; full_adder FA0 (.a(A[0]), .b(B[0]), .cin(Cin), .sum(SUM[0]), .cout(c[0])); full_adder FA1 (.a(A[1]), .b(B[1]), .cin(c[0]), .sum(SUM[1]), .cout(c[1])); full_adder FA2 (.a(A[2]), .b(B[2]), .cin(c[1]), .sum(SUM[2]), .cout(c[2])); full_adder FA3 (.a(A[3]), .b(B[3]), .cin(c[2]), .sum(SUM[3]), .cout(c[3])); full_adder FA4 (.a(A[4]), .b(B[4]), .cin(c[3]), .sum(SUM[4]), .cout(c[4])); full_adder FA5 (.a(A[5]), .b(B[5]), .cin(c[4]), .sum(SUM[5]), .cout(c[5])); full_adder FA6 (.a(A[6]), .b(B[6]), .cin(c[5]), .sum(SUM[6]), .cout(c[6])); full_adder FA7 (.a(A[7]), .b(B[7]), .cin(c[6]), .sum(SUM[7]), .cout(c[7])); full_adder FA8 (.a(A[8]), .b(B[8]), .cin(c[7]), .sum(SUM[8]), .cout(c[8])); full_adder FA9 (.a(A[9]), .b(B[9]), .cin(c[8]), .sum(SUM[9]), .cout(c[9])); full_adder FA10 (.a(A[10]),.b(B[10]),.cin(c[9]), .sum(SUM[10]),.cout(c[10])); full_adder FA11 (.a(A[11]),.b(B[11]),.cin(c[10]),.sum(SUM[11]),.cout(c[11])); 43
full_adder FA12 (.a(A[12]),.b(B[12]),.cin(c[11]),.sum(SUM[12]),.cout(c[12])); full_adder FA13 (.a(A[13]),.b(B[13]),.cin(c[12]),.sum(SUM[13]),.cout(c[13])); full_adder FA14 (.a(A[14]),.b(B[14]),.cin(c[13]),.sum(SUM[14]),.cout(c[14])); full_adder FA15 (.a(A[15]),.b(B[15]),.cin(c[14]),.sum(SUM[15]),.cout(c[15]));
assign Cout=c[15];
endmodule
// full adder module full_adder(a,b,cin,sum,cout); input a,b,cin; output sum,cout; wire I1,I2,I3;
half_adder HA1(.a(a),.b(b),.carry(I2),.sum(I1)); half_adder HA2(.a(I1),.b(cin),.carry(I3),.sum(sum)); or (cout,I2,I3);
endmodule
// half adder module half_adder(a,b,sum,carry);
input a,b; output sum,carry;
assign sum=a^b; assign carry=a&b; 44
endmodule
4.9.2 Brent kung adder
/* * 32-bit Brent-Kung Adder * * Pulluru Ashok Reddy */
module BrentKung32 (A, B, Cin, S, Cout); input [31:0] A, B; input Cin; output [31:0] S; output Cout;
/* First generate the propigate and generate signals for each bit */ wire [1:0] r1c32, r1c31, r1c30, r1c29, r1c28, r1c27, r1c26, r1c25; wire [1:0] r1c24, r1c23, r1c22, r1c21, r1c20, r1c19, r1c18, r1c17; wire [1:0] r1c16, r1c15, r1c14, r1c13, r1c12, r1c11, r1c10, r1c9; wire [1:0] r1c8, r1c7, r1c6, r1c5, r1c4, r1c3, r1c2, r1c1;
pg32 ipg32(.A(A), .B(B), .pg31(r1c32),.pg30(r1c31),.pg29(r1c30), .pg28(r1c29),.pg27(r1c28),.pg26(r1c27),.pg25(r1c26),.pg24(r1c25), .pg23(r1c24),.pg22(r1c23),.pg21(r1c22),.pg20(r1c21),.pg19(r1c20), .pg18(r1c19),.pg17(r1c18),.pg16(r1c17),.pg15(r1c16),.pg14(r1c15), .pg13(r1c14),.pg12(r1c13),.pg11(r1c12),.pg10(r1c11),.pg9(r1c10), .pg8(r1c9),.pg7(r1c8),.pg6(r1c7),.pg5(r1c6),.pg4(r1c5),.pg3(r1c4), .pg2(r1c3),.pg1(r1c2),.pg0(r1c1));
45
/* First row */ wire [1:0] r2c31, r2c29, r2c27, r2c25, r2c23, r2c21, r2c19, r2c17; wire [1:0] r2c15, r2c13, r2c11, r2c9, r2c7, r2c5, r2c3; wire r2c1;
black ir1c31(.pg(r1c31), .pg0(r1c30), .pgo(r2c31)); black ir1c29(.pg(r1c29), .pg0(r1c28), .pgo(r2c29)); black ir1c27(.pg(r1c27), .pg0(r1c26), .pgo(r2c27)); black ir1c25(.pg(r1c25), .pg0(r1c24), .pgo(r2c25)); black ir1c23(.pg(r1c23), .pg0(r1c22), .pgo(r2c23)); black ir1c21(.pg(r1c21), .pg0(r1c20), .pgo(r2c21)); black ir1c19(.pg(r1c19), .pg0(r1c18), .pgo(r2c19)); black ir1c17(.pg(r1c17), .pg0(r1c16), .pgo(r2c17)); black ir1c15(.pg(r1c15), .pg0(r1c14), .pgo(r2c15)); black ir1c13(.pg(r1c13), .pg0(r1c12), .pgo(r2c13)); black ir1c11(.pg(r1c11), .pg0(r1c10), .pgo(r2c11)); black ir1c9(.pg(r1c9), .pg0(r1c8), .pgo(r2c9)); black ir1c7(.pg(r1c7), .pg0(r1c6), .pgo(r2c7)); black ir1c5(.pg(r1c5), .pg0(r1c4), .pgo(r2c5)); black ir1c3(.pg(r1c3), .pg0(r1c2), .pgo(r2c3)); gray ir1c1(.pg(r1c1), .pg0(Cin), .pgo(r2c1));
/* Second row */ wire [1:0] r3c31, r3c27, r3c23, r3c19, r3c15, r3c11, r3c7; wire r3c3;
black ir2c31(.pg(r2c31), .pg0(r2c29), .pgo(r3c31)); black ir2c27(.pg(r2c27), .pg0(r2c25), .pgo(r3c27)); black ir2c23(.pg(r2c23), .pg0(r2c21), .pgo(r3c23)); black ir2c19(.pg(r2c19), .pg0(r2c17), .pgo(r3c19)); 46
black ir2c15(.pg(r2c15), .pg0(r2c13), .pgo(r3c15)); black ir2c11(.pg(r2c11), .pg0(r2c9), .pgo(r3c11)); black ir2c7(.pg(r2c7), .pg0(r2c5), .pgo(r3c7)); gray ir2c3(.pg(r2c3), .pg0(r2c1), .pgo(r3c3));
/* Third row */ wire [1:0] r4c31, r4c23, r4c15; wire r4c7;
black ir3c31(.pg(r3c31), .pg0(r3c27), .pgo(r4c31)); black ir3c23(.pg(r3c23), .pg0(r3c19), .pgo(r4c23)); black ir3c15(.pg(r3c15), .pg0(r3c11), .pgo(r4c15)); gray ir3c7(.pg(r3c7), .pg0(r3c3), .pgo(r4c7));
/* Fourth row */ wire [1:0] r5c31; wire r5c15;
black ir4c31(.pg(r4c31), .pg0(r4c23), .pgo(r5c31)); gray ir4c15(.pg(r4c15), .pg0(r4c7), .pgo(r5c15));
/* Fifth row */ wire r6c31, r6c23;
gray ir5c31(.pg(r5c31), .pg0(r5c15), .pgo(r6c31)); gray ir5c23(.pg(r4c23), .pg0(r5c15), .pgo(r6c23));
/* Sixth row */ wire r7c27, r7c19, r7c11;
47
gray ir6c27(.pg(r3c27), .pg0(r6c23), .pgo(r7c27)); gray ir6c19(.pg(r3c19), .pg0(r5c15), .pgo(r7c19)); gray ir6c11(.pg(r3c11), .pg0(r4c7), .pgo(r7c11));
/* Seventh row */ wire r8c29, r8c25, r8c21, r8c17, r8c13, r8c9, r8c5;
gray ir7c29(.pg(r2c29), .pg0(r7c27), .pgo(r8c29)); gray ir7c25(.pg(r2c25), .pg0(r6c23), .pgo(r8c25)); gray ir7c21(.pg(r2c21), .pg0(r7c19), .pgo(r8c21)); gray ir7c17(.pg(r2c17), .pg0(r5c15), .pgo(r8c17)); gray ir7c13(.pg(r2c13), .pg0(r7c11), .pgo(r8c13)); gray ir7c9(.pg(r2c9), .pg0(r4c7), .pgo(r8c9)); gray ir7c5(.pg(r2c5), .pg0(r3c3), .pgo(r8c5));
/* Eighth row */ wire r9c30, r9c28, r9c26, r9c24, r9c22, r9c20, r9c18, r9c16; wire r9c14, r9c12, r9c10, r9c8, r9c6, r9c4, r9c2;
gray ir8c30(.pg(r1c30), .pg0(r8c29), .pgo(r9c30)); gray ir8c28(.pg(r1c28), .pg0(r7c27), .pgo(r9c28)); gray ir8c26(.pg(r1c26), .pg0(r8c25), .pgo(r9c26)); gray ir8c24(.pg(r1c24), .pg0(r6c23), .pgo(r9c24)); gray ir8c22(.pg(r1c22), .pg0(r8c21), .pgo(r9c22)); gray ir8c20(.pg(r1c20), .pg0(r7c19), .pgo(r9c20)); gray ir8c18(.pg(r1c18), .pg0(r8c17), .pgo(r9c18)); gray ir8c16(.pg(r1c16), .pg0(r5c15), .pgo(r9c16)); gray ir8c14(.pg(r1c14), .pg0(r8c13), .pgo(r9c14)); gray ir8c12(.pg(r1c12), .pg0(r7c11), .pgo(r9c12)); gray ir8c10(.pg(r1c10), .pg0(r8c9), .pgo(r9c10)); 48
gray ir8c8(.pg(r1c8), .pg0(r4c7), .pgo(r9c8)); gray ir8c6(.pg(r1c6), .pg0(r8c5), .pgo(r9c6)); gray ir8c4(.pg(r1c4), .pg0(r3c3), .pgo(r9c4)); gray ir8c2(.pg(r1c2), .pg0(r2c1), .pgo(r9c2));
/* Finaly produce the sum */ xor32 ixor32(.A({r6c31,r9c30,r8c29,r9c28,r7c27,r9c26,r8c25,r9c24,r6c23, r9c22,r8c21,r9c20,r7c19,r9c18,r8c17,r9c16,r5c15,r9c14,r8c13,r9c12, r7c11,r9c10,r8c9,r9c8,r4c7,r9c6,r8c5,r9c4,r3c3,r9c2,r2c1,Cin}), .B({r1c32[1], r1c31[1],r1c30[1],r1c29[1],r1c28[1],r1c27[1],r1c26[1], r1c25[1],r1c24[1],r1c23[1],r1c22[1],r1c21[1],r1c20[1],r1c19[1], r1c18[1],r1c17[1],r1c16[1],r1c15[1],r1c14[1],r1c13[1],r1c12[1], r1c11[1],r1c10[1],r1c9[1],r1c8[1],r1c7[1],r1c6[1],r1c5[1],r1c4[1], r1c3[1],r1c2[1],r1c1[1]}), .S(S));
/* Generate Cout */ gray gcout(.pg(r1c32), .pg0(r6c31), .pgo(Cout));
endmodule
/* * cells.v * * Support cell library for adder circuits */
module gray (pg, pg0, pgo); input [1:0] pg; input pg0; output pgo; 49
assign pgo = (pg0 & pg[1]) | pg[0];
endmodule
module black (pg, pg0, pgo); input [1:0] pg, pg0; output [1:0] pgo;
assign pgo[1] = pg[1] & pg0[1]; assign pgo[0] = (pg0[0] & pg[1]) | pg[0];
endmodule
/*module xor16 (A, B, S); input [15:0] A, B; output [15:0] S;
assign S = A ^ B;
endmodule*/
module xor32 (A, B, S); input [31:0] A, B; output [31:0] S;
assign S = A ^ B;
endmodule
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module pg32 (A, B, pg31, pg30, pg29, pg28, pg27, pg26, pg25, pg24, pg23, pg22, pg21, pg20, pg19, pg18, pg17, pg16, pg15, pg14, pg13, pg12, pg11, pg10, pg9, pg8, pg7, pg6, pg5, pg4, pg3, pg2, pg1, pg0); input [31:0] A, B; output [1:0] pg31, pg30, pg29, pg28, pg27, pg26, pg25, pg24, pg23, pg22, pg21, pg20, pg19, pg18, pg17, pg16, pg15, pg14, pg13, pg12, pg11, pg10, pg9, pg8, pg7, pg6, pg5, pg4, pg3, pg2, pg1, pg0;
assign pg31 = {(A[31] ^ B[31]), (A[31] & B[31])}; assign pg30 = {(A[30] ^ B[30]), (A[30] & B[30])}; assign pg29 = {(A[29] ^ B[29]), (A[29] & B[29])}; assign pg28 = {(A[28] ^ B[28]), (A[28] & B[28])}; assign pg27 = {(A[27] ^ B[27]), (A[27] & B[27])}; assign pg26 = {(A[26] ^ B[26]), (A[26] & B[26])}; assign pg25 = {(A[25] ^ B[25]), (A[25] & B[25])}; assign pg24 = {(A[24] ^ B[24]), (A[24] & B[24])}; assign pg23 = {(A[23] ^ B[23]), (A[23] & B[23])}; assign pg22 = {(A[22] ^ B[22]), (A[22] & B[22])}; assign pg21 = {(A[21] ^ B[21]), (A[21] & B[21])}; assign pg20 = {(A[20] ^ B[20]), (A[20] & B[20])}; assign pg19 = {(A[19] ^ B[19]), (A[19] & B[19])}; assign pg18 = {(A[18] ^ B[18]), (A[18] & B[18])}; assign pg17 = {(A[17] ^ B[17]), (A[17] & B[17])}; assign pg16 = {(A[16] ^ B[16]), (A[16] & B[16])}; assign pg15 = {(A[15] ^ B[15]), (A[15] & B[15])}; assign pg14 = {(A[14] ^ B[14]), (A[14] & B[14])}; assign pg13 = {(A[13] ^ B[13]), (A[13] & B[13])}; assign pg12 = {(A[12] ^ B[12]), (A[12] & B[12])}; assign pg11 = {(A[11] ^ B[11]), (A[11] & B[11])}; 51
assign pg10 = {(A[10] ^ B[10]), (A[10] & B[10])}; assign pg9 = {(A[9] ^ B[9]), (A[9] & B[9])}; assign pg8 = {(A[8] ^ B[8]), (A[8] & B[8])}; assign pg7 = {(A[7] ^ B[7]), (A[7] & B[7])}; assign pg6 = {(A[6] ^ B[6]), (A[6] & B[6])}; assign pg5 = {(A[5] ^ B[5]), (A[5] & B[5])}; assign pg4 = {(A[4] ^ B[4]), (A[4] & B[4])}; assign pg3 = {(A[3] ^ B[3]), (A[3] & B[3])}; assign pg2 = {(A[2] ^ B[2]), (A[2] & B[2])}; assign pg1 = {(A[1] ^ B[1]), (A[1] & B[1])}; assign pg0 = {(A[0] ^ B[0]), (A[0] & B[0])};
endmodule
module inv(A, Y); input A; output Y; assign Y = ~A; endmodule
module and2(A, B, Y); input A, B; output Y; assign Y = (A & B); endmodule
module nand2(A, B, Y); input A, B; output Y; assign Y = ~(A & B); 52
endmodule
module or2(A, B, Y); input A, B; output Y; assign Y = (A | B); endmodule
module nor2(A, B, Y); input A, B; output Y; assign Y = ~(A | B); endmodule
module tiehi(Y); output Y; assign Y = 1'b1; endmodule
module tielo(Y); output Y; assign Y = 1'b0; endmodule
module xor2(A, B, Y); input A, B; output Y; assign Y = A ^ B; endmodule
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CHAPTER 5
IMPLEMENTATION & RESULT 5.1 IMPLEMENTATION 5.1.1 Xilinx
1. open Xilinx 2. a new window which shows Xilinx is opened
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3. Press OK 4. New window will appear after selecting OK
5. Go to File menu, select New Project
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6. Select the destination
7. After Selecting destination select Next 56
8. A new window which shows Device properties will appear
9. Select the Device properties in device properties window and select Next. 57
10. After device properties window, New project window will appear.
11. Now add source to the project by selecting "New Source" option
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12. Select the verilog module option and enter the file name 13. Save the file name with .v extension.
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14. After entering file name select Next 15. A new window which shows New source wizard will appear.
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16. Select Finish option 17. In the New Project Wizard source is added.
18. Select Next 19. A new wizard will appear write the code in this wizard 20. Save the file, Compile, and run the file
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5.1.2 Modelsim
1. Start Modelsim 2. Modelsim window will appear
3. Click on jumpstart. 4. A new window which shows welcome to Modelsim will appear.
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5. Click on create new project. 6. A new window which shows project creation will appear
7. Type the project name. example, hummingbird. click OK. 8. A new window which shows "Add items to project", will appear.
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9. Click on "Create New File", a new window naamed"Create Project File" will appear.
10. Enter the file name and press OK, this file is extended with ".vhd".
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11. Double click on the created file a window will appear, code should be written in that window.
12. After writing code save the file go to file menu>save as>cryptography.vhd, click on save.
13. Select the file, Right click on file go to compile > compile all.
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14. Check for errors
15. Go to Simulate > start simulation
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16. start simulation window
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17. go to work select top
18. double clik on top and select ok 19. a new window instance window will appear
20. write click on top instance Add> to wave > all items in region. 68
21. after that wave window will appear.
22. Force the values for signals and check for desired output.
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23 To continue the simulation (after 200ns) for another 100ns type: run 100ns (enter). The waveform output will now have 300ns of results. To start again from time 0, enter “restart”.
5.2 RESULTS
5.2.1 Simulation Results
At first, we had designed a Brent Kung adder that uses recursion as an idea to implement a fast adder. This was modeled in Model Sim and the results were just as expected for a parallel adder.
Screen-5.1:simulation of brent kung adder
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5.2 Synthesis Results
Screens-5.2:synthesis of brent kung adder 71
Screen-5.3:properties of brent kung adder
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CHAPTER6
CONCLUSION&FUTURE SCOPE
6.1 CONCLUSION The transistor level implementation of prefix adders is simple, lesser power dissipation and high speed compared to other pass transistor logics. The tradeoffs of prefix adders are in terms of power dissipation and area. To design Brent Kung adder it requires less no of carry operators. so reduction in carry operators reduces tradeoffs of Brent kung adder compared to kogge stone adder, ripple carry adder &CLA.
6.2 FUTURE SCOPE In future we can reduce the grey boxes and black boxes to implement brent kung adder as a Harlcalson adder. In this we can reduce the number of levels. According to the levels it can take less time.
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