1. Ent Entit ity y pgb pgblo lock ck is Port ( a: in std_logic; b: in std_logic; g0 : out std_logic; p0: out std_logic); end pgblock; architecture Behavioral o o pgcell pgcell is g0 !"( a and b); p0 !" (a #or b); end behavioral;
$. ent entit ity y blac blackc kcel elll is port (g0 (g0 : in std_logic; p0 : in std_logic; g1 : in std_logic; p1 : in std_logic; % : out &'_*%+,; &'_*%+,; P : out &'_*%+,); &'_*%+,); end blackcell ; architecture Behavioral o blackcell is % !"( g1 or(g0 and p1)); P !" (p0 and p1); End behavioral;
-. Entity SUMBLOCK is
port ( P: in std_logic; c: in std_logic su : out std_logic); end sublock; architecture Behavioral o sublock is su !" (P #or c); end behavioral;
/. Entity buer is Port ( % : in std_logic; c : out std_logic); end buer; architecture Behavioral o buer is c :" %; end behavioral;
entity Brent_kung is Port ( a : in &'_*%+,_E,'*2 (13 do4nto 0);
b : in &'_*%+,_E,'*2 (13 do4nto 0); cin : in &'_*%+,; su : out &'_*%+,_E,'*2 (13 do4nto 0); cout : out &'_*%+,); end Brent_kung;
architecture Behavioral o Brent_kung is coponent buer is Port (% : in std_logic; c : out std_logic); end coponent;
,oponent blackcell is Port ( g0 : in std_logic; p0 : in std_logic; g1 : in std_logic; p1 : in std_logic; % : out &'_*%+,; P : out &'_*%+,); end ,oponent;
,oponent pgblock is Port ( a : in &'_*%+,_E,'*2 (13 do4nto 0); b : in &'_*%+,_E,'*2 (13do4nto 0); g0 : out &'_*%+,_E,'*2 (13 do4nto 0); p0 : out &'_*%+,_E,'*2 (13 do4nto 0));
end ,oponent; coponent SUMBLOCK is port ( P: in std_logic; c: in std_logic su : out std_logic); end coponent;
signal %15P1: std_logic_vector(6 do4nto 0); signal %$5 P$: std_logic(- do4nto 0); signal %-5P- : std_logic_vector(1 do4nto 0); signal %/5P/ : std_logic; signal %35P3 : std_logic_vector($ do4nto 0); signal %75P7: std_logic_vector (7 do4nto 0); signal g05p0: std_logic_vector(13 do4nto 0); signal c : std_logic_vector(1/ do4nto 0);
begin
k0: pgblock port ap (a(0)5b(0)5g0(0)5p0(0)); k1 : pgblock port ap (a(1)5b(1)5g0(1)5p0(1)); k$: pgblock port ap (a($)5b($)5g0($)5p0($)); k- : pgblock port ap (a(-)5b(-)5g0(-)5p0(-)); k/: pgblock port ap (a(/)5b(/)5g0(/)5p0(/)); k3 : pgblock port ap (a(3)5b(3)5g0(3)5p0(3)); k7 : pgblock port ap (a(7)5b(7)5g0(7)5p0(7)); k6 : pgblock port ap (a(8)5b(8)5g0(8)5p0(8));
k8 : pgblock port ap (a(8)5b(8)5g0(8)5p0(8)); k9 : pgblock port ap (a(9)5b(9)5g0(9)5p0(9)); k10: pgblock port ap (a(10)5b(10)5g0(10)5p0(10)); k11: pgblock port ap (a(11)5b(11)5g0(11)5p0(11)); k1$ : pgblock port ap (a(1$)5b(1$)5g0(1$)5p0(1$)); k1- : pgblock port ap (a(1-)5b(1-)5g0(1-)5p0(1-)); k1/: pgblock port ap (a(1/)5b(1/)5g0(1/)5p0(1/)); k13: pgblock port ap (a(13)5b(13)5g0(13)5p0(13)); s1: graycell port ap (g0(0)5p0(0)5cin5%,(0)); s1: blackcell port ap (g0(0)5 p0(0)5 g1(1)5 p1(1)5 %1(0)5P1(0)); s$: blackcell port ap (g0($)5 p0($)5 g1(-)5 p1(-)5 %1(1)5P1(1)); s-: blackcell port ap (g0(/)5 p0(/)5 g1(3)5 p1(3)5 %1($)5P1($)); s/: blackcell port ap (g0(7)5 p0(7)5 g1(6)5 p1(6)5 %1(-)5P1(-)); s3: blackcell port ap (g0(8)5 p0(8)5 g1(9)5 p1(9)5 %1(/)5P1(/)); s7: blackcell port ap (g0(10)5 p0(10)5 g1(11)5 p1(11)5 %1(3)5P1(3)); s6: blackcell port ap (g0(1$)5 p0(1$)5 g1(1-)5 p1(1-)5 %1(7)5P1(7)); s8: blackcell port ap (g0(1/)5 p0(/)5 g1(13)5 p1(13)5 %1(6)5P1(6)); s9: blackcell port ap ( %1(0)5P1(0)5 %1(1)5P1(15) %$(0)5P$(0)); s10: blackcell port ap ( %1($)5P1($)5 %1(-)5P1(-) 5%$(1)5P$(1)); s11: blackcell port ap ( %1(/)5P1(/)5 %1(3)5P1(3) 5%$($)5P$($)); s1$: blackcell port ap ( %1(7)5P1(7)5 %1(6)5P161)5 %$(-)5P$(-)); s1-: blackcell port ap (%$(0)5P$(0) 5%$(1)5P$(1)5 %-(0)5P-(0)); s1/: blackcell port ap (%$($)5P$($) 5%$(-)5P$(-)5 %-(1)5P-(1)); s13: blackcell port ap (%$($)5P$($)5 %-(0)5P-(0)5%/(0)5P/(0)); s17: blackcell port ap (%-(0)5P-(0)5 %-(1)5P-(1)5%/(1)5P/(1)); s16: blackcell port ap (%$(0)5P$(0)5 %1($)5P1($)5%3(0)5P3(0));
s18: blackcell port ap (%-(0)5P-(0)5 %1(3)5P1(3)5%3(1)5P3(1)); s19: blackcell port ap (%/(0)5P/(0)5 %1(7)5P1(7)5%3($)5P3($)); s$0: blackcell port ap (%1(0)5P1(0)5g0($)5p0($)5%7(0)5P7(0)); s$1: blackcell port ap (%$(0)5P$(0)5g0(/)5p0(/)5%7(1)5P7(1)); s$$: blackcell port ap (%3(0)5P3(0)5g0(7)5p0(7)5%7($)5P7($)); s$-: blackcell port ap (%-(0)5P1(0)5g0(8)5p0(8)5%7(-)5P7(-)); s$/: blackcell port ap(%3(1)5P3(1)5g0(10)5p0(10)5%7(/)5P7(/)); s$3: blackcell port ap (%/(0)5P1(0)5g0(1$)5p0(1$)5%7(3)5P7(3)); s$7: blackcell port ap (%3($)5P3($)5g0(1/)5p0(1/)5%7(7)5P7(7));
t1 : buer portap (g0(0)5c(0)); t$ : buer port ap (%1(0)5c(1)); t- : buer port ap (%7(0)5c($)); t/ : buer port ap (%$(0)5c(-)); t3 : buer port ap (%7(1)5c(/)); t7 : buer port ap (%3(0)5c(3)); t6 : buer port ap (%7($)5c(7)); t8 : buer port ap (%-(0)5c(6)); t9 : buer port ap (%7(-)5c(8)); t10 : buer port ap (%3(1)5c(9)); t11 : buer port ap (%7(/)5c(10)); t1$ : buer port ap (%/(0)5c(11)); t1- : buer port ap (%7(3)5 c(1$)); t1/ : buer port ap (%3($)5c(1-)); t13 : buer port ap (%7(7)5c(1/));
t17 : buer port ap (%/(1)5cout);
1 : sublock port ap (P(0)5c(0)5su(0)); $: sublock port ap (P(1)5c(1)5su(1)); -: sublock port ap (P($)5c($)5su($)); /: sublock port ap (P(-)5c(-)5su(-)); 3: sublock port ap (P(/)5c(/)5su(/)); 7: sublock port ap (P(3)5c(3)5su(3)); 6: sublock port ap (P(7)5c(7)5su(7)); 8: sublock port ap (P(6)5c(6)5su(6)); 9: sublock port ap (P8)5c(8)5su(8)); 10: sublock port ap (P(9)5c(9)5su(9)); 11: sublock port ap (P(10)5c(10)5su(10)); 1$: sublock port ap (P(11)5c(11)5su(11)); 1-: sublock port ap (P(1$)5c(1$)5su(1$)); 1/: sublock port ap (P(1-)5c(1-)5su(1-)); 13: sublock port ap (P(1/)5c(1/)5su(1/)); 17: sublock port ap (P(13)5cout5su(13)); end behavioral;
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