3 bit adder

2013

Layout Design of 3-bit adder PUSHKAR CHAUDHARY

Y9227445

AVIRUP DASGUPTA

Y9227159

Abstract: Layout of a 3-bit adder is designed using the tool Design Architect. An adder can have different designs i.e. Ripple Adder, Mirror adder, Bypass adder, Linear select adder etc. Ripple adder is most efficient in terms of delay if the number of bits of inputs is less than 5. If the number of input bits become more than 5 then Ripple adder becomes less efficient than other adders.

Introduction: In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s), but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations. A 3-bit adder has two or more inputs and the outputs are a 3-bit number and a carry. Each input of a 3-bit adder can be as high as the decimal number 7. A 3-bit adder is consists of 1 half-adder and 2 full adders.

Half Adder: A half-adder also computes the addition of numbers but it doesn’t take ‘carry’ as an input. Let A and B are two one bit numbers, then A and B both can be either ‘0’ or ‘1’.

Sum = A+B Then making truth table: A

B

Sum

Carry

0 0

0 1

0 1

0 0

1 1

0 1

1 0

0 1

Using K-Map, we get Sum = A xor B Carry = A and B

Implementing the logic using gates :

Full-adder: Full adder is like a half- adder but it also takes an extra input ‘Cin’. The truth table can be written as A

B

Cin

Sum

Cout

0 0

0 0

0 1

0 1

0 0

0 0

1 1

0 1

1 0

0 1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Using K-Map we get Sum = A xor B xor Cin Cout = (A and B) or (B and Cin) or (Cin and A)

The above logic can be implemented as

3-Bit adder: It consists of 1 half-adder and 2 half adders. Input to the 3-bit adder are two numbers A and B and the output is their sum.

Layout Design: Techniques used: 1. Finger like structures of mosfet are used to minimise the capacitances and get a better aspect ratio.

2. Multiple contacts are used to reduce the contact resistance

3. Structures are given a square shape to minimize the area and hence capacitance.

4. Structures arranged so as to minimize the use of metal.

5. Wherever necessary vias are used to go from one metal layer to other in order to minimise the use of metal.

Gate Level Layouts:

Layout and Schematic of a XOR gate are shown side to side:

Note that inverters for are built into the XOR layout for inverting the input signals A and B, wherever required.

Layout and Schematic of a NAND gate are shown side to side

Layout and Schematic of NOR gate are shown side to side

Layout of Half-Adder:

Layout of Full Adder:

Layout of the 3-bit adder:

Simulation and plots: Half-Adder:

Full-Adder:

Output of the 3-bit adder:

Softwares used: 

IC studio by Mentor Graphics and LASI (Layout Software for Individuals) for layouts



ModelSim and IC studio (by Mentor Graphics) for simulations