4 Bit Brent Kung Adder

--*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*----OPARVersion1Synthesis(Demo) ---Additionneurdedelaiimposé4traverséesde"BK" --synthesisedSunday,25September2011 ---*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-libraryIEEE; useIEEE.STD_LOGIC_1164.All; entityCLAdderis port(A,B:inStd_Logic_Vector(3downto0);--A,B:addends S:outStd_Logic_Vector(3downto0);--S:Sum; Cout:outStd_Logic);--carryout endCLAdder; architecturestructuralofCLAdderis --G(ii)(jj),P(ii)(jj):"groupGenerate","groupPropagate".ii=groupleftp osition,jj=grouprightposition typeTrisarray(3downto0)ofStd_Logic_Vector(3downto0); signalG,P:Tr; procedureHA (signalG,P:outStd_Logic;signalA,B:inStd_Logic)is beginG<=AandB;P<=AxorB;endHA; procedureBK (signalGO,PO:outStd_Logic;signalGI1,PI1,GI2,PI2:inStd_Logic)is beginGO<=GI1or(PI1andGI2);PO<=PI1andPI2;endBK; begin --"HA"cellsrow HA(G(03)(03),P(03)(03),A(03),B(03)); HA(G(02)(02),P(02)(02),A(02),B(02)); HA(G(01)(01),P(01)(01),A(01),B(01)); HA(G(00)(00),P(00)(00),A(00),B(00)); --"BK"cellsrow1 --"BK"cellsrow2 BK(G(01)(00),P(01)(00),G(01)(01),P(01)(01),G(00)(00),P(00)(00)); --"BK"cellsrow3 BK(G(02)(00),P(02)(00),G(02)(02),P(02)(02),G(01)(00),P(01)(00)); --"BK"cellsrow4 BK(G(03)(00),P(03)(00),G(03)(03),P(03)(03),G(02)(00),P(02)(00)); --"XOR"gatesrow Cout<=G(03)(00); S(03)<=P(03)(03)xorG(02)(00); S(02)<=P(02)(02)xorG(01)(00); S(01)<=P(01)(01)xorG(00)(00); S(00)<=P(00)(00); endstructural;