Verilog Code for Car Parking System - FPGA4student

3/25/2018

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Verilog code for Car Parking System - FPGA4student.com

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Verilog code for Car Parking System

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This simple project is to implement a car parking system in Verilog. The Verilog code for code for the car parking system is fully presented. In the entrance of the parking system, system, there is a sensor which which is activated to detect a vehicle coming. Once the sensor is triggered, a password is requested to open the gate. If the entered password is correct, the gate would open to let the vehicle get in. Otherwise, the gate is still locked. If the current car is getting in the car park being detec d etected ted by the exit sensor and another the car comes, the door will be locked and requires the coming car to enter passwords.

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Popular FPGA pr Image pr FPGA usi This proje show det process a FPGA using Verilog fro bitmap image (.bmp), p w... Verilog co single cyc processor In this pro single-cy processor is implement HDL. MIPS is an RISC which is widely used b

Verilog code for the car parking system: system:

// fpga4student.com FPGA projects, projects , Verilog projects, projects , VHDL projects // Verilog // Verilog project project: : Verilog Verilo g code for car parki parking ng system `timescale 1ns / 1ps module parking_system( input clk,reset_n, input sensor_entrance, sensor_exit, input [1:0] password_1, password_2, output wire GREEN_LED,RED_LED, output reg [6:0] HEX_1, HEX_2 ); parameter IDLE = 3'b000 , WAIT_PASSWORD = 3'b001 , WRONG_PASS = 3'b010 , RIGHT_PASS // Moore FSM : output just depends on the current state reg[2:0] current_state, next_state; reg[31:0] counter_wait; counter_wait; reg red_tmp,green_tmp; // Next state always @(posedge clk or negedge reset_n) begin if(~reset_n) current_state = IDLE; else current_state = next_state; end // counter_wait always @(posedge clk or negedge reset_n) begin if(~reset_n) counter_wait <= 0; else if(current_state ==WAIT_PASSWORD ) counter_wait <= <= counter_wait counter_wait + 1; else counter_wait <= 0; end // change state // fpga4student.com FPGA projects, Verilog projects, VHDL projects always @(* @(*) begin case(current_state) IDLE: begin if(sensor_entrance == 1) next_state = WAIT_PASSWORD ; else next_state = IDLE; end http://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html

Verilog C RISC Pro In this V e Verilog co RISC pro presented. The RISC designed based on its i VHDL co Segment 3 FPGA Last time FPGA tut control the 4-digit 7-se Basys 3 FPGA. A full V displayi... [FPGA Tu Segment Basys 3 F This FPG guide you the 4-digit seven-segm Basys 3 FPGA Board. controller will be ... A comple Microcont In this VH VHDL co microcont presented. The 8-bit mi designed, implemented a... Verilog co controller A Verilog traffic ligh FPGA is sensor on the farm is t are any vehicles...

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WAIT_PASSWORD: begin if(counter_wait <= 3) next_state = WAIT_PASSWORD ; else begin if((password_1 ==2'b01)&&(password_2==2'b10)) next_state = RIGHT_PASS ; else next_state = WRONG_PASS ; end end WRONG_PASS: begin if((password_1 ==2'b01)&&(password_2==2'b10)) next_state = RIGHT_PASS ; else next_state = WRONG_PASS ; end RIGHT_PASS: begin if(sensor_entrance ==1 && sensor_exit == 1) next_state = STOP; else if(sensor_exit == 1) next_state = IDLE; else next_state = RIGHT_PASS ; end STOP: begin if((password_1 ==2'b01)&&(password_2==2'b10)) next_state = RIGHT_PASS ; else next_state = STOP; end default: next_state = IDLE; endcase end // LEDs and output, change the period of blinking LEDs here always @(posedge clk) begin case(current_state) IDLE: begin green_tmp = 1'b0; red_tmp = 1'b0; HEX_1 = 7'b1111111 ; // off HEX_2 = 7'b1111111 ; // off end WAIT_PASSWORD: begin green_tmp = 1'b0; red_tmp = 1'b1; HEX_1 = 7'b000_0110; // E HEX_2 = 7'b010_1011; // n end WRONG_PASS: begin green_tmp = 1'b0; red_tmp = ~red_tmp; HEX_1 = 7'b000_0110; // E HEX_2 = 7'b000_0110; // E end RIGHT_PASS: begin green_tmp = ~green_tmp; red_tmp = 1'b0; HEX_1 = 7'b000_0010; // 6 HEX_2 = 7'b100_0000; // 0 end STOP: begin green_tmp = 1'b0; red_tmp = ~red_tmp; HEX_1 = 7'b001_0010; // 5 HEX_2 = 7'b000_1100; // P end endcase end assign RED_LED = red_tmp ; assign GREEN_LED = green_tmp; endmodule

Testbench Verilog code for car parking system: `timescale 1ns / 1ps // fpga4student.com FPGA projects, Verilog projects, VHDL projects // Verilog project: Verilog code for car parking system module tb_parking_system;

// Inputs http://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html

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reg clk; reg reset_n; reg sensor_entrance; reg sensor_exit; reg [1:0] password_1; reg [1:0] password_2;

// Outputs wire GREEN_LED; wire RED_LED; wire [6:0] HEX_1; wire [6:0] HEX_2; // fpga4student.com FPGA projects, Verilog projects, VHDL projects // Instantiate the Unit Under Test (UUT) parking_system uut ( .clk(clk), .reset_n(reset_n), .sensor_entrance(sensor_entrance), .sensor_exit(sensor_exit), .password_1(password_1), .password_2(password_2), .GREEN_LED (GREEN_LED), .RED_LED (RED_LED), .HEX_1(HEX_1), .HEX_2(HEX_2) ); initial begin clk = 0; forever #10 clk = ~clk; end initial begin // Initialize Inputs reset_n = 0; sensor_entrance = 0; sensor_exit = 0; password_1 = 0; password_2 = 0; // Wait 100 ns for global reset to finish #100; reset_n = 1; #20; sensor_entrance = 1; #1000; sensor_entrance = 0; password_1 = 1; password_2 = 2; #2000; sensor_exit =1; // Add stimulus here // fpga4student.com FPGA projects, Verilog projects, VHDL projects end endmodule Simulation waveform for the car parking system in Verilog:

Car Parking System in VHDL What is FPGA Programming? FPGA vs Software programming Recommended and affordable Xilinx FPGA boards for students Recommended and affordable Altera FPGA boards for students Recommended Verilog projects: 1. What is an FPGA? How Verilog works on FPGA 2. Verilog code for FIFO memory 3. Verilog code for 16-bit single-cycle MIPS processor 4. Programmable Digital Delay Timer in Verilog HDL 5. Verilog code for basic logic components in digital circuits 6. Verilog code for 32-bit Unsigned Divider 7. Verilog code for Fixed-Point Matrix Multiplication 8. Plate License Recognition in Verilog HDL 9. Verilog code for Carry-Look-Ahead Multiplier 10. Verilog code for a Microcontroller 11. Verilog code for 4x4 Multiplier 12. Verilog code for Car Parking System http://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html

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10 comments: Unknown May 1, 2017 at 11:45 PM what type of sensor are we using? Reply

Anonymous May 1, 2017 at 11:49 PM In this code, the sensor is modeled as a switch for simulation only. Reply

hamza ahmad November 5, 2017 at 3:17 PM I want to do this project by Gate level modeling.It is possible??? Reply Replies Van Loi Le November 9, 2017 at 5:57 PM Absolutely can. However, you have to create state table and obtain the Boolean equations from K-maps. Then, based on the equations to write the structural code for t he project. Reply

Sid November 12, 2017 at 1:03 PM What is the role of HEX_1 and HEX_2? Reply Replies Van Loi Le November 12, 2017 at 11:03 PM Display the state of the system Reply

rama venkata raghunadh siram November 18, 2017 at 10:21 PM in this sensor exit=1 represents the car is leaving from the parking place?

http://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html

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Verilog code for Car Parking System - FPGA4student.com Reply Replies Van Loi Le November 19, 2017 at 3:05 AM Leaving the gate of the car park. Reply

Vinod Kumar January 28, 2018 at 7:48 AM What are all the requirements for this project? h/w and s/ w? TIA Reply

Unknown February 28, 2018 at 4:13 AM what is the role of green_led & red_led? Reply

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