FIR FIL FI LTER DESIGN DES IGN USING US ING VERILOG VE RILOG
FIR filters filters are is widely widely used in in different different applications such as as biomedical, biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.
Filters play an important role for removal of unwanted signal or noise from original input Filters play signal by removing the selected frequencies from incoming signal. They became much popular due to the increase of the digital digital signal processing.
Comparison between FIR and IIR Filters The non recursive FIR! and recursive IIR! filters have different characteristics for numbers of applications. The non recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table ".# below shows the comparison between FIR and IIR filters.
IIR $ore %fficient 'nalog %quivalent
FIR
&ess %fficient (o 'nalog %quivalent
$ay )e *nstable (on&inear -hase Response (o %fficiency ained by /ecimation
VERILOG CODE FOR FIR FILTER 00 main module FIR module filterfirclk,rst,1,dataout!2 input 3456712 input clk,rst2 output 38567dataout2 wire 34567d#,d",d92 wire 34567m#,m",m9,m:,m;2 wire 34567d##,d#",d#9,d#:2 parameter h6<9=b#6#2 parameter h#<9=b#662 parameter h"<9=b6##2 parameter h9<9=b6#62 parameter h:<9=b66#2 assign m#<1>>h62 dff u"clk,rst,1,d##!2 assign m">h#2 assign d#>h"2 assign d">h92 assign d9>h:2
'lways +table &inear -hase Response /ecimation Increases %fficiency
assign dataout
module dffclk,rst,d,q!200 sub module d flipflop input clk,rst2 input 34567d2 output 34567q2 reg 34567q2 alwaysBposedge clk! begin ifrst<<#! begin q<62 end else begin q
// ,e!ision 001 - 'ile Created // .dditional Comments: // //////////////////////////////////////////////////////////////////////////////// module tst // *nputs reg $l reg rst reg 7:0 ( // 3utputs ire 9:0 dataout // *nstantiate t5e 6nit 6nder %est 66%8 filterfir uut $l$l8 rstrst8 ((8 dataoutdataout8 8 initial )egin // *nitialie *nputs $l ; 0 rst ; 0 ( ; 0 <100 rst ; 1 <100 rst ; 0 ( ; =>d? <100 ( ; =>d10 <100 ( ; =>d12 <100 ( ; =>d1? <100 ( ; =>d1@
<100
end alays )egin
module fr_flter( input clock, input reet, input !ire"#$%&' input_mple, output re)"#$%&' output_mple*+ prmeter N #-+ re) i)ned"#$%&' coe."#/%&'+ re) "#$%&' 0older1e2ore"#/%&'+ !ire "#$%&' to3dd"#/%&'+ l!4 5(6* 7e)in coe."&'8-9$+ coe."#'#+ coe."/':-8$8+ coe."-'-+ coe.";';#9#+ coe."$';+ coe."8'/<;&;+ coe."9';+ coe."<';#9#+ coe."='-+ coe."#&':-8$8+ coe."##'#+ coe."#/'8-9$+ end )en>r i+ )enerte 2or (i&+ i?N+ ii@#* 7e)in% mult multiplier mult#( Adt(coe."i'*, Adt7(0older1e2ore"i'*, Areult(to3dd"i'**+ end end)enerte
l!4 5(poed)e clock or poed)e reet* 7e)in i2(reet* 7e)in 0older1e2ore"#/' ? &+ 0older1e2ore"##' ? &+ 0older1e2ore"#&' ? &+ 0older1e2ore"=' ? &+ 0older1e2ore"<' ? &+ 0older1e2ore"9' ? &+ 0older1e2ore"8' ? &+ 0older1e2ore"$' ? &+ 0older1e2ore";' ? &+ 0older1e2ore"-' ? &+ 0older1e2ore"/' ? &+ 0older1e2ore"#' ? &+ 0older1e2ore"&' ? &+ output_mple ? &+ end ele 7e)in 0older1e2ore"#/' ? 0older1e2ore"##'+ 0older1e2ore"##' ? 0older1e2ore"#&'+ 0older1e2ore"#&' ? 0older1e2ore"='+ 0older1e2ore"=' ? 0older1e2ore"<'+ 0older1e2ore"<' ? 0older1e2ore"9'+ 0older1e2ore"9' ? 0older1e2ore"8'+ 0older1e2ore"8' ? 0older1e2ore"$'+ 0older1e2ore"$' ? 0older1e2ore";'+ 0older1e2ore";' ? 0older1e2ore"-'+ 0older1e2ore"-' ? 0older1e2ore"/'+ 0older1e2ore"/' ? 0older1e2ore"#'+ 0older1e2ore"#' ? 0older1e2ore"&'+ 0older1e2ore"&' ? input_mple+ output_mple ? (input_mple @ to3dd"&' @ to3dd"#' @ to3dd"/' @ to3dd"-' @ to3dd";' @ to3dd"$' @ to3dd"8' @ to3dd"9' @ to3dd"<' @ to3dd"=' @ to3dd"#&' @ to3dd"##' @ to3dd"#/'*+ end end
endmodule
