A study and Analysis of Parameters of Two Stage Single Ended CMOS Amplifier Dilip Mathuria Department of Electronics and Communication Sharda University Greater Noida, India
Abstract This paper presents a CMOS two stage single ended operational amplifier, which operates at +5V and -1V power supply. The Op-Amp Op -Amp designed has two stages and a single ended output. CMOS has its structure similar to PMOS and NMOS but in this both PMOS and NMOS are fabricated on same chip so due to power dissipation is less and speed high. In this paper pa per we have focused on the various parameters p arameters like Gain, and slew rate of CMOS based two stage single ended operational amplifiers under 0.35um CMOS technology. The design is carried out using PSPICE tool.
Keywords Op-Amp, Slew Rate, CMOS, Pspice Tool, Frequency Response, 0.35um
1. Introduction An operational amplifier (often op-amp or opamp) is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output. Operational Amplifiers are one of the most commonly used building blocks of electronic circuits. Design of a stable operational amplifier with a high gain and high unity gain bandwidth with continuously reducing power supply and channel length is a major challenge. There is always a trade-off among various parameters such as bandwidth, speed, gain, power dissipation. With higher gain and bandwidth the speed and accuracy of the amplifier increases but the stability in negative feedback decreases. Aim is to build an op-amp with a fairly high gain and unity gain bandwidth at a maximum phase margin to ensure stability.
2. Literature Review In the year of 2002, IEEE Journal of solid state circuits, Fully Integrated CMOS two stage Amplifier Designed Using the Distributed Active-Transformer Architecture. A novel fully integrated single-stage circular geometry active-trans- former (DAT) power amplifier implemented in a low-voltage CMOS process
Prof. A.K. Singh Department of Electronics and Communication Sharda University Greater Noida, India achieves 1.9-W output power with 41% (31% single ended) PAE at 2.4 GHz. In the year of 2007 IEEE Custom Integrated Circuits Conference (CICC), A fully integrated 90nm CMOS PA capable of delivering 6.7 dBm of linear power in the 60 GHz band has been demonstrated. In 2010 IEEE International Conference, The paper presented a 2.4 GHz fully integrated CMOS power amplifier using capacitive cross coupling, fabricated in 0.18μm CMOS with 3.3V supply voltage. In October 2012, a fully integrated linear and efficient PA in 0.25 μm SiGe:C BiCMOS technology is presented and works at 2 GHz with a supply voltage of 2.5 V. The experimental results show a gain of 13 dB and a maximum output power of 23 dBm with a PAE of 38%.
3. Two Stage Single Ended CMOS Op-Amp Two stage operational amplifiers consist of a differential amplifier in the 1st stage followed by a common source amplifier in the 2nd stage. Differential amplifier stage is to ensure high gain and common source amplifier stage is to further increase the gain an also provide high voltage swing at the output. The block diagram of a two stage operational amplifier is shown in figure 1.
Figure 1:- Two Stage Amplifier The 1st block is a differential amplifier. amplifier. It has two inputs, an inverting input and non-inverting input. It can give a differential voltage or single ended voltage, depending on the configuration at the output which depends on differential input voltage. Single ended output degrades the output swing of the amplifier. Also the Common Mode Rejection Ratio degrades as the symmetry of the circuit is lost.
4. Circuit Implementation
higher gain as compared to passive loads. The differential current from M1 and M2 multiplied by the output resistances of the input stage gives the single-ended output voltage, which is fed as input to the next stage.
6. Common Source Amplifier Stage
Figure 2:- Design Procedure of Op-amp The circuit comprises of three subparts: the differential gain stage, second gain stage and biasing circuit. MOSFETS M1, M2, M3, M4, M5 form the differential amplifier stage. M6 and M7 form the second gain stage and are in Common Source Amplifier Configuration. M8 and the Current source form the biasing circuitry. The values of different circuit elements are: Current source, I=5μA
Capacitor=4 and 4.5 pF Resistance=2.2KΩ
The second stage is a common source topology amplifier. The purpose of the second stage is to provide additional gain and a high output swing. It is made up of transistors M6 and M7. The output from the drain of M2 is fed as input to the gate of M6. The MOSFET M7 serves as load to the driver MOSFET M6. The gain of this stage is given by: GAIN2 = (gmM6 +gmbM6)(ro6 || ro7 ) = [(gmM6 +gmbM6)*ro6*ro7] / ( ro6 + ro7) Where, gmM2= Trans conductance of M6 gmbM2= back gate Trans conductance of M6 Therefore, total gain at the output of the op-amp is: GAIN = GAIN1*GAIN2 = (gmM2 +gmbM2 )(gmM6 +gmbM6)(ro6 || ro7)(ro2 || ro4)
7. Biasing Circuitry Current source, Is in figure 3 acts as a reference source for transistor M8. Is and M8 form a current mirror biasing network driving the transistors, M5 and M7 which act as current sinks. The gate to source voltage of M5 and M7 is controlled by this bias network. 8. RC Compensation Rc and Cc are used between gate and drain of M6 to improve the phase margin and hence stability of the circuit.
Figure 3:- two stage amplifier topology
5. Differential Gain Stage
9. Design of the Circuit The circuit was designed to meet the following specifications as in table.
It is made up of MOSFETS M1, M2, M3, M4 and M5 as shown in Figure 3. Positive input is given to the gate of M1 and negative input is given to the gate of M2. M3 and M4 from the PMOS current mirror load of this stage. The gain of this stage is given by: GAIN1 = (gmM2 +gmbM2)(ro2 || ro4) = [(gmM2 +gmbM2)*ro2*ro4] / ( ro 2 + ro4) Where, gmM2= Trans conductance of M2 gmbM2= back gate Trans conductance of M2 The current mirror load provides for conversion of differential input to single ended output and also provides
Figure 4:- Two Stage Single Ended CMOS Op-Amp
Table: 1 W/L ratio of transistors in two stage single ended op-amp Transistor PMOS 1 PMOS 2 PMOS 3 PMOS 4 PMOS 5 NMOS 1 NMOS 2 NMOS 3
W/L Ratio 10/2 100/2 200/2 200/2 200/2 25/2 25/2 100/2
frequency the output signal becomes inverted, or anti phase in relation to the input.
11. Simulation Results The output waveform of two stage single ended CMOS operational amplifier using PSPICE tool is shown in figure 6.
10. Design Parameter SLEW RATE: slew rate is defined as the maximum rate of change of output voltage per unit of time and is expressed as volt per second. Limitations in slew rate capability can give rise to nonlinear effects in electronic amplifiers.
SR = max (|dvout(t)/dt|)
Figure 6:- Output waveform of the circuit Frequency Response
Figure 7:- .Frequency response at L=0.35um Slew Rate
Figure 5:- Slew rate effect on a square wave: red = desired output, green = actual output GAIN: Gain is a measure of the ability of a two port
circuit (often an amplifier) to increase the power or amplitude of a signal from the input to the output port by adding energy converted from some power supply to the signal. It is usually defined as the mean ratio of the signal amplitude or power at the output port to the amplitude or power at the input port. It is often expressed using the logarithmic decibel (dB) units ("dB gain"). PHASE MARGIN: The phase margin (PM) is the
difference between the phase, measured in degrees, and 180°, for an amplifier's output signal (relative to its input), as a function of frequency. Typically the openloop phase lag (relative to input) varies with frequency, progressively increasing to exceed 180°, at which
Figure 8:-. Slew rate at L=0.35um
12. Conclusion This work presents a study and analysis of the two stage single ended CMOS operational amplifier using 0.35 μm CMOS technologies. The circuits named two -
stage single ended op-amp have been simulated in PSPICE tool. The variation of parameters like gain, phase margin and slew rate with respect to input voltage and VDD has been simulated using the tool. For the twostage op-amp in 0.35 μm technologies with Vdd=5v and Vss=-1v, gain is 24 dB, phase margin is 120 degrees and slew rate 4.54V/us for rising edge has been observed. Hence from present study we conclude that with increasing in channel length of transistor gain decreases but slew rate increases. Hence it is a challenge for designer to increase the gain with use of nanotechnology of CMOS in channel length of transistor. Results have demonstrated that the proposed design is both effective and practical.
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