PID CONTROLLER
CHAPTER 1 INTRODUCTION
Since the Years 60, the law of Moore predicts that the complexity in terms of builtin circuit transistors doubles every two years, remain verified. The programmable FPGA circuits (Field Programmable Gate Array) didn't escape to this law. Since the the firs firstt FPGA FPGA,, deve develo lope ped d like like an evol evolut utio ion n natu natura rall of the the CPLD CPLD (Com (Compl plex ex Programmable Logic Devices), these circuits didn't stop winning in complexity and inte integr grat ated ed henc hencef efor orth th unti untill one bill billio ion n of tran transi sist stor orss for for the the most most rece recent nt generations. This increase of the integration level resulted in a similar growth of the power of calculation of these circuits. The FPGAs have been used then to make the fast samples of ASICs (Application Spec Specif ific ic Inte Integr grat ated ed Circ Circui uits) ts) and and find find sinc sincee some some year yearss thei theirr plac placee in many many domains of applications. However, the order of the processes industrial requires more and more elements of powerful calculations. This type of order is in the same way way in perp perpet etua uall evol evolut utio ion n with with the the deve develo lopm pmen entt of the the nume numeri ricc circ circui uits ts of calculation. Thus, the PID controllers represent the majority of the controllers used in the industrial systems control. Of this fact, it will be necessary to digitalize the PID algorithm. The The modern modern digi digital tal contr control ol syste systems ms requir requiree more more and and more more strong strong and fastes fastestt calculation components. This type of elements becomes yet indispensable with the utilization of some new control algorithms like the fuzzy control, the adaptive control, the sliding mode control… Although the PID controllers are the oldest they represent the most used controllers in the industrial control systems.
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PID CONTROLLER
The PID controllers to be implemented in FPGA systems, first needs to digitized. The The digit digital al PID contro controlle llerr equat equation ionss are modele modeled d using using Veril Verilog og HDL. HDL. Severa Severall other HDLs like VHDL are also available, the Verilog HDL is selected for it’s popularity and simplicity. The Verilog HDL supports three distinct modeling metho methods ds like like datafl dataflow, ow, struct structura urall and and behav behavior ioral. al. In this this design design a mixed mixed level level modeling of PID controller is proposed.
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PID CONTROLLER
Chapter 2
PROPOSED MECHANISM The main objective of our mini project is to develop an efficient and low cost PID controller using Verilog hdl. Our controller may be used to control any parameter of a vehicle such as speed, rear mirror control. Here we take speed, the most sensitive parameter to be controlled using our PID controller. Available controllers are high cost and less effective. Such controllers may not be affordable by small scale industries. Need for a low cost and highly efficient reconfigurable controller arise in the market. The implementation using Verilog
HDL further reduces its complexity by reducing number of programming lines and decreasing the area used thus resulting in high area effectiveness.
Our project mainly focuses on: 1. PID Controller 2. Verilog HDL
2.1PID (PROPORTIONAL INTEGTRAL DERIVATIVE) CONTROLLER
In the control of dynamic systems, no controller has enjoyed both the success and the failure of the PID control. Of all control design techniques, the PID controller is the most widely used. Over 85% of all dynamic controllers are of the PID variety. There is actually a great variety of types and design methods for the PID
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controller.
What What is a PID PID cont contro roll ller er?? The The acro acrony nym m PID PID stan stands ds for for Proportional-IntegralDifferential control. Each of these, the P, the I and the D are terms in a control
algorithm algorithm and each has a special special purpose. Sometimes Sometimes certain certain of the terms are left out because they are not needed in the control design. This is possible to have a PI, PD or just a P control. It is very rare to have a ID control
2.2VERILOG HDL
Verilog digital logic simulator tools allow you to perform the following tasks in the design process without building a hardware prototype: - Determine the feasibility of new design ideas - Try more than one approach to a design problem - Verify functionality - Identify Identify design design problems. problems. Coupling Coupling HDL Compiler Compiler with logic synthesis synthesis tools, tools, you can automatically convert an HDL description to a gate-level implementation in a target technology. technology. - HDL descriptions provide technology independent independent documentation of a design and its its func functi tion onal alit ity. y. Sinc Sincee the the init initia iall HDL HDL desi design gn desc descri ript ptio ion n is tech techno nolo logy gy-independent, you can use it again to generate the design in a different technology, without having to translate from the original technology .
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Chapter 3 Digital PID Controller 3.1 PID CONTROLLER WORKING: A proportional–integral–derivative controller (PID controller) is a generic control loop feedback mechanism (controller) widely used in industrial control systems – a PID is the most commonly used feedback controller. A PID controller calculates an "error" value as the difference between a measured process variable and a desired set point. The controller attempts to minimize the error by adjusting the process control inputs.
The The PID PID cont contro roll ller er calc calcul ulat atio ion n (alg (algori orith thm) m) invo involv lves es thre threee sepa separat ratee cons consta tant nt parameters, and is accordingly sometimes called three-term control: the proportional, the integral and derivative values, denoted P, I, and D. Heuristically, these values can be interpreted in terms of time: P depends on the present error, I on the accumulation of past errors, and D is a prediction of future errors, based on current rate of change.[1] The weighted sum of these three actions is used to adjust the process via a control element such as the position of a control valve, or the power supplied to a heating heating element.
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In the the absenc absencee of knowl knowledg edgee of the the underl underlyin ying g proces process, s, a PID contr control oller ler has histo historic ricall ally y been been consid considere ered d to be the best best contro controlle ller.[2 r.[2]] By tuning tuning the three three parameters in the PID controller algorithm, the controller can provide control action designed for specific process requirements. The response of the controller can be described in terms of the responsiveness of the controller to an error, the degree to which the controller overshoots the set point and the degree of system oscillation. Note that the use of the PID algorithm for control does not guarantee optimal control of the system or system stability.
Some Some applic applicati ations ons may may requir requiree using using only only one one or two actions actions to provid providee the the appropriate system control. This is achieved by setting the other parameters to zero. A PID controller will be called a PI, PD, P or I controller in the absence of the respective control actions. PI controllers are fairly common, since derivative action is sensitive to measurement noise, whereas the absence of an integral term may prevent the system from reaching its target value due to the control action. To impr improv ovee the the spee speed d and and mini minimi mize ze the the cost cost whil whilee offe offeri ring ng clea clearl rly y good ood performances, the adopted
architecture
used
includes
essentially
three
combinational logic multiplier, one subtractor three adders and three registers.
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PID CONTROLLER
BLOCK DIAGRAM
3.1.1 P controller P controller can eliminate forced oscillations caused by use of on-off controller. However, a second problem arises. There exists now a steady state error. For a properly designed control system steady state error should be zero. With P controller that is possible if: a) K =
∞
b) u (t) = u0 The first alternative (K =
∞
) cannot be physically realized in any proportional
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band (PB) excerpt for PB = 0 [%] which leads leads back to on-off controller and forced forced oscillations. The second alternative (u(t) = u0) implies that it is possible to find u0 at every moment and that it is possible to satisfy condition u(t) = u0 for every given reference value r(t). This can be achieved if integral mode is added to P controller. In general it can be said that P controller cannot stabilize higher order processes. For the 1st order processes, meaning the processes with one energy storage, a large incre increase ase in gain gain can be tolera tolerated ted.. Propor Proportio tional nal contro controlle llerr can stabi stabiliz lizee only only 1 st Order Order unsta unstable ble proces process. s. Chang Changing ing contr controll oller er gain gain K can chang changee close closed d loop loop dynamics. A large controller gain will result in control system with: a) Smaller steady state error, i.e. better reference following
b) Faster dynamics, i.e. broader signal frequency band of the closed loop system and larger sensitivity with respect to measuring noise c) Smaller amplitude and phase margin
The proportional term ( P ) gives a system control input proportional with the error. Using only P control gives a stationary error in all cases except when the system control input is zero and the system process value equals the desired value. In Figure the stationary error in the system process value appears after a change in the desired value (ref). Using a too large P term gives an unstable system.
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3.1.2 PI controller The name comes from the term "manual reset" which marks a manual change of operating point or of "bias" u0 in order to eliminate error. PI controller performs this function automatically. The fact that u0 is replaced with an integral allows PI controller to eliminate steady state error. On the other hand, P controller cannot eliminate steady state error since it does not have any algorithm that would allow for the controller to increase control control signal signal u(t) in order order to increase controll controlled ed variable variable y(t) (assuming positive positive process gain) if in some moment t1 error e(t1) = const. > 0. Proportional control law stays constant in this case and it will not try to change a controlled variable in such manner that control error is diminished.
Integral action can occur in the controller only on purpose, by design. Integral action can be noted on the other parts of the control system (actuators, plant etc.). These components components may help help in diminishing diminishing steady state state error, but control control system system designer generally cannot tune this components.
The integral term ( I ) gives an addition from the sum of the previous errors to the system control input. The summing of the error will continue until the system SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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process value equals the desired value and this result in no stationary error when the reference is stable. The most common use of the
I term
is normally together
with the P term, called a PI controller. Using only the I term gives slow response and often an oscillating system. Figure shows the step responses to a
I and PI
controller. As seen the PI controller response have no stationary error and the controller response is very slow.
3.1.3 PD controller
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PID CONTROLLER
D mode is used when prediction of the error can improve control or when it necessary to stabilize the system. From the frequency characteristic of D element it can be be seen seen that that it has has phase phase lead lead of 90 90 . Thus, Thus, D eleme element nt will will move move freque frequency ncy chara characte cteris ristic tic of the open open loop loop Go(j ) furthe furtherr away from from the critic critical al point point (-1,j0) (-1,j0).. Often derivative is not taken from the error signal but from the system output variable. This is done to avoid effects of the sudden change of the reference input that will cause sudden change in the value of error signal. Sudden change in error signal will cause sudden change in control output. To avoid that it is suitable to design D mode to be proportional to the change of the output variable y (t). If there is a measuring noise present in y(t) will amplify this noise. Noise is usually higher frequency signal, so good remedy for the noise problem is use of low-pass filter in derivative channel that will insure derivative action only in the frequency band of interest and diminish negative effect of D mode on signal noise. The derivative term ( D) gives an addition from the rate of change in the error to the system control input. A rapid change in the error will give an addition to the system control input. This improves the response to a sudden change in the system state or reference value. The D term is typically used with the P or PI PI as a PD or PID D
controller. A to large D term usually gives an unstable system. Figure shows
and PD controller responses. The response of the PD controller gives a faster
rising system process value than the P controller. Note that the D term essentially behaves as a high pass filter on the error signal and thus easily introduces instability in a system and make it more sensitive to noise.
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3.1.4 PID controller The The PID contro controlle llerr perfo performs rms espec especial ially ly well well when when the syste system m has has first first order order dynamics (a single pole). Actually, in this case, the P controller is a state-feedback control! In general, for the system with first-order dynamics the PI control is sufficient, and the D is not needed. For the system with essentially second-order dynamics, the PD control corresponds to state feedback. The PID control generally works works well for these systems. The PID controller controller can also work for some systems systems of higher order. Generally speaking, the derivative term is beneficial when the time constants of the system differ by orders of magnitude. It is sometimes helpful when tight control of higher-order dynamics is required. This is because the higher order dynamics prevent the use of high proportional gain. The D provides damping and speeds up the transient response. SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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The PID controller, of course, is not the end-all of controllers. Sometimes the controller just won’t work very well. The following are cases when the PID control doesn doesn’t ’t perfor perform m well. well. In gener general, al, these these requir requiree the use of more more sophis sophistic ticate ated d methods of control.
•
Tight control of higher order process
•
Systems with long delay times. In this case, the derivative term is not helpful. A
“Smith predictor” is often used in this case. •
Systems with lightly damped oscillatory modes
•
Systems with large uncertainties or variations.
•
Systems with harmonic disturbances
High Highly ly coup couple led d multi ulti-i -inp nput ut,, coordination is important.
•
mult multii-ou outp tput ut
syst system ems— s—es espe peci cial ally ly
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wher wheree
PID CONTROLLER
3.1.5 Choice of the controller type 3.1.5.1P controller When P controller is used, large gain is needed to improve steady state error table system do not have a problems when large gain is used. Such systems are systems with one energy storage (1st order capacitive systems). If constant steady state error can be accepted with such processes, than P controller can be used. Small steady state errors can be accepted if sensor will give measured value with error or if importance of measured value is not too great anyway. Example of such system is liquid level control in tanks when exact approximate level of liquid sufficient for the proper plant operation. Also, in cascade control sometime it is not important if there is an error inside inner loop, so P controller can a good solution in such cases.
Derivative mode is not required if the process itself is fast or if the control system as whol wholee does does not not have have to be fast fast in resp respon onse se.. Proc Proces esse sess of 1st 1st orde orderr reac reactt immediately on the reference signal change, so it is not necessary to predict error (introduce D mode) or compensate for the steady state error (introduce I mode) if it is possible to achieve satisfactory steady state error using only P controller.
3.1.5.2 PD controller It is well known that thermal processes with good thermal insulation act almost as inte integr grat ator ors. s. Sinc Sincee insu insula lati tion on is good good and and ther therma mall loss losses es are are smal small, l, the the most most significant part of the energy that is led to the system is used temperature rise.
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PID CONTROLLER
Those processes allow for large gains so that integral mode in the controller is not needed. needed. These These processes processes can be described as different connections of thermal energ energy y storag storages. es. Therma Thermall energy energy is shifte shifted d from from one one storag storagee into into anoth another. er. In general, with such processes there is present a process dynamics with large inertia. Since dynamics is slow, derivative mode is required for control of such processes. Integral mode would only already slow dynamics make more slowly. The other reason for using PD controllers in such systems is that is possible to measure temperature with low level of noise in the measured signal. PD contro controlle llerr is often often used used in contr control ol of moving moving objec objects ts such such are flying flying and and underwater vehicles, ships, rockets etc. One of the reasons is in stabilizing effect of PD controller on sudden changes in heading variable y(t). Often a "rate gyro" for velocity measurement is used as sensor of heading change of moving object.
3.1.5.3 PI controller PI controllers are the most often type used today in industry. A control without D mode is used when: a) Fast response of the system is not required b) Large disturbances and noise noise are present during operation operation of the process c) There is only one energy storage in process (capacitive or inductive) d) There are large transport delays in the system If there are large transport delays present in the controlled process, error prediction is requ requir ired ed.. Howe Howeve ver, r, D mode mode cann cannot ot be used used for for pred predic icti tion on beca becaus usee every every information is delayed till the moment when a change in controlled variable is SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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PID CONTROLLER
recorded. In such cases it is better to predict the output signal using mathematical model of the process in broader sense (process + actuator).
3.1.5.4 PID controller Derivative mode improves stability of the system and enables increase in gain K and decrease in integral time constant Ti, which increases speed of the controller resp respon onse. se. PID PID cont contro roll ller er is used used when when deal dealin ing g with with high higher er orde orderr capa capaci citi tive ve processes (processes with more than one energy storage) when their dynamic is not similar to the dynamics of an integrator (like in many thermal processes). PID controller is often used in industry, but also in the control of mobile objects (course and trajectory trajectory following following included) included) when stability stability and precise precise reference reference following following are required. Conventional autopilots are for the most part PID type controllers.
3.1.6 PID controller parameter and topology identification i dentification Problem of identification of PID controller arises when parameters of an existing controller have to be tuned. Manufacturers usually don’t give data about controller structure (serial or parallel), so its structure also has to be determined. Controller parameters have to be manually tuned if they are changed with time (that is often with hydraulic hydraulic and pneumatic pneumatic controlle controllers) rs) or because because process process parameters parameters have have changed so the controller does not perform satisfactory anymore. Not knowing the exact structure of the controller is not critical if manual parameter tuning can be done in controlled environment using trial and error method and if rules given in table are observed:
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CL RESPONSE Kp Ki Kd
RISE TIME
OVERSHOOT
Decrease Decrease Small Change
Increase Increase Decrease
SETTLING TIME Small Change Increase Decrease
S-S ERROR
Decrease Eliminate Small Change
3.2 PID CONTROLLER THEORY:
This section describes the parallel or non-interacting form of the PID controller. For other forms please see the section Alternative nomenclature and PID forms. The PID control scheme is named after its three correcting terms, whose sum cons consti titu tute tess the the mani manipu pula late ted d vari variab able le (MV) (MV).. The The prop propor orti tion onal al,, inte integr gral al,, and and derivative terms are summed to calculate the output of the PID controller. Defining as the controller output, the final form of the PID algorithm is:
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PID CONTROLLER
Where, Kp: Proportional gain, a tuning parameter Ki: Integral gain, a tuning parameter Kd: Derivative gain, a tuning parameter e (t): Error t: Time or instantaneous time (the present)
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PID CONTROLLER
Chapter 4 MODELLING OF PID CONTROLLER 4.1 VLSI implementation implementation
Industrial familiarized technology. technology.
Globally used logic.
Original standard IEEE 1364-1995 was approved.
Simple to design (VHDL circuits).
4.2 HISTORY 4.2.1 BEGINNING
Verilog was the first modern hardware description language to be invented. It was was crea create ted d by [[Ph [[Phil il Moorb oorby] y]]] and and [[Pr [[Prab abhu hu Goel Goel]] ]] duri during ng the the wint winter er of 1983/ 1983/19 1984. 84. The wordi wording ng for this this proces processs was was "Auto "Automat mated ed Integr Integrate ated d Desig Design n Syst System ems" s" (lat (later er rena rename med d to [[Ga [[Gate tewa way y Desi Design gn Auto Automa mati tion on]] ]] in 1985 1985)) as a hardw hardware are modeli modeling ng langu language age.. Gatew Gateway ay Desig Design n Autom Automati ation on was purcha purchased sed by [[Cadence Design Systems]] in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto standard (of Verilog [[logic simulator]]s) for the next decade. Originally, SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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Verilo Verilog g was intend intended ed to descr describe ibe and and allow allow simula simulatio tion; n; only only afterw afterward ardss was was support for synthesis added. Verilog-95 With the increasing success of [[VHDL]] at the time, Cadence decided to make the language available for open [[standardization]]. Cadence transferred Verilog into the public public domain domain under under the [http://w [http://www.ov ww.ovi.org i.org// Open Verilog Verilog Internati International] onal] (OVI) (now known as [[Accellera]]) organization. Verilog was later submitted to [[IEEE]] and became IEEE Standard 1364-1995, commonly referred to as Verilog95.
In the same time frame Cadence initiated the creation of [[Verilog-A]] to put standards support behind its analog simulator [[Spectre Circuit Simulator|Spectre]]. Verilog-A was never intended to be a standalone language and is a subset of [[Verilog-AMS]] which encompassed Verilog-95. Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became [[IEEE]] Standard 1364-2001 known as Verilog-2001.
Verilo Verilog-2 g-2001 001 is a signif significa icant nt upgrad upgradee from from Veril Verilog-9 og-95. 5. First, First, it adds adds explic explicit it support for (2's complement) signed nets and variables. Previously, code authors had had to perfor perform m signed signed operat operation ionss using using awkwar awkward d bit-l bit-leve evell manip manipula ulatio tions ns (for (for SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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PID CONTROLLER
example, the carry-out bit of a simple 8-bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -,
/,
*,
>>>.
A
generate/endgenerate
construct
(similar
to
VHDL's
gener generate ate/en /endg dgene enerat rate) e) allow allowss Veril Verilog-2 og-2001 001 to contr control ol instan instance ce and statem statement ent inst instan anti tiat atio ion n
thro throug ugh h
norm normal al
decisi cision on
oper operaators tors
(ca (case/i se/if/ f/el else se). ).
Usin sing
generate/ generate/endg endgenerat enerate, e, Verilog-20 Verilog-2001 01 can instanti instantiate ate an array array of instances, instances, with cont contro roll over over the the conn connec ecti tivi vity ty of the the indi indivi vidu dual al inst instan ance ces. s. File File I/O I/O has has been been improved by several new system tasks. And finally, a few syntax additions were intr introd oduc uced ed to impr improv ovee code code read readab abil ilit ity y (e.g (e.g.. alwa always ys @*, @*, name named d para parame mete ter r override, C-style function/task/module header declaration).
Verilo Verilog-2 g-2001 001 is the the domin dominant ant flavor flavor of Veril Verilog og suppo supporte rted d by the the majori majority ty of commercial [[Electronic design automation|EDA]] software packages. Verilog 2005 Not to be confused with [[SystemVerilog]], ''Verilog 2005'' ([[IEEE]] Standard 1364-2 1364-200 005) 5) consis consists ts of minor minor corre correcti ctions ons,, spec spec clari clarific ficati ations ons,, and and a few new language features (such as the uwire keyword).'''A separate part of the Verilog stan standa dard, rd, [[Ve [[Veri rilo log-A g-AMS MS]] ]],, atte attemp mpts ts to inte integr grat atee anal analog og and and mixe mixed d sign signal al modeling with traditional Verilog.
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4.3 DESIGN PROCESSING
Design process consists of four main steps,
•
Analysis
•
Elaboration
•
Simulation
•
Synthesis
4.3.1 ANALYSIS
•
Chec Check k for for synt syntax ax and and sem seman anti ticc erro errors rs – Syntax: grammar of the language. language. – semantics: the meaning of the the model
•
Analyze each design unit separately – entity declaration – architecture body – … – best if each design unit unit is in a separate file
•
Analyzed design units are placed in a library – in an implementation implementation dependent internal form – current library is called work work
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4.3.2 ELABORATION •
“Flattening” the design hierarchy
– create ports – create signals and processes processes within architecture body – for each component instance, copy instantiated entity and architecture body – repeat recursively • •
botto bottom m out at at purel purely y behavi behaviora orall archite architectu cture re bodie bodiess
Fina Finall resu result lt of elab elabor orat atio ion n – flat collection of signal signal nets and processes
4.3.3 SIMULATION •
Execut Execution ion of of the the proce processe ssess in the elabor elaborate ated d model model
•
Disc Discre rete te even eventt sim simul ulat atio ion n – time advances in discrete discrete steps –
•
when signal values change—events
A proc process esses es is sens sensiti itive ve to event eventss on inp input ut sign signals als – specified in wait statements statements – resumes and schedules new values values on output signals signals •
schedules transactions
•
event event on on a sign signal al if new new valu valuee diffe differen rentt from from old value value
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4.3.3.1 SIMULATION ALGORITHM •
Sim Simulation cycle – advance simulation time time to time of next transaction transaction – for each transaction at this time time •
upda pdate sig signal value alue – event if new value is different different from old value
– for each process sensitive to any of these events, or whose “wait for …” time-out has expired
•
•
resume
•
execu execute te unt until il a wait wait stat stateme ement, nt, then then susp suspend end
Simulation Simulation finishes finishes when there are no further further sched scheduled uled transactio transactions ns
4.3.4 SYNTHESIS •
Translates Translates register-t register-transfe ransfer-lev r-level el (RTL) (RTL) design design into gate-level gate-level netlist netlist
•
Restri Restricti ction onss on coding coding style style for for RTL RTL model model
•
Tool dependent
4.4 STRUCTURAL MODELING Logic is described in terms of Verilog gate primitives. •
Structural architecture –
port maps implements the module module as a composition of subsystems subsystems
– contains
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–
signal declarations, for internal interconnections interconnections •
the the entit entity y ports ports are also also trea treated ted as sig signal nalss
•
compon mponeent inst instan ance cess – instances of previously declared declared entity/architecture entity/architecture pairs
•
in comp compon onen entt inst instan ance cess – connect signals signals to component ports
4.5 BEHAVIOURAL MODELING Algorithmically specify the behavior of the design. •
Architecture body – describes an implementation implementation of an entity – may be several per entity entity
•
Behavioral architecture – describes the algorithm performed performed by the module – contains •
process statements, each containing containing –
sequential statements, including
•
signal assignment statement s and
•
wait statements.
4.6 MIXED BEHAVIORAL AND STRUCTURAL MODELING •
An architect architecture ure can can cont contain ain both behaviora behaviorall and and structu structural ral parts parts – process statements and component component instances •
collectively collectively called concurrent statements
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– processes can read and assign to signals signals •
Exampl Example: e: reg registe ister-tr r-trans ansfer fer-lev -level el (RTL) (RTL) Mode Modell – data path described structurally structurally – control section described described behaviorally
4.7OPERATORS
Operator
Operator type
Bitwise
Logical
Reduction
Operation performed
symbols
~
Bitwise NOT (1's complement)
&
Bitwise AND
|
Bitwise OR
^
Bitwise XOR
~^ or ^~
Bitwise XNOR
!
NOT
&&
AND
||
OR
&
Reduction AND
~&
Reduction NAND
|
Reduction OR
~|
Reduction NOR
^
Reduction XOR
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~^ or ^~
Reduction XNOR
+
Addition
-
Subtraction
-
2's complement
*
Multiplication
/
Division
**
Exponentiation (*Verilog-2001)
>
Greater than
<
Less than
>=
Greater than or equal to
<=
Less than or equal to
Arithmetic
==
Relational
!=
===
!==
Shift
>>
Logical equality (bit-value 1'bX is removed from comparison) Logical inequality (bit-value 1'bX is removed from comparison) 4-state logical equality (bit-value 1'bX is taken as literal)
4-state logical inequality (bit-value 1'bX is taken as literal)
Logical right shift
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<<
Logical left shift
>>>
Arithmetic right shift (* (*Verilog-2001)
<<<
Arithmetic left shift (*Verilog- 2001)
Concatenation { , }
Concatenation
Replication
Replicate value m for n times
{n{m}}
Conditional Conditional
?:
4.8 Discrete PID There are three controllers acting in concert. The three controllers are: A proportional (top), An Integral (center), A Derivative (bottom). The The propo proporti rtiona onal, l, integ integral ral and and deriv derivati ative ve output outputss are added added togeth together. er. The The PID controller can be thought of as having a transfer function. The PID controller transfer function can be obtained by adding the three terms. PID(s) = Kp + Ki/s+ sKd The transfer function can be combined into a pole-zero form. PID(s) = [sKp + Ki+ s2Kd]/s
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Since there is a quadratic in the numerator, there are two zeroes in this transfer function as well as the obvious pole at the origin, s = 0. Now, here's a good way to think about the effect of using a PID controller. The PID controller transfer function really adds a pole at the origin, and two zeroes that can be anywhere in the s-plane that the designer wants, depending upon the designer's choice of the three gains. PID(s) = [sKp + Ki+ s2Kd]/s This gives the designer an incredibly large number of possibilities. A standard “textbook” equation of PID controller is
Which then converted back to discrete equation as
- a form suitable for for implementation. implementation.
4.9 Verilog Model : module PID // bit width ? 1 (output signed [15:0] u_out, // input signed [15:0] e_in, //
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input clk, input reset); parameter k1=107; // change these these values to suit your system parameter k2 = 104; parameter k3 = 2; //reg signed [15:0] u_out; reg signed [15:0] u_prev; reg signed [15:0] e_prev[1:2];
always @ (posedge clk) begin if (reset == 1) begin u_prev <= 0; e_prev[1] <= 0; e_prev[2] <= 0; end else begin e_prev[2] <= e_prev[1]; e_prev[1] <= e_in; SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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u_prev <= u_out; end end
assign u_out = u_prev + k1*e_in - k2*e_prev[1] + k3*e_prev[2]; endmodule module PID_TST; reg clk, reset; reg[15:0] e_in; wire[15:0] u_out; initial begin clk=1'b0; reset = 1'b1; end always #5 clk =~clk; initial begin //#10 reset = 1'b1; //#25 reset = 1'b0; SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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#15 e_in=16'b0000000000001000; e_in=16'b0000000000001000; #25 e_in=16'b0000000000000110; e_in=16'b0000000000000110; end PID p1 (.u_out(u_out), .e_in(e_in), .clk(clk), .reset(reset)); endmodule
4.10 SPARTAN 3E •
The design is targeted to Spartan Spartan 3E board and synthesized. synthesized.
•
After synthesis, the design summary is obtained.
•
The RTL Schematic is also obtained from synthesis.
The device summary for our code is given below:
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The device utilization summary of our program in FPGA board comparing to its total memory available is:
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Chapter 5 RESULTS AND WAVEFORMS
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Chapter 6 CONCLUSION AND FUTURE WORKS 6.1ADVANTAGES SREE NARAYANA GURUKULAM COLLEGE OF ENGINEERING DEPARTMENT OF ECE
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It is far easier to tune a digital PID controller, than an analog controller. To tune analog controller, requires multi-turn potentiometers and a lot of actual "tweaking" of thos thosee pots pots.. Occa Occasi sion onal ally ly you you need need to chan change ge out out capa capaci cito tors rs in an anal analog og controller, too. Once pot values have been fixed, and permanent resistors have been soldered in place, there is amplifier, resistor, and capacitor drift to contend with. Analog systems sometimes require precision-valued components, which are expensive. Its major advantages are: •
The Verilog code is developed with complex routines and in depth operators to make it simpler.
•
The developed code is proved to area effective when it is synthesized with Xilinx ISE.
•
The design uses a single single global clock. clock. The total gate count count is only 1,832 and it uses only 83 memory slices in FPGA out of 2844 .
6.2CONCLUSION: •
A digit digital al PID contro controlle llerr imple implemen mented ted in Veril Verilog og HDL is a config configurab urable le controller in terms of bit-width and parallelism.
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Implementing PID controllers on FPGAs features speed, accuracy, power, compac compactne tness, ss, and and cost cost improv improveme ement nt over over other other digit digital al implem implement entati ation on techniques. The Verilog code is developed with complex routines and in depth operators to make it simpler.
•
The developed code is proved to area effective when it is synthesized with Xilinx ISE.
•
The design uses a single single global clock. clock. The total gate count count is only 1,832 and it uses only 83 memory slices in FPGA out of 2844.
•
We developed a Verilog code which is more simpler and consumes less area which in turn consumes less power*.
6.3FUTURE WORKS: In Future work we have planned to identify suitable plant to control and tune the gains accordingly. Also we like to implement interfacing modules along with this.
Chapter 7 REFERENCE
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1.R. Gao, D. Xu,J. P. Bentley, “Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications”,IEEE applications”,IEEE Transactions on Consumer Electronics, V49, N4,Nov 08. 2. Verilog HDL-Samir Palnitkar 3. www.asic-world.com
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