nexus 7 schematic

5

D

C

B

01.Block Diagram 02.POWER TREE 03.Power On/Off&Reset Timing 04.Power Sequence map 05.T30 Core & Fuse 06.T30 SYS IF 07.T30 GMI IF 08.T30 DDR 09.T30 DSI/CSI,CAM 10.T30 LCD 11.T30 HDMI,VGA 12.T30 BB,UART 13.T30 AUDIO 14.T30 USB,HSIC,ICUSB 15.T30 SDMMC,eMMC 16.T30 PCIe 17.T30 NC 18.Boot Straps 19.DDR3L 20.LCD data EMI filter 21.LCD panel power 22.eMMC,SDIO I/F 23.Sensor 24.Debug Connector 25.Hall 28.NUVOTON NPCE795L-1 30.EC description 31.SMBus tributaries 32.I/O Connector 33.TP&IO_CON(MB) 34.Coin cell 35.Camera power 36.Camera ISP & Connector 37.Codec_ALC5631Q-VE 38.DSP_FM34 39.Audio Conn 40.HW_RF_Interface 41.WiFi+BT combo II 43.BCM4751 GPS 44.SW CON 46.HDMI Conn 47.EMC 48.Srew Hole 49.DC_JACK & BAT CON 50.Power Sequenc Logic 51.Power_Latch 52.LVDS transmitter_30 53.LCD panel connector_30 a54.TP&IO_Block Diagram a55.TP&IO_Conn&SIM&SD a56.TPIO_ATMXT768EXES a57.TP&IO_TP CON a58.TP&IO_POWER a59.TP&IO_RST_SW 63.ALS_LSC3010 81_PW_+5VSUS_+3VSUS_TPS51125A 86_PW_2.85V&VDD_5V0_SYS 89_PW_Charger(BQ24745) 90_PW_A/D_IN 91.PMU-TPS65911 1/3 92.PMU-TPS65911 2/3 93.PMU-TPS65911 3/3 95.Force_off_recovery 96.Low_Low_BAT# 97.PWR_SW# Selection 99.HISTORY

4

3

2

1

1.0

ME370T (Nakasi) Original 2012/02/08 Project Name ME370T

Front Camera module

Rear Camera module

Aptina 1040

D

OV5650

MIPI_CSIB_1V2

Antenna

MIPI_CSIA_1V2

CAM_I2C_1V8

HDMI DDC_I2C 5V0

Micro HDMI

LCD Panel

Transmitter

LVDS

LSC3010

Audio DSP

AICHI AMI304

I2S CODEC

HEADSET JACK

Controls 32.768KHz PWR_I2C_1V8

Gen1_I2C_1V8

I2S_1V8

ALC5642

Tegra T30L Kai

PWR_I2C_1V8

Speaker DMIC KNOWLES SPM0423HD4H-WB

Gyro sensor Invensense MPU-6050

PMIC

OnSemi NCT72

DDR3L 256M x8 x4pcs 1333(667MHz)

DDR3L x 32_1V35 HSMMC x8_1V8

eMMC 8GB

Button FPC

GEN2_I2C_3V3

ELAN

JTAG_1V8 UART_4_1V8

I/O Board & TP EXTERNAL SD SCOKET

PWR_I2C_1V8

Charger

SMB347 USB Conn.

USB_1_3V3

SDIO_1_1V8 UART_3_1V8 32.768KHz

Power Button Volume Up & Down Reset Button

Debug Port

GEN2_I2C_1V8 Battery Gauge

C

Thermal Sensor XTAL 12MHZ

Internal D MIC

Touch screen

XTAL 32.768KHz

MAXIM MAX77663

FM34

EXT MIC

XTAL 27.12MHz

E-COMPASS

CAM_I2C_1V8

GEN1_SMB_3V3 HEADSET

Light sensor

CAM_I2C_1V8

LCD_RGB_1V8

TI SN75LVDS83B

NFC NXP PN65

CAM_I2C_1V8

EC NUVOTON NPCE795LA0DX

B

Antenna

WIFI + BT Azurewave AW/NH-665

XTAL 37.4MHz

USB_3_3V3 Docking USB Port

TCXO 26MHz

Gen1_I2C_1V8

USB*3 , Line out , Mic In , DC Jack

32.768KHz

Docking

UART_2_1V8

Antenna

GPS Broadcom BCM4751

A

A

Title : 01.Block Diagram Engineer:

ASUSTeK COMPUTER INC. EPAD Size

Project Name

C Date: 5

4

3

2

Richard Lin Rev

ME370T

Friday, March 02, 2012

Sheet 1

2.0 1

of

60

5

4

3

2

1

page 52

PMIC

ME370T (Nakasi)

MAX77663

Power Tree

IN_LDO2

LDO2

IN_LDO3/5

LDO3

VDD_PMU_LDO2_2V8 T30 2.8V. 150mA, PMIC

VDD_DDR_RX

VDD_PMU_LDO3_2V8 page 20 2.8V. 300mA, PMIC VDD_PMU_LDO5

LDO5

page 31

2.8V. 300mA, PMIC

USB Conn.

VDD_USB1_VBUS

Dock Conn.

+3VSUS_CPU

Charger DOCK_5V

VBATT

U1

page 5

T30

Power SW NCT352

Battery

D

VDDIO_CAM Camera VDDIO

Power Source page 49

VCORE_EMMC_S 200mA for eMMC VCC

D

VDD_FUSE VDD_1V8_GEN_CPU

T30

SMB347

T30

T30

VDD_3V3_GMI

T30

Power SW NCT352

AVDD_USB

page 26

VDDIO_PEX_CTL

page 48

Buck-Boost

3.3V. 2A

TPS63020 page 48

VDD_5V0_SYS

Boost

RT9276GQW

5V. 1A

page 22 U30

page 29

LDO

S-1167

page 26

MAX77663 MBATT, MON, GPIO_INA & AVSD

page 26

T30 CORE

1.2V. 3A, PMIC

VDD_ALS

for Hall Sensor, ALS

VDD_GYRO

for Gyro VDD

AVDD_ECOM

for E-compass AVDD

WiFi_BT_VCC_3V3

page 26

page 26

IOVCC_30

page 27

for Wifi/BT Module

VDDIO_GYRO

for Gyro VLOGIC

DVDD_ECOM

for E-compass DVDD

for Audio Codec DBVDD

VDD_1V8_CDC

CPVDD

page 41

VDD_CORE

GPS_VDD_BAT_3V3 for GPS

1.2V, 2.5A, Terga

1.8V. 2.0A, PMIC

LDO6

VDD_PMU_LDO4_1V2

T30

T30

3/1.8V. 150mA, PMIC

page 27

PMIC

VDD_RTC

IN_LDO0/1

VDDIO_SDMMC1

U27

LDO0

LDO1 AVDD_CAM1

S-1132

Camera AVDD

2.8V. 300mA IN_LDO7/8

CAM1_LDO_EN(T30 KB_ROW6)

LDO7

U28 AVDD_VCM

S-1132

CAMERA AF VCM

LDO8

2.8V. 300mA

VDD_PMU_LDO0_1V0 T30 1.0V. 150mA, PMIC

page 27 page 44

VDD_SPK

DACREF_CDC

VDD_1V8_DMIC

VDD_DDR_HS page 41

150mA, PMIC

No usage

VDD_PMU_LDO7_1V2 T30 1.2V. 450mA, PMIC T30

1.2V. 300mA, PMIC

page 43

GPS_VDD_IO_1V8

for GPS

NFC_PVDD

for NFC

AVDD_DSI_CSI AVDD_PLLA_P_C AVDD_PLLM page 50

AVDD_PLLU_D Codec Speaker Amp.

PMIC

AVDD_PLLX

NFC VBAT

WiFi_BT_VDDIO_1V8 for Wifi/BT Module

page 44

VDD_PMU_LDO8_1V2

T30 NFC_VBAT

AVDD_CDC_F

VDD_PMU_LDO1

CAM2_LDO_EN(T30 KB_ROW8) A

VCP_CDC

for DMIC VDD

MAX77663

1.2V. 150mA, PMIC VDD_PMU_LDO6_3V_1V8

DCVDD

page 52

1.35V. 1.5A, PMIC

VDB_CDC

B

AVDD

+1.35V

IN_LDO4/6

LDO

IOVCC

VDD_1V8_GEN

LDO4

page 31

VDDIO_HSMMC for LVDS Transmitter

page 41

VDD_CPU

SD3

LDO

for eMMC VCCQ

page 22

SD2

page 31

page 20

AVDD_USB_PLL

CORE_PWR_REQ

1.05V, 6.1A, Terga (Tj=90, 1.3GHz)

VDD_1V2_SOC

SD1

B

for LVDS Transmitter

VDD_LVDS_PLL_30

PMIC

T30 CPU

T30

Load SW PMOS

PLLVCC

page 50~52

1.05V. 6A, PMIC

Q2

page 14

VDD_LVDS_F_30

page 29

VDD_5V0_SYS enable

VDD_1V0_GEN

C

VDDIO_SDMMC3

LVDSVCC

page 25

SD0

for LCD Panel

VDD_LVDS_30

for Touch Sensor TP_3V3

3.3V. 150mA

EN_5V0_SBY(T30 GMI_AD11)

VCC_LCD3V3

VCC

VDD_LVDS_30

VDDIO_SDMMC4

T30

EN_VDD_PNL (T30 LCD_M1)

EN_3V3_SYS(PMU GPIO3)

Internal Usage

Power SW NCT352

+3VSUS

VDD_IO_AUDIO

T30

U8

page 21

VDD_PNL

VDDIO_UART

T30

TBD (no use) C

VDDIO_BB

T30

for Thermal Sensor T30

VDDIO_LCD

T30

VCORE_TEMP

VCC_LED

VDDIO_CAM

T30

EN_AVDD_USB (MAX77663 GPIO2) page 21

VDDIO_SYS

T30

U14

page 14

VDD_AC_BAT (VPH_PWR_CHGR)

AVDD_OSC

EN_VDD_FUSE (T30 LCD_PWR1)

MAX77663

A

VDDIO_DDR Internal Usage

Max. 710mA

GPIO_INB

DRAM Chip 256Mb x8bits x4pcs page 19

170mA x4, each DRAM chip

VDD_DDR3L

for DDR3L VDD

VDDQ_DDR3L

for DDR3L VDDQ

Title : 02.POWER TREE ASUSTeK COMPUTER INC. EPAD Size

Project Name

5

4

3

2

Richard Lin Rev

ME370T

Custom Date:

Engineer:

Thursday, March 01, 2012 1

Sheet

2.0 2

of

60

5

4

3

2

1

TF300T_T3 Power On/Off

A/D_IN AC_BAT_SYS

D

D

3.3V

AC_OK

3.3V

+3VA_PAL(PU8805)

3.3V

PWR_SW# 3.3V +3VA_EC (PU8806) AC_BAT_SYS EC to PU8100 P_+5VSO_EN_10 (Q7900) 5V +5VSUS (PU8100) 1.8V VDD_1V8_PMU_VRTC(PMU VRTC) SW# to PMU

3.3V

PMU_ONKEY#

C

C

EN_5V0_SBY(PMU GPIO0)

1.8V

VDD_5V0_SBY(PQ9106, 2A) PMU to T3

VDD_RTC(PMU LDO4) VDD_1V8_GEN(PMU SWIO)

PMU to T3

VDD_CORE(PMU SW1)

PMU to T3

VDD_PMU_LDO7(T3 AVDD_PLLx)

PMU to T3

CLK_32K_IN(PMU)

T3 XTAL

System Clock(T3 26MHz)

5V 1.8V 1.2V 1.1V

5.0V

EN_VDD_1V35(EN_DDR, PMU GPIO7)

1.8V

+1.8V

B

B

1.35V

+1.2V(for DDR3L 1.35V) 5.0V PMU to PU8100 EN_3V3_SYS(PMU GPIO6) T3 to Q1603

1.8V

EN_3V3_EMMC(T3)

2.85V

VCORE_eMMC_S(Q1603)

A

PMU to T3

VDD_DDR_HS(PMU LDO8) 1.0V

PMU to T3

VDD_SATA(PMU LDO2)

PMU to T3

VDD_PEX(PMU LDO1)

PMU to T3

SYS_RESET#(PMU)

T3 to PMU

CPU_PWR_REQ(TERGA)

1.05V 1.05V

(EEPROM OFF)

1.8V 1.8V A

1.0V PMU to T3

VDD_CPU(PMU SW) +1.05VS/+1.2VS/+1.5VS OTHERS

(PMU LDOs, Switched Rails) Title :Timing ASUSTeK COMPUTER INC. EPAD Size

Project Name

Custom

Date: Thursday, March 01, 2012 5

4

3

2

1

Engineer:

Richard Lin Rev

ME370T Sheet

2.0 3

of

60

5

4

<1>PWR_SW#

TF300T T3 power on/off map

Button

Power Latch

3

LDO

<2B>+3VA_EC

EN_VDD_FUSE

P-MOS SI2305DS EN

VDD_FUSE

T30

<10B>+3VSUS CAM1_LDO_EN

<10B>VDD_PNL(+3VSUS)

<2A>P_+3VA_EN

EN_VDD_PNL

D

P-MOS SI2305DS EN

LCD panel

VCC_LCD3V3

Adapter LDO

+3V_PAL

<10B>+3VSUS

A/D IN AC_BAT_SYS Buck Boost

EN_3V3_COM Charger BQ24740

BAT

1

<2A>P_+3VA_EN <10B>+3VSUS

1201

2

SW1

<10B>+3VSUS CAM2_LDO_EN

P-MOS SI2305DS EN

LDO 2.85V RT9193-2HGU5 EN

AVDD_CAM1

LDO 2.85V RT9193-2HGU5 EN

AVDD_VCM

D

WIFI+BT

WiFi_BT_VCC_3V3

<10B>+3VSUS(+3VSO1)

TI TPS51125ARGER EN1 EN2

SW2

<3>+5VSUS(+5VSO1)

LDO

C

N-MOS IRFHS8342TRPBF EN

** <5A>VDD_5V0_SBY

EN_5V0_SYS

N-MOS IRFHS8342TRPBF EN

VDD_5V0_SYS

<4>+3VA

<2C> P_+5VSO_EN_10

<10A> EN_3V3_SYS

Battery Pack

<5>EN_5V0_SBY

DOCK_IN

<10B>+3VSUS

<6>EN_VDD_SOC

BAT EN_VDD_BL <7>VDD_1V8_GEN EN_1V8_CAM

P-MOS SI2305DS EN

VCC_LED

P-MOS SI2305DS EN

VDDIO_CAM

P-MOS SI2305DS EN

+5VSUS_DOCK

P-MOS SI2305DS EN

<11>VCC_TCH

P-MOS SI2305DS EN

<6A>VDD_1V2_SOC

LCD panel backlight

<10>+3VSUS(+3VSO1)

B

Sequence: <1>--><2>--><2A>--><2B>--><2C>--><2D>--> <3>--><4>--><5>--><6>--><6A>--><7>--><8>--> <9>--><10>--><10A>--><10B>--><11>--><12>--><13>

<7>VDD_1V8_GEN

T30

SW

<0FF>VDD_CPU

VDD_CPU

<0FF>VDD_1V2_GEN

VDD_CORE

VCC2

SW2

<9>+1.2V

VCCIO

SWIO

<7>VDD_1V8_GEN

VCC7

VRTC

<5>VDD_1V8_PMU_VRTC

VCC6

LDO1 LDO2

<11>VCORE_eMMC_S(core power) VDD_SD_S

LDO3

VDDIO_SDMMC1

*** VCC4

A

B

VDD_SATA

<4>VDD_RTC

VDD_RTC

LDO5

VDD_PMU_LDO5

VDDIO_SDMMC1(3.3V)

LDO7

GPIO4 GPIO5 PWRDN(power down) HOT_RST PWRON

VDD_1V8_GEN @

LDO4

LDO6 VCC3

VDD_CELL_LCL

AP_OVERHEAT# HOT_RST <2D>PMU_ONKEY#

CPU_PWR_REQ CORE_PWR_REQ SYS_RESET_N PWR_INT_N CLK_32K_IN

SW1

VBACKUP

@

<13>CPU_PWR_REQ CORE_PWR_REQ <12>SYS_RESET# PWR_INT# <9>CLK_32K_IN

VCC1

VDDIO

<5>VDD_1V8_PMU_VRTC

VDDIO_HDMI_CONN_AIO

V5IN

VCC5 VDD_5V0_SYS

P-MOS SI2305DS EN

C

EN2 EN1 SLEEP NRESPWRON PWR_INT# CLK32KOUT <5A>VDD_5V0_SBY

***

HDMI_VBUS_EN_AIO

VDD_PMU_LDO6 <9>VDD_PMU_LDO7(T3 AVDD_PLLx)

LDO8

<11>VDD_DDR_HS

GPIO0 GPIO2 GPIO6 GPIO7

<5>EN_5V0_SBY <6>EN_VDD_SOC <10>EN_3V3_SYS <9>EN_DDR

EEPROM

<10B>+3VSUS <9>+1.2V HVDD_PEX VDD_FUSE

AVDD_DSI_CSI(1.2V) * ***

AVDD_PLLx

VDD_DDR_HS

AVDD_USB VDD_DDR_RX AVDD_HDMI VDDIO_GMI VDD_PEX_CTL VDDIO_LCD VDDIO_DDR HVDD_PEX(3.3V) VPP_FUSE(3.3V) A

time slot duration: 2ms

Title : Power on/off map ASUSTeK COMPUTER INC. EPAD Size

Project Name

D Date: 5

4

3

2


Engineer:

Richard Lin Rev

ME370T Sheet

2.0 4

of

60

5

4

3

2

1

需需需需 02004-00120000 C.S T30-R-A3 FCBGA-728

BOM MAX77663 LDO4 VDD_RTC

VDD_FUSE 2 /@

U1

C

2

1

4

IN DIS

1 2 3

NCT3521U N/A

0720 VDD_FUSE_DISABLE

C24 0.1U6.3VX5RC1K N/A

OUT GND EN

R2 1 300R1F 2 N/A

1

VDDIO_UART

Unmount

2

R3 100KR1J /@

1

10 EN_VDD_FUSE

2

R4 100KR1J N/A

0720 default disable FUSE

function

B

A

GND_001 GND_002 GND_003 GND_004 GND_005 GND_006 GND_007 GND_008 GND_009 GND_010 GND_011 GND_012 GND_013 GND_014 GND_015 GND_016 GND_017 GND_018 GND_019 GND_020 GND_021 GND_022 GND_023 GND_024 GND_025 GND_026 GND_027 GND_028 GND_029 GND_030 GND_031 GND_032 GND_033 GND_034 GND_035 GND_036 GND_037 GND_038 GND_039 GND_040 GND_041 GND_042 GND_043 GND_044 GND_045 GND_046 GND_047 GND_048 GND_049 GND_050 GND_051 GND_052 GND_053 GND_054 GND_055 GND_056 GND_057 GND_058 GND_059 GND_060 GND_061 GND_062 GND_063 GND_064 GND_065 GND_066 GND_067 GND_068 GND_069 GND_070 GND_071 GND_072 GND_073 GND_074 GND_075 GND_076 GND_077 GND_078 GND_079 GND_080 GND_081 GND_082 GND_083 GND_084 GND_085 GND_086 GND_087 GND_088 GND_089 GND_090 GND_091 GND_092 GND_093 GND_094 GND_095 GND_096 GND_097 GND_098 GND_099 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121

1 1

VDD_RTC_0001 VDD_RTC_0002

V22 V23

VDD_RTC

1 1 1 1 1

N/A 2 C5 4.7U6.3VX5RC2M /@ 2 C29 4.7U6.3VX5RC2M N/A 2 C9 4.7U6.3VX5RC2M N/A 2 C11 8P25VNPOC1J

1

VDD_CPU

1 1 1

0.9~1.0V (0.9 ~ 1.0V)

VDD_CPU_01 VDD_CPU_02 VDD_CPU_03 VDD_CPU_04 VDD_CPU_05 VDD_CPU_06 VDD_CPU_07 VDD_CPU_08 VDD_CPU_09 VDD_CPU_10 VDD_CPU_11 VDD_CPU_12 VDD_CPU_13 VDD_CPU_14 VDD_CPU_15 VDD_CPU_16 VDD_CPU_17 VDD_CPU_18 VDD_CPU_19 VDD_CPU_20 VDD_CPU_21 VDD_CPU_22

H10 J10 J8 K8 K9 M7 M8 M9 N8 N9 P14 P15 P16 P17 R14 R17 T14 T17 U14 U15 U16 U17

VDD_CPU

0906 NV add

1220 add VDD_CORE

1 1

N/A 2 C14 22U6.3VX5RC5M N/A 2 C17 22U6.3VX5RC5M

1

VDD_CORE

1 1 1 1 1 1 1 1

1.0~1.2V

N/A 2 C15 0.1U6.3VX5RC1K N/A 2 C12 0.1U6.3VX5RC1K N/A 2 C20 0.1U6.3VX5RC1K N/A 2 C22 4.7U6.3VX5RC2M N/A 2 C18 4.7U6.3VX5RC2M N/A 2 C26 4.7U6.3VX5RC2M N/A 2 C27 4.7U6.3VX5RC2M N/A 2 C28 4.7U6.3VX5RC2M N/A 2 C25 33P25VNPOC1J

1 1 1

C

(1.0 ~ 1.2V)

VDD_CORE_01 VDD_CORE_02 VDD_CORE_03 VDD_CORE_04 VDD_CORE_05 VDD_CORE_06 VDD_CORE_07 VDD_CORE_08 VDD_CORE_09 VDD_CORE_10 VDD_CORE_11 VDD_CORE_12 VDD_CORE_13 VDD_CORE_14 VDD_CORE_15 VDD_CORE_16 VDD_CORE_17 VDD_CORE_18 VDD_CORE_19 VDD_CORE_20 VDD_CORE_21 VDD_CORE_22 VDD_CORE_23 VDD_CORE_24 VDD_CORE_25 VDD_CORE_26 VDD_CORE_27 VDD_CORE_28

M13 M15 M17 M19 N12 N14 N16 N18 N7 P13 P19 R12 R18 R7 R8 R9 T13 T19 T8 T9 U18 V13 V15 V17 V19 W14 W16 W18

VDD_CORE

0614 remove VDD_CPU_SENSE

Note: Place the 0402 shunts close to Tegra side

VDD_CPU_SENSE_T30

2

GND_CPU_SENSE_T30

AB12

VDD_CPU_SENSE_T30

AB15

GND_CPU_SENSE_T30

VDD_CORE_SENSE_T30

VVDD_CPU_SENSE VGND_CORE_SENSE

VDD_CORE_SENSE GND_CORE_SENSE

51

1 /@

GND_CPU_SENSE

GND_CPU_SENSE

51

PJP2 SHORT_PIN

2

B

PJP3 SHORT_PIN 1 /@

VDD_CORE_SENSE

P05 P05 GND_CORE_SENSE_T30

VDD_CPU_SENSE

MAX77663 SD0 sense

2

Short Copper

GND_CPU_SENSE

VDD_CPU_SENSE

P05 P05

Short Copper

VDD_CPU_SENSE

PJP1 SHORT_PIN 1 /@

VDD_CORE_SENSE

51

MAX77663 SD1 sense 1 /@

2

GND_CORE_SENSE

GND_CORE_SENSE

51

PJP4 SHORT_PIN

AB16 AA23

W23

VDD_CORE_SENSE_T30

W22

GND_CORE_SENSE_T30

VDD_FUSE (3.3V)

VPP_FUSE

(3.3V)

VPP_KFUSE

AB8 AA4

VPP_KFUSE

R5 10KR1J N/A

R6 1KR1J /@


A

Unmount

Title : T30 Core & Fuse Engineer:

ASUSTeK COMPUTER INC. EPAD Size C Date: 4

N/A 2 C16 4.7U6.3VX5RC2M N/A 2 C19 4.7U6.3VX5RC2M /@ 2 C21 4.7U6.3VX5RC2M /@ 2 C23 0.1U6.3VX5RC1K

1

VDD_CORE

T30L-R-P-A3 T30

5

D

1

Unmount

5

N/A 2 C2 0.1U6.3VX5RC1K N/A 2 C4 0.1U6.3VX5RC1K N/A 2 C6 0.1U6.3VX5RC1K N/A 2 C8 4.7U6.3VX5RC2M N/A 2 C7 4.7U6.3VX5RC2M N/A 2 C3 4.7U6.3VX5RC2M N/A 2 C10 4.7U6.3VX5RC2M N/A 2 C13 4.7U6.3VX5RC2M

(1.0 ~ 1.2V)

2

A2 A29 AC11 AC14 AC17 AC2 AC20 AC23 AC26 AC29 AC5 AC8 AF11 AF14 AF17 AF2 AF20 AF23 AF26 AF29 AF5 AF8 AJ1 AJ11 AJ14 AJ17 AJ2 AJ20 AJ23 AJ26 AJ29 AJ30 AJ5 AJ8 AK2 AK29 B1 B11 B14 B17 B2 B20 B23 B26 B29 B30 B5 B8 E11 E14 E17 E2 E20 E23 E26 E29 E5 E8 H11 H14 H17 H2 H20 H23 H26 H29 H5 H8 L2 L23 L26 L29 L5 L8 M12 M14 M16 M18 N13 N15 N17 N19 P12 P18 P2 P23 P26 P29 P5 P8 R13 R15 R16 R19 T12 T15 T16 T18 U13 U19 U2 U23 U26 U29 U5 U8 V12 V14 V16 V18 W12 W13 W15 W17 W19 Y2 Y23 Y26 Y29 Y5 Y8

VDD_CORE

R1 1 0R2J

1

1.2V

1/22 CORE POWER

MAX77663 SD1(3A)

+3VSUS_CPU

VDD_CPU

1

VDD_CPU

VDD_1V2_SOC

0622

N/A 2 C1 0.1U6.3VX5RC1K

U2A

MAX77663 SD0(6A)

D

1.0~1.2V

1

0906 NV add

2

0.9~1.0V VDD_1V0_GEN

VDD_RTC

0620

1

VDD_PMU_LDO4_1V2

2

1.2V

3

2

Project Name

Richard Lin Rev

ME370T

Saturday, March 24, 2012

Sheet 1

2.0 5

of

60

5

4

MAX77663 LDO8

1.2V

VDD_PMU_LDO8_1V2

VDD_PMU_LDO8_1V2_CPU

3

1.2V


AVDD_PLLA_P_C

1.2V


AVDD_PLLU_D

1.2V

Remove AVDD_PLLX

1.2V

Remove AVDD_PLLM

2

1

Power from MAX77663 MAX77663 LDO8 1.2V to T30 AVDD_PLLx MAX77663 SD2 1.8V (VDD_1V8_PMU_DCDC2) to VDD_1V8_GEN

Signal to & from MAX77663 R8

1.8V

1

VDD_1V8_GEN

2 N/A

0R3J

1.8V

VDD_1V8_GEN_CPU

VDD_1V8_GEN_CPU

SYS_RESET# from MAX77663 nRSTIO, check reset circuit(p.32) and PMU side

VDDIO_SYS L7

D

MAX77663 SD2 (2A)

1.8V

1

VDD_1V8_GEN_CPU

N/A

2

PWR_INT# from MAX77663 nIRQ, check PU resister in PMU side(100k PU to VDD_1V8_GEN) AVDD_OSC

D

CORE_PWR_REQ to MAX77663 EN1, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

30Ohm/100Mhz

VDD_1V8_PMU_DCDC2

CPU_PWR_REQ to MAX77663 EN2, check PD resister in PMU side(100k PD)

0906 NV change U2B

CLK_32K_IN from MAX77663 GPIO4, check PU resister in PMU side(100k PU to VDD_1V8_GEN)

2/22 OSC, PLL & SYS

F30

AVDD_OSC

AVDD_OSC

XTAL_IN

T30

XTAL_IN

T29

XTAL_OUT

R9 N/A 2MR2J

VDD_PMU_LDO7

R10 0R1J N/A

AD7 /@ AVDD_PLLE_no_use

AA22

2

1 2

C32 12P50VNPOC2J N/A

USB&DSI

VDDIO_SYS

VDDIO_SYS C

AVDD_PLLU_D2

1.05V

AVDD_PLLE

PCIE&SATA

R11 1KR1J N/A

R12 1KR1J N/A 2

SHORT_PIN PWR_I2C_SCL PWR_I2C_SDA SYS_RESET_N

PWR_INT_N

PUPD

B

Deep Sleep

PinState

PUPD

After Wake

COL0

UP

100K

PU

Config.

Reset

COL1

UP

100K

PU

Config.

Reset

COL2

UP

100K

PU

Config.

Reset

COL3

UP

100K

PU

Config.

Reset

COL4

UP

100K

PU

Config.

Reset

COL5

UP

100K

PU

Config.

Reset

COL6

UP

100K

PU

Config.

Reset

COL7

UP

100K

PU

Config.

Reset

ROW0

DOWN 100K

PD

Config.

Reset

ROW1

DOWN 100K

PD

Config.

Reset

ROW2

DOWN 100K

PD

Config.

Reset

ROW3

DOWN 100K

PD

Config.

Reset

ROW4

DOWN 100K

PD

Config.

Reset

ROW5

DOWN 100K

PD

Config.

Reset

ROW6

DOWN

50K

PD

Config.

Reset

ROW7

DOWN

50K

PD

Config.

Reset

ROW8

DOWN

50K

PD

Config.

Reset

ROW9

DOWN

50K

PD

Config.

Reset

ROW10 DOWN

50K

PD

Config.

Reset

ROW11 DOWN

50K

PD

Config.

Reset

VDDIO_SYS

VDDIO_SYS_1 VDDIO_SYS_2

CORE_PWR_REQ CPU_PWR_REQ SYS_CLK_REQ CLK_32K_IN CLK_32K_OUT

PWR_I2C_SCL PWR_I2C_SDA

N28

SYS_RESET#

PWR_INT#

M22

1227 R0732 100K -> 10K VDDIO_SYS PWR_I2C_SCL PWR_I2C_SDA SYS_RESET#

Unmount

1 R16 1KR1J

2 N/A

26,27,49,50 26,27,49,50

R14 100KR1J N/A

20,32,50

JTAG_TRST# PWR_INT#

0229 NV change 10k -> 100k

50

CORE_PWR_REQ CPU_PWR_REQ

N25 R24 T23

CORE_PWR_REQ 14,50 CPU_PWR_REQ 50

CLK_32K_IN CLK_32K_OUT

R22 U27

CLK_32K_IN CLK_32K_OUT

R15 100KR1J N/A

50 40,41,43 2

POR

VDDIO_SYS

(1.8/3.3V)

1.8V

M24 N27

1

Short Copper

K29 K30

C32 & C33 change to 12pF

TXC/7V12000011

Change

(1.1V)

(1.05V)

1

1.2V

0721

DRAM

KB_COL00 KB_COL01 KB_COL02 KB_COL03 KB_COL04 KB_COL05 KB_COL06 KB_COL07 KB_ROW00 KB_ROW01 KB_ROW02 KB_ROW03 KB_ROW04 KB_ROW05 KB_ROW06 KB_ROW07 KB_ROW08 KB_ROW09 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG_RTCK

ROW12 DOWN

50K

PD

Config.

Reset

THERM_DN THERM_DP

ROW13 DOWN

50K

PD

Config.

Reset

OWR

ROW14 DOWN

50K

PD

Config.

Reset

HDMI_CEC

ROW15 DOWN

50K

PD

Config.

Reset

TEST_MODE_EN

J30 N26 V25 R26 W26 R30 P27 N29 T26 M23 V27 M28 N24 N30 T24 T25 R27 M26 R25 M27 N23 V28 M25 V26

PCB_ID2 PCB_ID5

0802 ID5

PCB_ID3

KB_ROW0 KB_ROW1 KB_ROW2 SNN_KB_ROW3 SNN_CAM_I2C_SEL0 SNN_CAM_I2C_SEL1 CAM1_LDO_EN CAM2_LDO_EN CAM3_LDO_EN SNN_CAM1_AF_PWDN* SNN_CAM2_AF_PWDN* CAM3_AF_PWDN* SNN_KB_ROW12 SNN_KB_ROW13 SNN_KB_ROW14 SNN_KB_ROW15

PCB_ID4 PCB_ID0 PCB_ID1 CAM1_LDO_EN NC CAM2_LDO_EN

LL_BAT_T30 1V8_O_LID#

T27 R29 T28 R23 T22 V24

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRT_N JTAG_RTCK

M30 M29

THERMD_N THERMD_P

KB_COL0 KB_COL1 KB_COL2 KB_COL3 SNN_KB_COL4 SNN_KB_COL5 SNN_KB_COL6 SNN_KB_COL7

PWR_SW#_BUTTON_R

33

KB_ROW0

32,33 B

NFC_GPIO4_R

PCBID ID1 ID0 0 0 AW-NH660

44

CAM1_LDO_EN

31

ROW10, 11 for charger control

CAM2_LDO_EN 31 SMB347_USB51HC 33 SMB347_SUSP 33

TEMP_ALERT#_KAI LL_BAT_T30 1V8_O_LID# NFC_VEN 44

BCM4330 VDD_1V8_GEN_CPU

TEMP_ALERT#_KAI form Thermal Sensor

25

PCB_ID0

1

2 R21 /@

0R1J

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# JTAG_RTCK

24 24 24 24 24 24

1 100KR1J 2 R18 1 100KR1J 2 R17

/@/PCBID/WIFI /PCBID/WIFI

PCB_ID1

1 100KR1J 2 R19 1 100KR1J 2 R20

/PCBID/WIFI /@/PCBID/WIFI

1 100KR1J 2 R22 1 100KR1J 2 R27

/PCBID/GPS /@/PCBID/GPS

1 100KR1J 2 R23 1 100KR1J 2 R25

/@/PCBID/PROJECT /PCBID/PROJECT

Unmount JTAG_TRT_N

PCB_ID2

Unmount THERMD_N THERMD_P

26 26

PCB_ID3

R26 1 0R1J

N/A 2

Unmount PCB_ID4

1 100KR1J 2 R31 1 100KR1J 2 R28

/@/PCBID/PROJECT /PCBID/PROJECT

Unmount PCB_ID5

T30L-R-P-A3 N/A

A

BCM4330

0 AW-NH665

33

R24 100KR1J N/A TEST_MODE_EN

1

Pin to Pin

26

N22

R28

for ME370T SR3

PCBID ID2 = 0 for BCM47511 ID2 = 1 for BCM4751

Unmount

Unmount

AC18

PCBID ID5 ID4 ID3 0 0 0

CPU_PWR_REQ PD 100k in KAI design

VOL_UP_BUTTON 32 VOL_DWN_BUTTON 32

1

PJ1 2

(1.1V)

AVDD_PLLU_D

remove PLL_S_PLL_LF

2

1 2

1 2


1.2V

NC37

CPU

1

AA8

AVDD_PLLU_D C

(1.1V)

AVDD_PLLM

VDDIO_SYS


1.2V

Change C33 12P50VNPOC2J N/A

2

AVDD_PLLU_D

(1.1V)

H12

1

J13

AUDIO&PERIPHERAL AVDD_PLLA_P_C AVDD_PLLX

X1 change to 12MHz XTAL 3

2

J12

(1.1V)

1.2V

2

Remove C35, C36 for AVDD_PLLX & AVDD_PLLM


H13

AVDD_PLLA_P_C

X1 N/A 12MHz

1

1

C31 4.7U6.3VX5RC2M N/A

2

1 2

AVDD_PLLA_P_C

Change 1

1

XTAL_OUT_R AVDD_OSC

2

1

1.1V 1.2V

1

2

R1.0 R1.2

XTAL_OUT

4

PMU

1.8V (1.8V)

1 100KR1J 2 R30 1 100KR1J 2 R29

/@/PCBID/PROJECT /PCBID/PROJECT A



4

3

2

Project Name

Richard Lin Rev

ME370T

Thursday, March 22, 2012

Sheet 1

2.0 6

of

60

5

4

3

2

1

R35

3.3V

1

+3VSUS

0R3J

2 N/A

3.3V

+3VSUS_CPU

+3VSUS_CPU

VDD_3V3_GMI

TPS63020 buck-boost

D

D

U2D

N/A 2 C39 10U6.3VX5RC3M N/A 2 C40 0.1U6.3VX5RC1K

1

VDD_3V3_GMI

1

4/22 GMI (1.8/3.3V)

VDD_3V3_GMI

C1 C2 D1

VDDIO_GMI_1 VDDIO_GMI_2 VDDIO_GMI_3

3.3V POR

VDDIO_GMI

PUPD

PUPD

After Wake

AD00

None

Z

Disable

Reset

AD01

None

Z

Disable

Reset

AD02

None

Z

Disable

Reset

AD03

None

Z

Disable

Reset

AD04

None

Z

AD05

None

Z

Disable

Reset

AD06

None

Z

Disable

Reset

AD07

None

Z

Disable

Reset

AD08

None

Z

Disable

Reset

Disable

GMI_A16 GMI_A17 GMI_A18 GMI_A19

Reset

GMI_CS0_N GMI_CS1_N GMI_CS2_N GMI_CS3_N GMI_CS4_N GMI_CS6_N GMI_CS7_N

AD09

None

Z

Disable

Reset

AD10

DOWN 100K

PD

Disable

Reset

AD11

DOWN 100K

PD

Disable

Reset

AD12

None

Z

Disable

Reset

AD13

None

Z

Disable

Reset

AD14

None

Z

Disable

Reset

GMI_RST_N GMI_WAIT GMI_WP_N

AD15

None

Z

Disable

Reset

GMI_IORDY

A16

None

Z

Config.

Hold

A17

None

Z

Config.

Hold

A18

None

Z

Config.

Hold

Z

Config.

Hold

CS0

UP

100K

PU

Config.

Reset

None

CS1

UP

100K

PU

Config.

Reset

CS2

UP

100K

1

Disable

Reset

CS3

UP

100K

1

Disable

Reset

CS4

UP

100K

PU

Config.

Reset

CS6

UP

100K

PU

Disable

Reset

CS7

UP

100K

PU

Config.

Reset

None

1

Disable

Reset

None

ADV_N CLK

0

Disable

Reset

RST_N

UP

100K

0

Disable

Reset

WAIT

UP

100K

PU

Disable

Reset

WP_N

UP

100K

PU

Config.

Reset

IORDY

UP

100K

PU

Config.

Reset

OE_N

None

1

Disable

Reset

WR_N

None

1

Disable

Reset

DQS

None

Z

Disable

Reset

GMI_ADV_N GMI_CLK

GMI_OE_N GMI_WR_N GMI_DQS

NAND_D0 NAND_D1 NAND_D2 NAND_D3 NAND_D4 NAND_D5 NAND_D6 NAND_D7 LCD_BL_PWM NC TS_WAKEUP# TS_IRQ# TS_RESET#_3V3

H4 J6 C4 J3

NC NC NC NC

J4 K7 F6 A3 D6 J5 J7

NC NC NC NC

LCD1_BL_PWM PWM_3D LCD1_BL_EN EN_VDD_BL1 TS_IRQ* TS_RESET* CARD_PEX_RST#

NAND_D0 NAND_D1 NAND_D2 NAND_D3 NAND_D4 NAND_D5 NAND_D6 NAND_D7 LCD_BL_PWM

18 18 18 18 18 18 18 18 23

TS_WAKEUP# TS_IRQ#

29,48 29

TS_RESET#_3V3

Boot Straps PCBID ID7 ID6 0 0 0 1 1 0 1 1

ALC5631Q WM8903 ALC5642 Reserved

29

TS_WAKEUP# for TS 5V enable (PD 1M on page.48)

PCBID ID8 Reserved

SPI4_SCK SPI4_DOUT SPI4_DIN SPI4_CS1

PCB_ID6

VDD_3V3_GMI

1 100KR1J 2 R37 1 100KR1J 2 R36

/@/PCBID/CODEC /PCBID/CODEC

Unmount

FTM_MODE#

SNN_GMI_CS0 PCB_ID6 CHARGER_STAT PCB_ID7 PCB_ID8 LCD_LANDSCAPE SNN_TP_IRQ# SNN_GMI_CS6 WW_WAKE*

PCB_ID7 SNN_GMI_CS2

1 100KR1J 2 R38 1 100KR1J 2 R39

/PCBID/CODEC /@/PCBID/CODEC

Unmount PCB_ID8

1 100KR1J 2 R40 1 100KR1J 2 R41

/@/PCBID /PCBID C

E6

NAND_ALE

A4

NAND_CLE

NAND_ALE NAND_CLE SNN_GMI_RST* RECOVERY_MODE* MFG_MODE_R

D4 B4 D5

18 LCD_BL_PWM

18,26

R43 N/A 330KR1J 1 2

NAND_CLE for AP thermal shut down in KAI

C3 F2 G4

NAND_RE# NAND_WE#

NAND_RE# NAND_WE#

18 18

G3 VDD_3V3_GMI

VDD_3V3_GMI

SNN_GMI_DQS

R44, R45 (GEN2_I2C PU) placed on P.29 VDD_3V3_GMI GEN2_I2C_SCL GEN2_I2C_SDA

G5 G7

GEN2_I2C_SCL GEN2_I2C_SDA


29 29

TS I2C 1

A19

B

PinState

F8 G6 D3 E4 G2 D2 B3 G1 H6 F4 E7 F3 F5 F7 J2 F1

R316 1MR1J N/A 2

C

Deep Sleep

GMI_AD00 GMI_AD01 GMI_AD02 GMI_AD03 GMI_AD04 GMI_AD05 GMI_AD06 GMI_AD07 GMI_AD08 GMI_AD09 GMI_AD10 GMI_AD11 GMI_AD12 GMI_AD13 GMI_AD14 GMI_AD15

FTM_MODE#

1

T30L-R-P-A3 N/A

T51 /@ tpc40t_np_68

B

A

A

Title : T30 GMI IF Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T

Wednesday, March 21, 2012

Sheet 1

2.0 7

of

60

5

4

3

2

1

U2C 3/22 DDR3/LPDDR2

D

2.8V

1.35V

MAX77663 LDO2 VDD_PMU_LDO2_2V8

VDD_DDR_RX

from PMIC

1.0V

DDR_DQ00 DDR_DQ01 DDR_DQ02 DDR_DQ03 DDR_DQ04 DDR_DQ05 DDR_DQ06 DDR_DQ07 DDR_DQ08 DDR_DQ09 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15 DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23 DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31


VDD_DDR_HS VDD_DDR_RX

A27

(2.8/3.3V)

VDD_DDR_RX

from PMIC

VDDIO_DDR

1 1 1 1 1 1 1

C

1

N/A 2 C41 0.1U6.3VX5RC1K N/A 2 C43 0.1U6.3VX5RC1K N/A 2 C44 4.7U6.3VX5RC2M N/A 2 C42 4.7U6.3VX5RC2M N/A 2 C45 4.7U6.3VX5RC2M N/A 2 C46 10U6.3VX5RC3M N/A 2 C47 10U6.3VX5RC3M N/A 2 C48 10U6.3VX5RC3M

VDD_DDR_HS

E10 H9

DDR_DM0 DDR_DM1 DDR_DM2 DDR_DM3

(1.00V)

VDD_DDR_HS_1 VDD_DDR_HS_2 DDR_DQS0N DDR_DQS0P DDR_DQS1N DDR_DQS1P

1.0V

DDR_DQS2N DDR_DQS2P

0503

DDR_DQS3N DDR_DQS3P DDR_A00 DDR_A01 DDR_A02 DDR_A03 DDR_A04 DDR_A05 DDR_A06 DDR_A07 DDR_A08 DDR_A09 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

C60 N/A 4.7U6.3VX5RC2M C61 N/A 4.7U6.3VX5RC2M C64 N/A 4.7U6.3VX5RC2M C67 N/A 4.7U6.3VX5RC2M

1

2

1

2

1

2

1

2

VDD_DDR_HS

1

N/A 2 C49 4.7U6.3VX5RC2M

VDD_DDR_RX

1

N/A 2 C50 4.7U6.3VX5RC2M

VDDIO_DDR

3.3V

DDR_RAS_N DDR_CAS_N DDR_WE_N DDR_BA0 DDR_BA1 DDR_BA2 DDR_CS0_N DDR_CS1_N DDR_ODT0 DDR_ODT1

B

DDR_CKE0 DDR_CKE1 DDR_CLK_N DDR_CLK DDR_RESET DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3

DDR_DQ[31..0]

D24 B25 A25 D21 A24 A21 A22 B22 C15 A13 C12 B13 C13 A10 B10 C10 G22 D22 D25 F23 G21 E25 F24 F22 F13 G13 G10 D13 G9 F10 D10 F12


C22 D12 E22 G12


B24 C24

DDR_DQS0N DDR_DQS0P

B12 A12

DDR_DQS1N DDR_DQS1P

E24 D23

DDR_DQS2N DDR_DQS2P

E12 D11

DDR_DQS3N DDR_DQS3P

D20 G15 A18 D14 B19 A16 C21 A15 D15 C16 E16 D18 E15 A19 B16

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

G18 D17

DDR_RAS_N DDR_CAS_N

DDR_RAS_N DDR_CAS_N

19 19

D19

DDR_WE_N

DDR_WE_N

19

F15 E21 F21

DDR_BA0_N DDR_BA1_N DDR_BA2_N


19 19 19 19 19

19

D

DDR_DM[3..0]

F16 E19

DDR_CS0_N DDR_CS1_N

DDR_CS0_N DDR_CS1_N

D16 F18

DDR_ODT0_N

DDR_ODT0_N

19

F19 E18

DDR_CKE0

DDR_CKE0

19

B18 C18

DDR_CLKN DDR_CLKP

C19

DDR_RESET_N

D27 D26 E9 F9

DDR_QUSE0 DDR_QUSE1 DDR_QUSE2 DDR_QUSE3

DDR_DQS0N DDR_DQS0P

19 19

DDR_DQS1N DDR_DQS1P

19 19

DDR_DQS2N DDR_DQS2P

19 19

DDR_DQS3N DDR_DQS3P DDR_A[14..0]

19 19 19

19

C

VDDIO_DDR

Unmount DDR_RESET_N

1 10KR1J 2 R48

/@

0906 NV change to UM

B

No Use No Use DDR_CLKN DDR_CLKP DDR_RESET_N

19

R49 1 0R1J 1 0R1J R52

R50 45.3R2F N/A

2 /@ 2 /@

19 19

1

MAX77663 SD3(2A)

(1.2/1.25/1.35/1.5)

VDDIO_DDR_01 VDDIO_DDR_02 VDDIO_DDR_03 VDDIO_DDR_04 VDDIO_DDR_05 VDDIO_DDR_06 VDDIO_DDR_07 VDDIO_DDR_08 VDDIO_DDR_09 VDDIO_DDR_10 VDDIO_DDR_11 VDDIO_DDR_12 VDDIO_DDR_13 VDDIO_DDR_14 VDDIO_DDR_15 VDDIO_DDR_16

R51 45.3R2F N/A 2

0620

G16 G19 H15 H16 H18 H19 H21 H22 J15 J16 J18 J19 J21 J23 K22 K23

1

+1.35V

VDDIO_DDR

2

from PMIC

VDDIO_DDR

DDR_CLK_R_C

DDR_COMP_PD

B21

DDR_COMP_PU

B15

DDR_COMP_PD

1

40.2R2F R54

VDDIO_DDR 2

DDR_COMP_PU

1

Unmount R53 1 40.2R2F 2 N/A 2 N/A

C51 0.01U10VX7RC1K N/A

T30L-R-P-A3 N/A

A

A

Title : T30 DDR Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 8

of

60

5

4

3

2

1

0502

1.2V

T30 VI


AVDD_DSI_CSI

T30 GPIO

T30S pin

VI_MCLK

PRO_RST#

BB

AA1

VI_PCLK

HDMI_VBUS_EN_OC#

BB

W5

VI_HSYNC VI_VSYNC

EN_VDDIO_SD EN_VDD_MC

BB BB

PUPD

W5 AA3

2

1 2


1

AVDD_DSI_CSI

D

VI_DO0 VI_DO1 VI_DO2 VI_DO3 VI_DO4 VI_DO5 VI_DO6 VI_DO7 VI_DO8 VI_DO9 VI_DO10 VI_DO11


BAT_IN_CPU# COMPASS_DRDY ALS_INT#_MB GS_INT LVDS_SHTDN# CAM_RST_2M EN_VDD_PNL DSP_RST# EN_VDD_FUSE EN_HVDD_PEX DSP_PWDN# SDMMC1_WP

BB BB BB BB LCD CAM UART BB UART XX CAM AUDIO

V4 AC11 AF6 AA9 AP18 AM14 AG33 V8 AM36 X AM16 D36

GPIO

0620 U2H 7/22 DSI & CSI (1.2V)

AVDD_DSI_CSI

CSI_CLKAN CSI_CLKAP

1.2V

CSI_D1AN CSI_D1AP CSI_D2AN CSI_D2AP

C

CSI_CLKBN CSI_CLKBP CSI_D1BN CSI_D1BP CSI_D2BN CSI_D2BP

DSI_CLKAN DSI_CLKAP DSI_D1AN DSI_D1AP DSI_D2AN DSI_D2AP

DSI_CSI_RUP

AD3 AD2

CSI_D1AN CSI_D1AP

AE2 AE3

CSI_D2AN CSI_D2AP

AG3 AG2

CSI_CLKBN CSI_CLKBP

AD1 AE1

CSI_D1BN CSI_D1BP

CSI_CLKAN CSI_CLKAP

31 31

CSI_D1AN CSI_D1AP

31 31

CSI_D2AN CSI_D2AP

31 31

CSI_CLKBN CSI_CLKBP CSI_D1BN CSI_D1BP

After Wake

D00

DOWN

15K

PD

Disable

Hold

D01

DOWN

15K

PD

Disable

Hold

D02

DOWN

15K

PD

Disable

Hold

D03

DOWN

15K

PD

Config.

Hold

D04

DOWN

15K

PD

Disable

Hold

D05

DOWN

15K

PD

Disable

Hold

D06

DOWN

15K

PD

Disable

Hold

D07

DOWN

15K

PD

Disable

Hold

D08

DOWN

15K

PD

Disable

Hold

D09

DOWN

15K

PD

Disable

Hold

D10

DOWN

15K

PD

Disable

Hold

D11

DOWN

15K

PD

Disable

Hold

MCLK

DOWN

15K

PD

Disable

Hold

PCLK

DOWN

15K

PD

Disable

Hold

HSYNC

DOWN

15K

PD

Disable

Hold

VSYNC

DOWN

15K

PD

Disable

Hold

D

Camera 1 (Rear)

C

31 31

Camera 2 (Front)

31 31

AH2 AH1

AA1 AB1 AB2 AB3

AVDD_DSI_CSI

AA2 AA3

R56 453R2F N/A

AG4

DSI_CSI_RUP

AJ3

DSI_CSI_RDN

AB4

DSI_CSI_TEST_OUT

2

DSI_CSI_RDN

CSI_CLKAN CSI_CLKAP

PUPD

2

AVDD_DSI_CSI

AC4 AD4

Deep Sleep PinState

1

AB6

POR

VDDIO_VI

R57 49.9R2F N/A R58 49.9R2F N/A

B

1.8V

PUPD

PinState

PUPD

After Wake

PBB0

None

Z

Config.

Hold

PBB3

None

Z

Config.

Hold

PBB4

None

Z

Config.

Hold

PBB5

None

Z

Config.

Hold

PBB6

None

Z

Config.

Hold

0626

PBB7

None

Z

Config.

Hold

VDD_1V8_GEN

PCC1

UP

50K

PU

Config.

Hold

PCC2

UP

50K

PU

Config.

Reset

0626 VDD_1V8_GEN_CPU

VDDIO_CAM_T30S

0626

C55 N/A 4.7U6.3VX5RC2M

1

U2G

R59 2.2KR1J N/A

0626

R60 2.2KR1J N/A 2

18/22 CAM

2

1


2

2

1

VDD_1V8_GEN

1

0626 VDDIO_CAM_T30S

Deep Sleep

POR

VDDIO_CAM

1

T30L-R-P-A3 N/A

1

2

DSI_CSI_TEST_OUT B

(1.8/2.8 ~ 3.3V)

VDDIO_CAM

1.8V

CAM_I2C_SCL CAM_I2C_SDA CAM_MCLK GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7

A

AG5 AH7

CAM_I2C_SCL CAM_I2C_SDA

AD5

VI_MCLK

AF6 AD6 AG7 AE5 AE6 AE7

CAM_RST_5M

CAM_I2C_SCL 25,26,31,44 CAM_I2C_SDA 25,26,31,44 1

PWDN_5M CAM2_PWDN PWDN_2M

CAM_RST_5M

31

PWDN_5M

31

PWDN_2M

31

R61 N/A 33R2J 2

1

AD9

2

VDDIO_CAM_T30S

C56 /@ 33P25VNPOC1J

CAM_MCLK

31

CW/0228 Check SI

A

Unmount 12/23 RF add 33P

GPIO_PCC1 GPIO_PCC2

AC6 NC AG6

FRONT_SEL TEMP_ALERT#

TEMP_ALERT# 26

Title : T30 DSI/CSI,CAM

T30L-R-P-A3 N/A

Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T

Tuesday, March 20, 2012

Sheet 1

2.0 9

of

60

5

4

3

2

1

U2I 8/22 LCD

1.8V

VDD_1V8_GEN_CPU

1.8V

VDDIO_LCD

AB13 AC13

VDDIO_LCD

VDDIO_LCD_1 VDDIO_LCD_2 (1.8 ~ 3.3V)

LCD_PCLK LCD_WR_N LCD_DE LCD_HSYNC LCD_VSYNC

D

1

VDDIO_LCD

1 1

LCD_D00 LCD_D01 LCD_D02 LCD_D03 LCD_D04 LCD_D05 LCD_D06 LCD_D07 LCD_D08 LCD_D09 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17 LCD_D18 LCD_D19 LCD_D20 LCD_D21 LCD_D22 LCD_D23

N/A 2 C57 0.1U6.3VX5RC1K N/A 2 C58 0.1U6.3VX5RC1K C59 N/A 2 0.1U6.3VX5RC1K

AG11

LCD_PCLK

AH16 AG9 AF16 AF10

SNN_LCD_ER# LCD_DE LCD_HSYNC LCD_VSYNC

AE8 AF12 AD10 AK15 AK16 AK10 AK12 AG16 AG8 AD15 AK9 AJ12 AF9 AC12 AD12 AE18 AF13 AH15 AE9 NC AE10 NC AH13 NC AH9 NC AE13 NC AK13 NC

LCD_D0 LCD_D1 LCD_D2 LCD_D3 LCD_D4 LCD_D5 LCD_D6 LCD_D7 LCD_D8 LCD_D9 LCD_D10 LCD_D11 LCD_D12 LCD_D13 LCD_D14 LCD_D15 LCD_D16 LCD_D17

LCD_PCLK

22

LCD_DE 22 LCD_HSYNC 22 LCD_VSYNC 22 LCD_D[17..0] 22

D

POR

VDDIO_LCD

PUPD LCD_M1

LCD_PWR0 LCD_PWR1 LCD_PWR2 LCD_SCK LCD_CS0_N LCD_CS1_N LCD_SDOUT LCD_SDIN

C

LCD_DC0 LCD_DC1

CRT_HSYNC CRT_VSYNC DDC_SCL DDC_SDA HDMI_INT

EN_VDD_PNL

EN_VDD_PNL1

AJ9 NC AG10 AH12 NC

EN_VDD_FUSE

SNN_LCD_PWR0 EN_3V3_FUSE SNN_LCD_PWR2

AG15 AJ15 AC10 AJ13 AH10

COMPASS_DRDY

SDMMC_WP* BAT_DET* COMPASS_DRDY SNN_LCD_SDOUT ALS_IRQ*

AG12

AE15 AE12

ALS_INT#_MB LVDS_SHTDN#

LVDS1_SHTDN* SNN_LCD_DC1

EN_VDD_PNL

21,48

EN_VDD_FUSE

PUPD

After Wake

DOWN

100K

PD

Disable

Hold

LCD_PWR0 DOWN

100K

PD

Disable

Hold

LCD_PWR1 DOWN

100K

PD

Disable

Hold

LCD_PWR2 DOWN

100K

PD

Disable

Hold

LCD_SCK

UP

100K

PU

Disable

Hold

LCD_CS0_N UP

100K

PU

Disable

Hold

LCD_CS1_N UP

100K

PU

Disable

Hold

LCD_SDOUT UP

100K

PU

Disable

Hold

LCD_SDIN UP LCD_M1

Deep Sleep PinState

100K

PU

Disable

Hold

LCD_DC0

DOWN

100K

PD

Disable

Hold

LCD_DC1

DOWN

100K

PD

Disable

Hold

0502

5

0621 COMPASS_DRDY ALS_INT#_MB

25

LVDS_SHTDN#

22

26

C

0721 SNN_CRT_HSYNC SNN_CRT_VSYNC

AD13 AJ16 AG14 AJ10 AG13

T30L-R-P-A3 N/A

B

B

A

A

Title : T30 LCD Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 10

of

60

5

4

3

2

1

3.3V U2K 10/22 HDMI

3.3V AE4 AF4

AVDD_HDMI_1 AVDD_HDMI_2

HDMI_TXCN HDMI_TXCP

(3.3V)

HDMI_TXD0N HDMI_TXD0P

1.8V


D


1.8V AF7

AVDD_HDMI_PLL (1.8V)

HDMI_PROBE HDMI_RSET

AK3 AK4 AJ4 AH4

HDMI Conn.

AH6 AJ6

D

AK7 AJ7 AG1 AH3

T30L-R-P-A3

All HDMI pins & powers leave NC when HDMI is not be used. U2J 9/22 VDAC

AK6

AVDD_VDAC

VDAC_R VDAC_G VDAC_B

(2.8V)

VDAC_VREF VDAC_RSET

C

AB7 AA9 AA7

AA5 AA6 C

T30L-R-P-A3

All VDAC pins & powers leave NC CEC

B

B

0818 NC son't support CEC

A

A

Title : T30 HDMI,VGA Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 11

of

60

5

4

3

U2S

2

1

Note: 'EN_VDD_SDMMC1' reserved for power gating

12/22 BB

W1

VDDIO_BB

ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7

(1.8/3.3V)

1.8V

VDD_1V8_GEN_CPU

VDDIO_BB

D

1

VDDIO_BB

1

ULPI_CLK ULPI_DIR ULPI_NXT ULPI_STP

N/A 2 C69 1U6.3VX5RC2K N/A 2 C70 0.1U6.3VX5RC1K

DAP3_DIN DAP3_DOUT DAP3_FS DAP3_SCLK

GPIO_PV0 GPIO_PV1

R3 V1 N1 T3 P4 T4 T1 T2

UART1_TXD UART1_RXD WLAN_MAC_WAKEN NC NC CAM_RST_2M

R1 R2

WLAN_MAC_WAKEN

No Use CAM_RST_2M

NC

PUPD

41

GPIO

31

Debug??

CDC_LDO1_EN

EN_VDD_SDMMC1 EN_VDDIO_VID_OC* EN_3V3_MODEN SNN_DAP3_SCLK

SNN_D_AP_ONKEY# SNN_D_AP_ACOK#

AP_ONKEY# AP_ACOK#

CDC_LDO1_EN

27

DSP_1V8_EN -> CODEC_1V8_EN

AP_ONKEY# AP_ACOK#

33 33

T30L-R-P-A3

JTAG N/A

PinState

After Wake

UP

100K

PU

Disable

Hold

DATA1

UP

100K

PU

Disable

Hold

DATA2

UP

100K

PU

Disable

Hold

DATA3

UP

100K

PU

Config.

Hold

DATA4

UP

100K

PU

Config.

Hold

DATA5

UP

100K

PU

Disable

Hold

DATA6

UP

100K

PU

Disable

Hold

DATA7

UP

100K

PU

Disable

Hold

PV0

None

Z

Config.

Hold

PV1

None

Z

Config.

Hold

POR PUPD

不不不不不, 需需TX/RX GND

PUPD

DATA0

VDDIO_BB

GPI : Disable SD card write protection

Deep Sleep

POR

VDDIO_BB

Debug??

UART4_TXD UART4_RXD

M2 M4 N2 N4

N3 M3 R4 R6

DEBUG_GPIO0 DEBUG_GPIO1 DBG_IRQ# WF_WAKEUP ACC_IRQ* SNN_ULPI_DATA5 SNN_ULPI_DATA6 SNN_ULPI_DATA7

D

Deep Sleep PUPD

After Wake

DAP3_DIN

DOWN 100K

PinState PD

Disable

Hold

DAP3_DOUT

DOWN 100K

PD

Disable

Hold

DAP3_FS

DOWN 100K

PD

Disable

Hold

DAP3_SCLK

DOWN 100K

PD

Disable

Hold

VDD_1V8_GEN_CPU

Unmount UART4_TXD

1 0R1J

2 R69

/@

UART4_RXD

1 0R1J

2 R70

/@

UART1_TXD

1 0R1J

2 R72

N/A

UART1_RXD

1 0R1J

2 R73

N/A

1

1.8V VDDIO_BB

R71 1MR1J /@

Unmount

C

2

C

UART_DEBUG_TXD

24,28 24,28

1

UART_DEBUG_RXD

1.8V

AA30

(1.8/3.3V)

1

GEN1_I2C_SCL GEN1_I2C_SDA UART2_TXD UART2_RXD UART2_RTS_N UART2_CTS_N

VDDIO_UART

2

UART3_TXD UART3_RXD UART3_RTS_N UART3_CTS_N


Z Z Z Z Z Z Z

B

GPIO_PU0 GPIO_PU1 GPIO_PU2 GPIO_PU3 GPIO_PU4 GPIO_PU5 GPIO_PU6 DAP4_DIN DAP4_DOUT DAP4_FS DAP4_SCLK

CLK3_OUT CLK3_REQ

2

1

Cardhu use 4.7K

GEN1_I2C no use KAI -- ALS, Compass, Gyro, NFC I2C connect to GEN1 I2C Current connect to CAM_I2C

2

1.8V

VDDIO_UART

0902 R76 4.7KR1J N/A

2

14/22 UART

VDDIO_UART VDDIO_UART

+3VSUS_CPU

R75 4.7KR1J N/A

U2R

VDD_1V8_GEN_CPU

1

+3VSUS_CPU

0906 NV change 2.2K -> 4.7K

R74 1MR1J N/A

AB25 V29


W25 AB28 AB26 AA25

GPS_UART2_TXD GPS_UART2_RXD GPS_UART2_RTS# GPS_UART2_CTS#

GPS_UART2_TXD 43 GPS_UART2_RXD 43 GPS_UART2_RTS# 43 GPS_UART2_CTS# 43

AC27 W27 AB29 W29

BT_UART3_TXD BT_UART3_RXD BT_UART3_RTS# BT_UART3_CTS#

BT_UART3_TXD 41 BT_UART3_RXD 41 BT_UART3_RTS# 41 BT_UART3_CTS# 41

AA28 V30 AB30 AB27 AC25 W30 AA27

BT_EN BT_WAKEUP GPS_PWRON

AA29 W28 AA24 AA26

DAP4_DIN DAP4_DOUT DAP4_FS DAP4_SCLK

Y27 W24

DOCK_IN# AP_CHARGING# BT_IRQ#


BT_EN BT_WAKEUP GPS_PWRON GPS_RST* MB_DET_DOCK* GPS_IRQ# BT_IRQ*

BT_EN BT_WAKEUP GPS_PWRON

GPS UART BT UART

40,41 40,41 40,43

GPIO DOCK_IN# -> MAX8903B_CHG#_1V8

DOCK_IN# 28 AP_CHARGING# 33 BT_IRQ# 41

VDDIO_UART

POR

Deep Sleep

PUPD

PinState

PUPD

After Wake

PU0

None

Z

Disable

Hold

PU1

None

Z

Disable

Hold

PU2

None

Z

Disable

Hold

PU3

None

Z

Disable

Hold

PU4

None

Z

Disable

Hold

PU5

None

Z

Config.

Hold

PU6

None

Z

Config.

Hold

B

williams 0602 DAP4_DIN DAP4_DOUT DAP4_FS DAP4_SCLK

41 41 41 41

BT PCM

CLK3_OUT CLK3_REQ

T30L-R-P-A3 N/A

A

A

Title : T30 BB,UART Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 12

of

60

5

4

3

2

1

D

D

VDD_1V8_GEN_CPU

VDD_IO_AUDIO

2

1.8V

1

VDD_IO_AUDIO


U2Q

Change

13/22 AUDIO

DAP2_SCLK DAP2_FS DAP2_DOUT DAP2_DIN

C

SPDIF_IN SPDIF_OUT

SPI1_SCK SPI1_CS0_N SPI1_MOSI SPI1_MISO

C28 C29 G27 F27

H27 NC A28 NC

1

27

C74 33P25VNPOC1J /@

REMOVE FM I2S 0609

Unmount

DAP2_SCLK_H DAP2_FS_H DAP2_DOUT DAP2_DIN

R78 R79 DAP2_DOUT DAP2_DIN

27 27

C75 27P25VNPOC1J /@

SNN_SPDIF_IN SNN_SPDIF_OUT

1 33R1J 1 33R1J

2 N/A 2 N/A

DAP2_SCLK DAP2_FS

27 27

CODEC

C76 27P25VNPOC1J /@

C

Unmount

B28 J24 F29 F28 HOOK_DET#_CPU

D29 G28 F25 E27 NC B27 NC D30

HOOK_DET#_CPU CDC_IRQ# HEAD_DET# LINOUT_DET GYRO_INT

SNN_DIS_5V_SWITCH SNN_SATA_DET* HP_DET* CDC_IRQ* NFC_IRQ* GYRO_IRQ*

CDC_IRQ# HEAD_DET# LINOUT_DET NFC_IRQ_R GYRO_INT

27 28 28 44 26

GPIO

2

R234

HOOK_DET#

28

1

N/A 1 0R1J C89 27P25VNPOC1J /@

2

SPI2_SCK SPI2_CS0_N SPI2_CS1_N SPI2_CS2_N SPI2_MOSI SPI2_MISO

DAP_MCLK1

2

SNN_MODEM_AUDIO_CLK SNN_MODEM_AUDIO_CS SNN_MODEM_AUDIO_DI SNN_MODEM_AUDIO_DOUT

G29 D28 G26 G25

N/A 2


1

DAP1_SCLK DAP1_FS DAP1_DOUT DAP1_DIN

09002-00050000 R77 1 0R1J

DAP_MCLK1_H

2

(1.8/3.3V)

C27 F26 NC

1

CLK1_OUT CLK1_REQ

2

VDDIO_AUDIO

1

C30

2

1.8V VDD_IO_AUDIO

Unmount

0229 EMI add T30L-R-P-A3 N/A

POR

VDD_IO_AUDIO

PUPD SPI2_SCK B

Deep Sleep PinState

PUPD

After Wake Reset

UP

100K

PU

Disable

SPI2_CS0_N UP

100K

PU

Disable

Reset

SPI2_CS1_N UP

100K

PU

Config.

Hold

SPI2_CS2_N UP

100K

PU

Config.

Hold

SPI2_MOSI DOWN

100K

PD

Disable

Hold

SPI2_MISO DOWN

100K

PD

Disable

Hold

B

A

A

Title : T30 AUDIO Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 13

of

60

5

4

3

2

1

USB1_VBUS Q6 SI2305DS

TPS63020 buck-boost AVDD_USB

USB1_VBUS

1

1 2

1 2 AVDD_USB

Unmount

2 1

50 EN_AVDD_USB

2 N/A

D

ACOK_DOCKOK_2

6

C90 0.1U6.3VX5RC1K /@

R81 1 1MR1J

R82 100KR1J N/A

1014 TF201 add 1

0229 EMI add Close to CPU

AVDD_USB_DISCHARGE 1 330R1J 2 R66 N/A

ACOK_DOCKOK_3


2

1 2

1

NCT3521U

0720


Unmount

1 2 3 N/A

OUT GND EN

DIS

1

IN

4

2 N/A

G

USB1_VBUS

U14 5

C80 0.1U6.3VX5RC1K /@

2

3

2 /@

USB VBUS

S

D 3

R68 1 0R2J

Q5A UM6K1N N/A

MAX77663 GPIO2

Signal from MAX77663

SI2305DS 2nd Source 07G005C69010 P-MOSFET EMF44P02J SOT-23 07G005051130 P-MOSFET SI2305DS-T1-E3 SOT-2 07G005051310 P-MOSFET NTR2101PT1G SOT-23 07G00538101L P-MOSFET AP2305GN SOT-23

EN_AVDD_USB from MAX77663 GPIO2, check PU resister in PMU side(100k PU to VPH_PWR_CHGR)

AVDD_USB

0620

USB1_VBUS

1

U2L

R83 100KR1J /@

11/22 USB

N/A 2 C77 4.7U6.3VX5RC2M N/A 2 C78 0.1U6.3VX5RC1K

1 1

(3.3V)

AVDD_USB

U12

3.3V

USB1_VBUS

W5

USB1_VBUS

W3 W2

USB1_DN USB1_DP

T7

USB1_ID

2

AVDD_USB

AVDD_USB USB1_DN USB1_DP ACC1_DETECT

Unmount USB1_DN USB1_DP

28,49 28,49

USB Conn.(OTG) USB1_ID

1

0229 EMI add Close to CPU C156 0.1U6.3VX5RC1K /@

C

(1.8V)

AVDD_USB_PLL

U4

1.8V

C

Unmount

AVDD_USB_PLL

USB2_VBUS


1.8V

28

2

+3VSUS

2

3.3V

D

VDD_USB1_VBUS

USB2_DN USB2_DP ACC2_DETECT

V5

SNN_USB2_VUS

3G Module

T6 T5 W4

SNN_USB2_ID

R5

SNN_USB3_VUS

T30 AVDD_USB_PLL 1.8V AVDD_USB_PLL_1 R80 N/A 30Ohm/100Mhz 1 2

EN_AVDD_USB_PLL__SWITCH_2

3 5 4

R63 N/A 1 100KR1J 2EN_AVDD_USB_PLL__SWITCH_1

AVDD_USB_PLL

1

R62 330R1J N/A 2

C63 100P25VNPOC1J /@

2

1 2

B

AVDD_USB_PLL

1

Unmount

11

Q2 SI2305DS N/A

G

2

3 D

3

S

2

VDD_1V8_GEN


USB3_VBUS

Q3B UM6K1N N/A

USB3_DN USB3_DP

Vth=1.5V

1

ACC3_DETECT

Dock USB HUB

V3 V2 V4

SNN_USB3_ID

Y4

USB_RSET

B

2

R64 10KR1J N/A 1

USB_REXT EN_AVDD_USB_PLL_SWITCH_3

6

T30L-R-P-A3 N/A

1

R84 1KR1F N/A

Q3A UM6K1N N/A

2

6,50 CORE_PWR_REQ

2

From T30 U2N 16/22 IC_USB

SNN_AVDD_IC_USB

V9

AVDD_IC_USB (1.8V)

IC_USB_DN IC_USB_DP

IC_USB_REXT

W8 W9

SNN_IC_USB_DN SNN_IC_USB_DP

V8

SNN_IC_USB_REXT

T30L-R-P-A3 N/A

A

A

U2M 15/22 HSIC

W7

(1.2V)

VDDIO_HSIC

Note: 1. once USB1 is connected and USB1_VBUS is a wake source, our EMC, CPU would run at max frequency and voltage. 2. USB1_VBUS must be powered when force recovery mode. 3. USB1_VBUS is powered with USB_DP/N data transition, SW will recognize that a HOST PC is plugged in.

HSIC_DATA HSIC_STROBE HSIC_REXT

V6 V7

HSIC_DATA HSIC_STROBE

W6

Title : T30 USB,HSIC,ICUSB

T30L-R-P-A3 N/A

Size C Date: 5

4

3

Engineer:

ASUSTeK COMPUTER INC. EPAD

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 14

of

60

5

4

3

2

1

0620 U2E 5/22 SDMMC4 (1.2/1.8V)

1.8V

VDDIO_SDMMC4 VDD_1V8_GEN_CPU

D8

VDDIO_SDMMC4

VDDIO_SDMMC4

1.8V

D

1

VDDIO_SDMMC4

1


SDMMC4_DAT0 SDMMC4_DAT1 SDMMC4_DAT2 SDMMC4_DAT3 SDMMC4_DAT4 SDMMC4_DAT5 SDMMC4_DAT6 SDMMC4_DAT7 SDMMC4_CLK SDMMC4_CMD SDMMC4_RST_N

B9 B6 C6 A6 B7 A7 D7 D9

SDMMC4_DAT0 SDMMC4_DAT1 SDMMC4_DAT2 SDMMC4_DAT3 SDMMC4_DAT4 SDMMC4_DAT5 SDMMC4_DAT6 SDMMC4_DAT7

A9 C7

SDMMC4_CLK_T30 SDMMC4_CMD_T30

C9

SDMMC4_RST#


20 20 20 20 20 20 20 20

SDMMC4_RST#

20

SDMMC4_CLK_T30

1 N/A 0R1J 1 N/A 0R1J

N/A

Unmount MAX77663 LDO6 1

0R1J

2 R34 /@

2 R32

SDMMC4_CLK

2 R33

SDMMC4_CMD

SDMMC4_CLK

20

SDMMC4_CMD

20

C66 33P25VNPOC1J /@

0217 EMI add

Unmount

3.3V/1.8V VDD_PMU_LDO6_3V_1V8

eMMC

1 2

2

C65 33P25VNPOC1J /@

T30L-R-P-A3

1

SDMMC4_CMD_T30

D

Internal Pull-up resistors on DATA & CMD is 15K

0620 VDDIO_SDMMC1 U2P 17/22 SDMMC1

C

C

3.3V/1.8V

VDDIO_SDMMC1

(1.8/2.8 ~ 3.3V)

J1

VDDIO_SDMMC1

0229 NV recommend VDDIO_SDMMC1 connect to GND when SDMMC1 is not using VDDIO_SDMMC1

1

/@ 2 C84 4.7U6.3VX5RC2M

1

N/A 2 C85 0.1U6.3VX5RC1K 10G211000007010

Change

SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3 SDMMC1_CLK SDMMC1_CMD

Unmount

K1 K3 K2 K4

SD Card

M6 N6

Unmount

VDDIO_SDMMC1

POR

VDDIO_SDMMC1 SDMMC1_COMP_PU

C85 change to 0ohm

SDMMC1_COMP_PD

L4

SDMMC1_COMP_PU

1 33.2R1F 2 R86

/@

K6

SDMMC1_COMP_PD

1 33.2R1F 2 R87

/@

PUPD

0613Y

Deep Sleep PinState

PUPD

After Wake

GPIO_PV2

None

Z

Disable

Hold

GPIO_PV3

None

Z

Disable

Hold

SNN_GPIO_PV2 GPIO_PV2 GPIO_PV3 CLK2_OUT CLK2_REQ

M5 M1

NC NC

K5 N5

NC NC

SNN_GPIO_PV3

No Use 0614

T30L-R-P-A3 N/A

1.8V

VDD_1V8_GEN_CPU

VDDIO_SDMMC3

B

B

0620 T30s has onchip 47k pull-ups U2O

Note: 'EN_3V3_EMMC' reserved for power gating

6/22 SDMMC3 (1.8/2.8 ~ 3.3V)

VDDIO_SDMMC3

G24

VDDIO_SDMMC3

1.8V

VDDIO_SDMMC3

1 1


SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 SDMMC3_DAT4 SDMMC3_DAT5 SDMMC3_DAT6 SDMMC3_DAT7 SDMMC3_CLK SDMMC3_CMD SDMMC3_COMP_PU SDMMC3_COMP_PD

L27 J26 J28 K26 J27 K25 K24 K28

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3

G30 J29

SDMMC3_CLK SDMMC3_CMD

J25

SDMMC3_COMP_PU

K27

SDMMC3_COMP_PD

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 EN_3V3_EMMC EN_3V3_COM WF_RST* WF_EN

WF_RST# WIFI_EN

WF_RST# WIFI_EN

40 40 40 40

WIFI

PUPD

GPIO

40,41 40,41

SDMMC3_CLK 40 SDMMC3_CMD 40

POR

VDDIO_SDMMC3

WIFI

Deep Sleep PinState

PUPD

After Wake

SDMMC3_DAT4

UP

15K

PU

Config.

Hold

SDMMC3_DAT5

UP

15K

PU

Config.

Hold

SDMMC3_DAT6

UP

15K

PU

Config.

Hold

SDMMC3_DAT7

UP

15K

PU

Config.

Hold

VDDIO_SDMMC3

T30L-R-P-A3

R88 1 33.2R1F 2 N/A

N/A

1 33.2R1F 2 N/A R89

A

A

Title : T30 SDMMC,eMMC Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 15

of

60

5

4

3

2

1

U2T 20/22 PEX (1.05V)

AB18 AB19

AVDD_PEXA_1 AVDD_PEXA_2

PEX_L0_TXN PEX_L0_TXP

AG18 AF18

1.05V PEX_L0_RXN PEX_L0_RXP

D


AJ19 AH19

D

AF19 AG19

(1.05V)

AD22

VDD_PEXA

1.05V

PEX_L1_RXN PEX_L1_RXP

PEX_L2_TXN PEX_L2_TXP PEX_L2_RXN PEX_L2_RXP

(3.3V)

AB21

AK22 AK21

AJ18 AH18 AK19 AK18

HVDD_PEX

3.3V PEX_L3_TXN PEX_L3_TXP PEX_L3_RXN PEX_L3_RXP

AK24 AK25 AJ21 AH21

(1.05V)

AC22

C

AVDD_PEXB

1.05V

PEX_L4_TXN PEX_L4_TXP PEX_L4_RXN PEX_L4_RXP

3.3V

R91 1 0R2J

+3VSUS_CPU

2 /@

AG21 AF21

C

AJ24 AH24

VDDIO_PEX_CTL

Unmount


(1.05V)

AE23

AJ25 AH25

VDD_PEXB

1.05V

PEX_L5_RXN PEX_L5_RXP

AG22 AG23

(1.05V)

AE24

B

AVDD_PEX_PLL

1.05V

PEX_CLK1N PEX_CLK1P PEX_CLK2N PEX_CLK2P PEX_CLK3N PEX_CLK3P

PEX_REFCLKN PEX_REFCLKP

AK28 AK27

B

AB24 AB23 AH27 AJ27

AJ22 AH22

(3.3V)

AF24

VDDIO_PEX_CTL

AF15 AC16 AG17

AVDD_SATA

(1.05V)

VDD_SATA

(1.05V)

HVDD_SATA

(3.3V)

AVDD_SATA_PLL

A

3.3V

SATA_L0_TXN SATA_L0_TXP

(1.05V)

SATA_L0_RXN SATA_L0_RXP

SATA_TESTCLKN SATA_TESTCLKP SATA_TERMP

C88 4.7U6.3VX5RC2M 10G212000004010 N/A

AD16 AE16 AE19 AD19

2

21/22 NC

AC15

VDDIO_PEX_CTL

1

U2U

PEX_L0_CLKREQ_N PEX_L0_PRSNT_N PEX_L0_RST_N PEX_L1_CLKREQ_N PEX_L1_PRSNT_N PEX_L1_RST_N

C88 change to 0ohm (0402)

PEX_L2_CLKREQ_N PEX_L2_PRSNT_N PEX_L2_RST_N

Change

PEX_WAKE_N

AE21 AD21

PEX_TESTCLKN PEX_TESTCLKP

AD18

PEX_TERMP

AG24 AD25 AG26 AD26 AD24 AG27 AC21 AE22 AG25 AF22 A

AJ28 AH28 AG20

T30L-R-P-A3

Title : T30 PCIe

T30L-R-P-A3

Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 16

of

60

5

4

3

2

1

D

D

U2V 22/22 NC

NC38 NC39 NC40 NC41 NC42 NC43 NC44

AB10 AB5 AC19 AC9 C25 E13 H25

U2F 19/22 VI (1.2 / 1.8V)

AH30

VDDIO_VI

VI_MCLK VI_PCLK VI_HSYNC VI_VSYNC

AE26 AF25 AD27 AG30

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36

C

VI_D00 VI_D01 VI_D02 VI_D03 VI_D04 VI_D05 VI_D06 VI_D07 VI_D08 VI_D09 VI_D10 VI_D11

AF27 AD30 AH29 AG28 AE27 AE25 AG29 AD29 AE29 AD28 AE30 AE28

T30L-R-P-A3

AB11 AB14 AB17 AB20 AB22 AB9 AE11 AE14 AE17 AE20 F11 F14 F17 F20 J11 J14 J17 J20 J22 J9 L22 L25 L6 L9 P22 P25 P6 P9 U22 U25 U6 U9 Y22 Y25 Y6 Y9

C

T30L-R-P-A3 B

B

A

A

Title : T30 NC Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 17

of

60

5

4

3

Boot Source:eMMC as default

NAND_D0

7

VDD_3V3_GMI

NAND_D1

7

NAND_D2

7

NAND_D3

7

AD3 AD2 AD1 AD0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1

0502

R92 100KR1J N/A 2

D

R95 100KR1J N/A

AD[3:0] 0001 (T30S CRB)

2

2

R94 100KR1J N/A

2

R93 100KR1J N/A

1

1

1

NAND_D0 NAND_D1 NAND_D2 NAND_D3

Default value should set to 10


Note: 1. NAND_D[3:0] have internal 100K pull up.

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

2

1

Determine Boot Device to be config.

eMMC primary x4 eMMC primary x8 eMMC secondary x4 NAND D

NAND w/ block & page offset=1

Mobile LBA NAND FlexMuxOneNAND eSD x4 SPI Flash SNOR (Muxed, x16) SNOR (Muxed, x32) SNOR (Non-Muxed, x16) MuxOneNAND SATA eMMC secondary x8 Use fuse data YM 0502 DG05576900 V1.3 P75

RAM Code

7

NAND_D5 R102 100KR1J /BOOTSTRAP/DDR

7

NAND_D6

7

NAND_D7

7

AD5 AD4 SKU1&3 SKU2&4

2

2

/@/BOOTSTRAP/eMMC

NAND_D4

1

1 R100 100KR1J /@/BOOTSTRAP/DDR

R98 100KR1J

2

VDD_3V3_GMI

2

R96 100KR1J /@/BOOTSTRAP/eMMC C

VDD_3V3_GMI

1

VDD_3V3_GMI

1

VDD_3V3_GMI

AD[7:0] 0000 (T30S CRB) R100

Select Memory Type

ELPIDA DDR3LRS 256MBx4 EDJ2108EDBG-DJL-F Hynix DDR3LM 256MBx4 H5TC2G83CFR-H9R

R101

R102

V

03006-00030900 03006-00031200

V

R103 V

V C

TBD

V

TBD

V

V V

1

AD7 AD6 SKU1&2

Remove RECOVERY_MODE# & DEV_MODE# Default value should set to 00

0 1 0 1

20120302

R103 100KR1J /@/BOOTSTRAP/DDR 2

R99 100KR1J /BOOTSTRAP/eMMC

2

R101 100KR1J /BOOTSTRAP/DDR

2

2

R97 100KR1J /BOOTSTRAP/eMMC

1

1

1

NAND_D4 NAND_D5 NAND_D6 NAND_D7

0 0 1 1

SKU3&4


0 0 1 1

R96

Select eMMC Type

0 1 0 1

HYNIX 8GB Kingston 8GB

H26M42001FMR KE44B-26BN

FBGA-153 FBGA169

R97

R98

V

03100-00120000 05G002514010

V

TBD

V

TBD

V

R99 V

V V V

Note: 1. NAND_D[7:4] do NOT have internal 100K pull up.

For what?

F_RECOVERY#

24,32 7

NAND_CLE

7,26

NAND_ALE

7

NAND_WE#

7

2

R108 100KR1J N/A 2

R107 100KR1J N/A

0502

N/A 1 47KR1J 2 R105

NAND_RE# NAND_CLE NAND_ALE NAND_WE#

1

1

1

2

R106 47KR1J N/A

2

R104 100KR1J N/A

R109 0R1J /@

F_RECOVERY#

Unmount Default value should set to 10

NAND_CLE

NAND_ALE

0 0 1 1

0 1 0 1

RECOVERY

0 1

2

B

NAND_RE#

1

VDD_3V3_GMI

1

VDD_3V3_GMI

Description Serial JTAG chain, MPCORE and AVP B

MPCore only JTAG AVP only JTAG Reserved

Description USB Recovery Mode Boot from secondary device


A

A

Title : Boot Straps Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 18

of

60

1 1 1

VDD_DDR3L

1 1 1

C

1 1 1 1 1 1 1

VDDQ_DDR3L

N/A 2 C107 10U6.3VX5RC3M N/A 2 C109 0.1U6.3VX5RC1K N/A 2 C111 0.1U6.3VX5RC1K N/A 2 C113 0.1U6.3VX5RC1K N/A 2 C115 0.1U6.3VX5RC1K N/A 2 C117 0.1U6.3VX5RC1K C119 N/A 2 0.1U6.3VX5RC1K C121 N/A 2 0.1U6.3VX5RC1K N/A 2 C123 0.1U6.3VX5RC1K N/A 2 C125 4.7U6.3VX5RC2M

1 1 1 1 1

VDD_DDR3L

8 DDR_DM[3..0]

8

1 1 1 1 1 1 1 1 1

DDR_CS0_N DDR_CS1_N

8 8

DDR_CLKP DDR_CLKN

8

DDR_CKE0

8 8

DDR_RAS_N DDR_CAS_N

1

2

DDR_VREFDQ

C127 0.1U6.3VX5RC1K N/A

1

2

R114 7.5KOhm N/A 1%

8

DDR_WE_N

8 8 8


2

VDD_DDR3L

1

2

DDR_VREFCA

1

R115 7.5KOhm N/A 1%

C132 0.1U6.3VX5RC1K N/A

DDR_DQS0N DDR_DQS0P

8 8

DDR_DQS1N DDR_DQS1P

8 8

DDR_DQS2N DDR_DQS2P

8 8

DDR_DQS3N DDR_DQS3P 8

DDR_ODT0_N

1

2

R118 7.5KOhm N/A 1%

8 8

8 DDR_RESET_N

N/A 1 243R1F 2 R111

F7 G7 G9 G1 H2 F3 G3 H3 C3 D3

DDR_DM0

A7 B7

DDR_RESET_N

N2

DDR3L_ZQ0_0

H8

F1 F9 H1 H9 J7

DDR_CS1_N

DDR_CS0_N DDR_CS1_N DDR_CLKP DDR_CLKN DDR_CKE0 C128 N/A 0.1U6.3VX5RC1K C131 0.1U6.3VX5RC1K N/A

DDR_RAS_N DDR_CAS_N

1

R113 7.5KOhm N/A 1%

B

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14

J2 K8 J3

A3

2

VDD_DDR3L

8 8

DDR_ODT0_N DDR_CS0_N DDR_RAS_N DDR_CAS_N DDR_WE_N DDR_DQS0P DDR_DQS0N

DDR_A[14..0]

N/A 2 C108 10U6.3VX5RC3M N/A 2 C110 0.1U6.3VX5RC1K N/A 2 C112 0.1U6.3VX5RC1K N/A 2 C114 0.1U6.3VX5RC1K N/A 2 C116 0.1U6.3VX5RC1K N/A 2 C118 0.1U6.3VX5RC1K C120 N/A 2 0.1U6.3VX5RC1K C122 N/A 2 0.1U6.3VX5RC1K N/A 2 C124 0.1U6.3VX5RC1K N/A 2 C126 4.7U6.3VX5RC2M

1

DDR_CLKP DDR_CLKN DDR_CKE0


1

1

1

1

N/A 2 C96 10U6.3VX5RC3M N/A 2 C97 0.1U6.3VX5RC1K N/A 2 C99 0.1U6.3VX5RC1K N/A 2 C102 0.1U6.3VX5RC1K N/A 2 C104 0.1U6.3VX5RC1K N/A 2 C106 4.7U6.3VX5RC2M

1

2

VDDQ_DDR3L

N/A 2 C93 10U6.3VX5RC3M N/A 2 C100 0.1U6.3VX5RC1K N/A 2 C98 0.1U6.3VX5RC1K N/A 2 C101 0.1U6.3VX5RC1K N/A 2 C103 0.1U6.3VX5RC1K N/A 2 C105 4.7U6.3VX5RC2M

2

1


DDR_WE_N DDR_BA0_N DDR_BA1_N DDR_BA2_N

03006-00031200 U5 HYNIX/H5TC2G83CFR-H9R /DDR DDR_VREFCA J8 B3 DQ0 DDR_VREFDQ E1 VREFCA C7 VREFDQ DQ1 C2 DQ2 DDR_A0 K3 C8 A0 DQ3 DDR_A1 L7 E3 A1 DQ4 DDR_A2 L3 E8 A2 DQ5 DDR_A3 K2 D2 A3 DQ6 DDR_A4 L8 E7 A4 DQ7 DDR_A5 L2 A5 DDR_A6 M8 A6 DDR_A7 M2 A7 DDR_A8 N8 A8 DDR_A9 M3 A9 DDR_A10 H7 A10/AP DDR_A11 M7 A11 DDR_A12 K7 A12/BC# DDR_A13 N3 A13 DDR_A14 N7 A14


J2 K8 J3

BA0 BA1 BA2

DDR_DQS0N DDR_DQS0P DDR_CLKP DDR_CLKN DDR_CKE0

DDR_DQS1N DDR_DQS1P DDR_DQS2N DDR_DQS2P

DDR_ODT0_N DDR_CS0_N DDR_RAS_N DDR_CAS_N DDR_WE_N

DDR_DQS3N DDR_DQS3P

F7 G7 G9 G1 H2 F3 G3 H3

CK CK# CKE ODT CS# RAS# CAS# WE#

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9

VDDQ1 VDDQ2 VDDQ3 VDDQ4


BA0 BA1 BA2



1

1

2

2

1

03006-00031200 U4 HYNIX/H5TC2G83CFR-H9R /DDR DDR_VREFCA J8 DQ0 DDR_VREFDQ E1 VREFCA VREFDQ DQ1 DQ2 DDR_A0 K3 A0 DQ3 DDR_A1 L7 A1 DQ4 DDR_A2 L3 A2 DQ5 DDR_A3 K2 A3 DQ6 DDR_A4 L8 A4 DQ7 DDR_A5 L2 A5 DDR_A6 M8 A6 DDR_A7 M2 A7 DDR_A8 N8 A8 DDR_A9 M3 A9 DDR_A10 H7 A10/AP DDR_A11 M7 A11 DDR_A12 K7 A12/BC# DDR_A13 N3 A13 DDR_A14 N7 A14

C95 N/A 0.1U6.3VX5RC1K C94 0.1U6.3VX5RC1K N/A

A2 A9 D7 G2 G8 K1 K9 M1 M9

VDD_DDR3L

B9 C1 E2 E9

VDDQ_DDR3L


RESET#

ZQ

NC1

F7 G7 G9

DDR_ODT0_N DDR_CS0_N DDR_RAS_N DDR_CAS_N DDR_WE_N

G1 H2 F3 G3 H3

DDR_DQS1P DDR_DQS1N

DQS DQS# NU/TDQS# DM/TDQS

J2 K8 J3

DDR_CLKP DDR_CLKN DDR_CKE0

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5

A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9

N/A 1 243R1F 2 R112

C3 D3

DDR_DM1

A7 B7

DDR_RESET_N

N2

DDR3L_ZQ1_0

H8

B2 B8 C9 D1 D9

A3

NC2 NC3 NC4 NC5 NC6

F1 F9 H1 H9 J7

DDR_CS1_N

DDR_DQ25 DDR_DQ30 DDR_DQ26 DDR_DQ24 DDR_DQ31 DDR_DQ28 DDR_DQ29 DDR_DQ27

1

03006-00031200 Hynix DDR3LM 256MBx4 H5TC2G83CFR-H9R


2

03006-00030900 ELPIDA DDR3LRS 256MBx4 EDJ2108EDBG-DJL-F


B3 C7 C2 C8 E3 E8 D2 E7

1

D

MAX77663 SD3(2A)

2


2

+1.35V from PMIC


VDD_DDR3L

1

8 DDR_DQ[31..0]

VDDQ_DDR3L

2

3

1

4

2

5



A2 A9 D7 G2 G8 K1 K9 M1 M9

VDD_DDR3L

B9 C1 E2 E9

VDDQ_DDR3L


DDR_CLKP DDR_CLKN DDR_CKE0 DDR_ODT0_N DDR_CS0_N DDR_RAS_N DDR_CAS_N DDR_WE_N

J2 K8 J3

F7 G7 G9 G1 H2 F3 G3 H3

BA0 BA1 BA2






A2 A9 D7 G2 G8 K1 K9 M1 M9

VDD_DDR3L

B9 C1 E2 E9

VDDQ_DDR3L

DQS DQS# NU/TDQS# DM/TDQS RESET#

ZQ

NC1

A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12

C

B2 B8 C9 D1 D9

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5

NC2 NC3 NC4 NC5 NC6


B3 C7 C2 C8 E3 E8 D2 E7

B

A2 A9 D7 G2 G8 K1 K9 M1 M9

VDD_DDR3L

B9 C1 E2 E9

VDDQ_DDR3L

DDR_ODT0_N DDR_DQS3P DDR_DQS3N

C3 D3

DDR_DQS2P DDR_DQS2N

DQS DQS#

C3 D3

DQS DQS#

DDR_RESET_N

N/A 1 243R1F 2 R116

DDR_DM3

A7 B7

DDR_RESET_N

N2

DDR3L_ZQ3_0

H8

NU/TDQS# DM/TDQS RESET#

ZQ

A

A3

DDR_CS1_N

F1 F9 H1 H9 J7

NC1


NC2 NC3 NC4 NC5 NC6

A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9

N/A 1 243R1F 2 R117

DDR_DM2

A7 B7

DDR_RESET_N

N2

DDR3L_ZQ2_0

H8

B2 B8 C9 D1 D9

A3

DDR_CS1_N

F1 F9 H1 H9 J7

NU/TDQS# DM/TDQS RESET#

ZQ

NC1

NC2 NC3 NC4 NC5 NC6


A1 A8 B1 D8 F2 F8 J1 J9 L1 L9 N1 N9

A

B2 B8 C9 D1 D9

Title : DDR3L C Date:

4

3

2

Engineer:


5

D


BA0 BA1 BA2


B3 C7 C2 C8 E3 E8 D2 E7

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 19

of

60

5

4

3

2

1

eMMC I/F

MAX77663 SD2 (2A) D

D

1.8V

VDD_1V8_GEN

VDDIO_HSMMC

0906 NV add VDDIO_HSMMC

1 1


VDDIO_HSMMC

1 1 1

2.8V

N/A 2 C134 1U6.3VX5RC2K N/A 2 C136 0.1U6.3VX5RC1K N/A 2 C137 0.1U6.3VX5RC1K

03100-00120000 HYNIX 8GB

H26M42001FMR

FBGA-153

05G002514010 Kingston 8GB

KE44B-26BN

FBGA169


VCORE_eMMC_S

0906 NV add C

VCORE_eMMC_S

1 1 1

N/A 2 C150 1U6.3VX5RC2K N/A 2 C138 0.1U6.3VX5RC1K N/A 2 C151 0.1U6.3VX5RC1K

1

VCORE_eMMC_S

1


C

YM 0502 DG05576900 V1.3 P63 CW/0320 Change to 4.7K by Cardhu.

15 15 15 15 15 15 15 15

1 2

R120 4.7KR1J N/A

2

1

VDDIO_HSMMC

R121 4.7KR1J /@

Unmount



SDMMC4_CMD SDMMC4_CLK

15 SDMMC4_CMD 15 SDMMC4_CLK

SDMMC4_RST#

SDMMC4_RST#_eMMC

B

KAI ref. design

1

1 /@

/@

2

/@

2

1

1 /@

2

/@

2

1

1 /@

2

/@

2

1

1 /@

2

/@

2

1

1 /@

2

/@

2

R402 /@ SDMMC4_RST#_eMMC 1 2 0R1J 1 2 0R1J N/A R403

2

15 SDMMC4_RST# 6,32,50 SYS_RESET#

1

Unmount

B

EMI C146 C148 C142 C144 C149 C147 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J C139 C141 C143 C145 33P25VNPOC1J C172 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J 33P25VNPOC1J

SDMMC4_DAT6 SDMMC4_DAT5 SDMMC4_DAT4 SDMMC4_DAT3 SDMMC4_DAT2 SDMMC4_DAT1 SDMMC4_DAT0

SDMMC4_DAT7 J6 J5 J4 J3 J2 H5 H4 H3

SDMMC4_CMD SDMMC4_CLK

W5 W6

SD I/F DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 CMD CLK

POWER/GND VCORE_eMMC_S

M6 N5 T10 U9

VDDIO_HSMMC

K6 W4 Y4 AA3 AA5

A

K2

VCCQ0 VCCQ1 VCCQ2 VCCQ3 VCCQ4

VSS0 VSS1 VSS2 VSS3 VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4

M7 P5 R10 U8 K4 Y2 Y5 AA4 AA6

VCCI

1

VCCI_EMMC

VCC0 VCC1 VCC2 VCC3

HYNIX H26M42001FMR 03100-00120000

2

C154 2.2U6.3VX5RC2M

HYNIX H26M42001FMR 03100-00120000

N/A

Footprint 12x16_14x18 colay

AH11 AH9 AH6 AH4 AG13 AG2 AE14 AE1 AA14 AA13 AA12 AA11 AA10 AA9 AA8 AA7 AA2 AA1 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y3 Y1 W14 W13 W12 W11 W10 W9 NC138 NC137 NC136 NC135 NC134 NC133 NC132 NC131 NC130 NC129 NC128 NC127 NC126 NC125 NC124 NC123 NC122 NC121 NC120 NC119 NC118 NC117 NC116 NC115 NC114 NC113 NC112 NC111 NC110 NC109 NC108 NC107 NC106 NC105 NC104

NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34

NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC86 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68

U7A /eMMC

Unmount

NC103 NC102 NC101 NC100 NC99 NC98 NC97 NC96 NC95 NC94 NC93 NC92 NC91 NC90 NC89 NC88 NC87 RST_n NC85 NC84 NC83 NC82 NC81 NC80 NC79 NC78 NC77 NC76 NC75 NC74 NC73 NC72 NC71 NC70 NC69

W8 W7 W3 W2 W1 V14 V13 V12 V3 V2 V1 U14 U13 U12 U10 U7 U6 U5 U3 U2 U1 T14 T13 T12 T5 T3 T2 T1 R14 R13 R12 R5 R3 R2 R1

SDMMC4_RST#_eMMC

Check

A

Title : eMMC

K11 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M5 M8 M9 M10 L4 M12 M13 M14 N1 N2 N3 N10 N12 N13 N14 P1 P2 P3 P10 P12 P13 P14

U7B /eMMC A4 A6 A9 A11 B2 B13 D1 D14 H1 H2 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1 J7 J8 J9 J10 J11 J12 J13 J14 K1 K3 K5 K7 K8 K9 K10

Size

03100-00120000

C Date:

5

4

3

Engineer:


2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 20

of

60

5

4

3

2

1

LCD PNL power Switch TPS63020 buck-boost

3.3V

+3VSUS

VDD_PNL

VDD_PNL

VCC_LCD3V3

D

D

U8 1 N/A

2

4

IN DIS

OUT GND EN

1 2 3 N/A

1

N/A 2 C155 1U6.3VX5RC2K

NCT3521U

R125 330R1J

2

C157 0.1U6.3VX5RC1K N/A

1

5

VCC_LCD3V3_SW_DIS

EN_VDD_PNL_R R127 1MR1J N/A

1201 R1907 100K -> 1M

2

2

C158 100P25VNPOC1J /@

1

1

10,48 EN_VDD_PNL

Close to LCD Connector

Unmount

2.8~5.5V

LCD BL power Switch C

C

R128 0R3 2 N/A

0223 change from VBATT

VCC_LED 1

Remove for Hydis panel

2

1

VPH_PWR_CHGR

C161 1U6.3VX5RC2K N/A

B

B

A

A

Title : LCD panel power Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 21

of

60

4

3

U9

18bit LCD panel

1

U10

1

EMI FILTER

2

N/A U11

1

5

1

N/A

N/A

LCD_D12

7

3

LCDC_C_R0

LCD_D13

8

4

LCDC_C_R1

LCD_D14

9

5

LCDC_C_R2

LCD_D15

10

6

LCDC_C_R3

LCD_D8

7

3

LCDC_C_G2

LCD_D4

7

3

LCDC_C_B4

LCD_D9

8

4

LCDC_C_G3

LCD_D5

8

4

LCDC_C_B5

LCD_D10

9

5

LCDC_C_G4

9

5

LCD_D11

10

6

LCDC_C_G5

10

6 2

NFA21SL307X1A45L

2

NFA21SL307X1A45L NFA21SL307X1A45L 2

10 LCD_D[17..0]

N/A

U13

7

3

LCDC_C_R4

LCD_D0

7

3

LCDC_C_B0

LCD_D17

8

4

LCDC_C_R5

LCD_D1

8

4

LCDC_C_B1

LCD_D6

9

5

LCDC_C_G0

LCD_D2

9

5

LCDC_C_B2

6

LCDC_C_G1

LCD_D3

10

6

LCDC_C_B3

10

R134 1 0R2J

VDD_1V8_GEN

3.3V C

+3VSUS

R135 1 0R2J

VDD_LVDS_30 N/A 2

N/A 2

L2 N/A 120Ohm/100Mhz 1 2

2

NFA21SL307X1A45L

2

NFA21SL307X1A45L

MAX77663 SD2 (2A)

N/A

LCD_D16

LCD_D7

1.8V

1

D

U12

1

D

IOVCC_30

C

VDD_LVDS_F_30

TPS63020 buck-boost 1 L3

2

VDD_LVDS_PLL_30

EMI FILTER

120Ohm/100Mhz N/A

U39

1

VDD_LVDS_PLL_30

1

1

VDD_LVDS_F_30 B

1

1

VDD_LVDS_30

10 10 10

TF201 0906 add

LCD_HSYNC LCD_VSYNC LCD_DE

LCD_HSYNC LCD_VSYNC LCD_DE

N/A 2 C166 1U6.3VX5RC2K N/A 2 C167 0.1U6.3VX5RC1K N/A 2 C168 0.1U6.3VX5RC1K N/A 2 C140 1U6.3VX5RC2K

10 LCD_PCLK 10 LVDS_SHTDN#

LCD_PCLK LVDS_SHTDN#

N/A N/A

R143 R142

1 0R1J 1 0R1J

LCDC_PCLK_C_30 A2 LVDS_EN_30 B3

2 2

CLKP CLKM

D2 D1

2 TXECK1P_30 TXECK1N_30

R139 100R1J /@

R138 100R1J /@

1

2 2 TXE3P_30 TXE3N_30

R136 100R1J /@

1

C2 C1

R137 100R1J /@

1

J1 K4 H4 H6 E6 D6 A5

Y3P Y3M

E2 E1

2

LCDC_C_R6 LCDC_C_R7 LCDC_C_G6 LCDC_C_G7 LCDC_C_B6 LCDC_C_B7

D8 D9 D12 D13 D14 D15 D18

G2 G1

TXE0P_30 TXE0N_30

TXE0P_30 TXE0N_30

23 23

TXE1P_30 TXE1N_30

TXE1P_30 TXE1N_30

23 23

TXE2P_30 TXE2N_30

TXE2P_30 TXE2N_30

23 23

TXECK1P_30 TXECK1N_30

23 23

1 C6 B6 B5 A6 A4 B4 A3

Y2P Y2M

H2 H1

2

LCDC_C_B2 LCDC_C_B3 LCDC_C_B4 LCDC_C_B5 LCDC_HSYNC_C LCDC_VSYNC_C LCDC_DEN_C

Y1P Y1M

D19 D20 D21 D22 D24 D25 D26

VCC IOVCC2 LVDSVCC

D27 D5 D10 D11 D16 D17 D23 CLKIN SHTDN#

PLLVCC GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10

H5 G4

VDD_LVDS_30 IOVCC_30

F1

VDD_LVDS_F_30

B2

VDD_LVDS_PLL_30

A1 B1 C3 C5 D3 F2 F5 G3 H3 J5

R140 100R1J /@

1

N/A 2 C164 0.01U10VX7RC1K N/A 2 C165 0.1U6.3VX5RC1K

K6 J6 G5 G6 F6 E5 D5

Y0P Y0M

Unmount IOVCC_30

B

R141 100KR1J N/A

IOVCC1 CLKSEL

C4 D4

LVDS_R_F_30

IOVCC_30

Unmount


Unmount R9807 100K -> 1M LCDC_C_R6 LCDC_C_R7 LCDC_C_G6 LCDC_C_G7 LCDC_C_B6 LCDC_C_B7

1

SN75LVDS83BZQLR N/A

R145 100KR1J /@

For Y3P and Y3M use As Y3P and Y3M are open, so connect pin 50, 2, 8, 10, 16, 18 to GND

2

1201

2

2


R144 1MR1J N/A

1

IOVCC_30

N/A 2 C170 0.1U6.3VX5RC1K

2

1

1

1

1

N/A 2 C163 4.7U6.3VX5RC2M

LCDC_C_G1 LCDC_C_G2 LCDC_C_G3 LCDC_C_G4 LCDC_C_G5 LCDC_C_B0 LCDC_C_B1

D0 D1 D2 D3 D4 D6 D7

1

1

VDD_LVDS_30

J2 K1 K2 J3 K3 J4 K5

2

LCDC_C_R0 LCDC_C_R1 LCDC_C_R2 LCDC_C_R3 LCDC_C_R4 LCDC_C_R5 LCDC_C_G0

Unmount

For Y3P and Y3M use As Y3P and Y3M are open, so connect pin 50(D27), 2(D2), 8(D10), 10(D11), 16(D16), 18(D17) to GND

Unmount LVDS_EN_30 A

1

/@ 2 C185 0.1U6.3VX5RC1K

A

0229 EMI add

Title : LVDS transmitter_30 Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 22

of

60

5

4

3

2

1

LCD PNL power Switch From +3VSUS 3.3V


1

VCC_LCD3V3

D

From +3VSUS through SW

1

D


LCD BL power Switch N/A 2 C178 1U6.3VX5RC2K N/A 2 C179 0.1U6.3VX5RC1K

1

VCC_LED

C

4.2V

1

Unmount 2


2 2 2 2 2

EMI Cap.

C

1 C175 /@ TXE0N_R_30 0.1U6.3VX5RC1K 1 C176 /@ TXE0P_R_30 0.1U6.3VX5RC1K 1 C177 /@ TXE1N_R_30 0.1U6.3VX5RC1K 1 C180 /@ TXE1P_R_30 0.1U6.3VX5RC1K 1 C181 /@ TXE2N_R_30 0.1U6.3VX5RC1K 1 C182 /@ TXE2P_R_30 0.1U6.3VX5RC1K CON5 N/A BTOB_CON_30P

2 2

1 C183 /@ TXECK1N_R_30 0.1U6.3VX5RC1K 1 C184 /@ TXECK1P_R_30 0.1U6.3VX5RC1K

TXE0N_R_30 TXE0P_R_30 TXE1N_R_30 TXE1P_R_30 TXE2N_R_30 TXE2P_R_30 TXECK1N_R_30 TXECK1P_R_30

7

LCD_BL_PWM

LCD_BL_PWM

34 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 33

SIDE4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 SIDE3

SIDE1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 SIDE2

31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 32

VCC_LCD3V3

VCC_LED

12016-00070700 B

B

LVDS EMI Filter

22

TXE0P_30

22

TXE1N_30

22

TXE1P_30

U16

7

3

TXE0N_R_30

22

TXE2N_30

TXE0P_30

8

4

TXE0P_R_30 22

TXE2P_30

TXE1N_30

9

5

TXE1N_R_30

22

TXECK1N_30

TXE1P_30

10

6

TXE1P_R_30 22

TXECK1P_30

NFA21SL307X1A45L

1

0805 SIZE

TXE0N

2

TXE0N_30

0805 SIZE

TXE2N_30

7

3

TXE2P_30

8

4

TXE2P_R_30

TXECK1N_30 9

5

TXECK1N_R_30

6

TXECK1P_R_30

TXECK1P_3010

N/A NFA21SL307X1A45L

2

U15 22

1

CON5 2nd source MATSUSHITA/AXT530124 12G161H00307 TXE2N_R_30

N/A

A

A

Title : LCD Connector Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 23

of

60

5

4

3

2

1

D

D

0226 delete debug port power

Unmount

1

1

VDD_1V8_GEN_CPU

R147 10KR1J N/A

0705

JTAG

R149 100KR1J N/A 2

R148 10KR1J /@

1

1

1

T1 /@

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# JTAG_RTCK JTAG_RESOUT#

C

2

6 JTAG_TCK 6 JTAG_TDI 6 JTAG_TDO 6 JTAG_TMS 6 JTAG_TRST# 6 JTAG_RTCK

Debug UART

J1

2

2

R146 10KR1J N/A

1 3 5 7 9 11 13 15 17 19 21 23

1 3 5 7 9 11 13 15 17 19 21 23

2 4 6 8 10 12 14 16 18 20 22 24

2 4 6 8 10 12 14 16 18 20 22 24

UART_DEBUG_TXD UART_DEBUG_RXD

BtoB_CON_24P /@/DUG MATSUSHITA/AXK6F24347YG 12G160800244 BtoB CON 24P,0.5mm,M,1.5H,S/T

HEADER

UART_DEBUG_TXD UART_DEBUG_RXD HOT_RST# F_RECOVERY#

UART_DEBUG_TXD UART_DEBUG_RXD

HOT_RST# F_RECOVERY#

12,28 12,28

32 18,32

1 1

T15 T16

/@ /@

C

Unmount

B

B

A

A

Title : Debug Connector Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 24

of

60

5

4

3

2

1

MAX77663 SD2 (2A)

+3VSUS_CPU

VDD_1V8_GEN_CPU

R150 1MR1J N/A

1

+3VSUS_CPU

1 2

2

1

1 C187 1U6.3VX5RC2K N/A

C188 0.1U6.3VX5RC1K N/A

2

2

U17 VDD GND


1V8_O_LID#

6 D

RB520CS 2nd Source 07004-00030200 - SCHOTTKY BAT54TM SOD923 07G004045223 SCHOTTKY RB520CS-30 VMN2 [GA] ROHM 07G004250110 SCHOTTKY RB520G-30 SOD723 [GA] PANJIT

Unmount

3

2

O_LID#

TPS63020 buck-boost

R151 100KR1J N/A

D1 N/A RB520CS_30 2 1

2

PR 0217

D

1

TPS63020 buck-boost

1

Hall Sensor

Output EC2618NLB1GR 06G051025010 N/A

GND

GND

Note: 1. VDD power supply range is +2.7V to +3.3V.

C

C

Ambient Light Sensor

VDD_ALS

1 1

TPS63020 buck-boost

VDD_ALS

+3VSUS


CW/0310 Follow EP101, change P/N

VDD_ALS

U18 1 2 3

ALS_SEL

CW/0302 Change to 1.8V for ALS.

EP101 BOM

VDD GND SEL

SDA SCL INT

AL3010

N/A

6 5 4

ALS_SDA ALS_SCL ALS_INT#_MB

1.8V level

B

B

ALS_SDA ALS_SCL

CAM_I2C_SDA CAM_I2C_SCL

VDD_ALS

Slave address

7 bit 1

9,26,31,44 9,26,31,44

GND

R:00111001(39h) W:00111000(38h)

1C

VDD

R:00111101(3Dh) W:00111100(3Ch)

1D

NC

R:00111111(3Fh) W:00111110(3Eh)

1E

R155 0R1J /@ 2

VDD_1V8_GEN

R157 0R1J N/A

ALS_INT#_MB 2

10 ALS_INT#_MB

Unmount

ALS_SEL 1

R156 100KR1J N/A 2

R3137 10K -> 100K

1

1201

A

A

Title : Hall & ALS Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 25

of

60

5

4

3

2

1

Thermal Sensor 1 VDD_1V8_GEN_CPU 2

VCORE_TEMP 1

+3VSUS detect

R160 10KR1J N/A

1

TEMP_ALERT_3V3#

2 R159

TEMP_ALERT#_KAI

R163

2

1 0R1J N/A

TEMP_VDD C194 N/A 0.1U6.3VX5RC1K

2 2

TEMP_THERMD_P TEMP_THERMD_N TEMP_THERMAL#

OD

06023-00030100 8 7 6 5

VDD SCLK D+ SDATA DALERT#/THERM2# THERM# GND NCT72CMTR2G


TEMP_ALERT_3V3#

N/A VPH_PWR_CHGR

3 5

R170 1 0R1J N/A

Signal to MAX77663

50

0322 delete R640 & R641

2 1

C

1201

Note: 1. Low pass filter (R=100ohm & C=1nF) to reduce CM/DIFF noise. 2. THERM# & ALERT# provide open-drain, active low output. 3. VDD power supply range is +3.0V to +3.6V. 4. Route D+/D- tracks close together and w/ grounded guard.

C195 1uF -> 0.1uF 6

Q9A UM6K1N N/A

AP_OVERHEAT#

Q9B UM6K1N N/A

C195 0.1U16VX7RC2K N/A

2

AP_OVERHEAT# to MAX77663 SHDN, NAND_CLE reverse circuit on PMU side

2

4

2 6

2

1103 U20 06G023124010 TEMP. SENSOR NCT1008CMT3R2G change to 06023-00030100 TEMP. SENSOR NCT72CMTR2G

TEMP_THERMAL#_REV 1

1

R172 1MR1J N/A

VDD_5V0_AC_BAT R168 10KR1J N/A

50

1

THERMAL#_R

2

1201 R172 100K -> 1M

1

Signal to MAX77663

R171 10KR1J N/A

6,27,49,50 6,27,49,50

OD

VDD_1V8_GEN VDD_1V8_GEN_CPU

6

0217 KAI modify U20 1 2 3 4

N/A

C

9

NAND_CLE_THERMAL

NAND_CLE

2 1

7,18

Unmount

Gyro Sensor

+3VSUS

Q8A UM6K1N N/A

0217 KAI modify +3VSUS

E-COMPASS

VDD_GYRO

AVDD_ECOM

1


1


1

1

VDD_1V8_GEN

DVDD_ECOM N/A 2 C201 0.01U10VX7RC1K N/A 2 C202 0.1U6.3VX5RC1K

1 1 VDD_1V8_GEN

VDDIO_GYRO

R180

N/A

GYRO_CLKIN

1 100KR1J 2

R181

N/A

GYRO_CLKOUT

1 100KR1J 2

R182

N/A

VDDIO_GYRO

C206 0.01U10VX7RC1K /@

2

1 9 10 DRDY SCL VPP

U22 AVDD GND VREG

1 2 3

AMI306 N/A

R183 10KR1J /@ ECOMPASS_VREG C205 1U6.3VX5RC2K N/A

Unmount

CAD0_DAU

R184 10KR1J N/A GND

VDD_GYRO GND

GYRO_FSYNC

R185 1KR1J /@

13 GYRO_AD0

C207 0.1U6.3VX5RC1K N/A

R186 1KR1J N/A

1

T3 /@

9,25,31,44 9,25,31,44


CAM_I2C_SCL 1 0R1J CAM_I2C_SDA 1 0R1J

2 R187 2 R188

N/A N/A

MS_I2C_SCL MS_I2C_SDA

A

2

A

ECOMPASS_INT MS_I2C_SDA

Unmount 1

1

GYRO_AD0

8 7 6

GND

GYRO_INT

Unmount

10 COMPASS_DRDY

COMPASS_DRDY MS_I2C_SCL

ADDR DVDD

1 100KR1J 2

5 4

GND1 NC8 NC7 NC6 NC5 VDD

GYRO_FSYNC

SDA INT

1

02143-00010000 VDD_GYRO 18 17 16 15 14 13

AVDD_ECOM

1

GYRO_IME_DAT GYRO_IME_CLK

1

C204 100P25VNPOC1J /@

2

1

Unmount

U21 MPU-6050 N/A 1 CLKIN 2 NC1 3 NC2 4 NC3 5 NC4 6 IME_DA

AVDD_ECOM

CAD0_DAU

2

GYRO_CLKIN

0720

7 8 9 GYRO_REGOUT10 GYRO_FSYNC 11 12

CW/0223 Remove Gyro CLKIN.

DVDD_ECOM

CPOUT chage to 0.22nF C203 220P25VX7RC1K N/A

2

GYRO_SCL GYRO_SDA

GYRO_CPOUT

N/A N/A

24 23 22 21 20 19

2 R179 2 R178

MPU-6050 02134-00010000

IME_CL SDA VLOGIC SCL AD0 CLKOUT REGOUT RESV2 FSYNC CPOUT INT RESV1

1 0R1J 1 0R1J


N/A 2 C200 0.1U6.3VX5RC1K B

2

9,25,31,44 9,25,31,44

GYRO_CLKOUT

1 B

2

THERMD_N

TEMP_ALERT#

1

THERMD_N

C193 1000P25VX7RC1K N/A R166 1 100R1J 2

D

2 /@

2

6

1 0R1J

R161 100R1J N/A

R162 1 100R1J 2 N/A

THERMD_P

1

THERMD_P

1

6

Unmount

2

VCORE_TEMP

D

1

R158 1 0R2J N/A

+3VSUS

2

3.3V

Note: 1. VDD power supply range is +1.8V to +3.6V. 2. VIO max. voltage is VDD. 3. VOH=0.9xVIO & VOL=0.3xVIO. 4. VIH=0.8xVIO & VIL=0.2xVIO

Note: 1. DVDD power supply range is +1.7V to +2.8V. 2. AVDD power supply range is +2.4V to +3.6V. 3. Let VREG & VPP NC for reference. 4. DRDY is +1.8V level out and active high.

ADDR

I2C Address

H

1Fh/read 1Eh/write

L

1Dh/read 1Ch/write

Gyro AD0 High : I2C Address 1101001b Gyro AD0 Low : I2C Address 1101000b

Title : Sensors Size C Date:

5

Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 26

of

60

5

4

3

Codec VDD 1.8V

1.8V

VDD_1V8_GEN

VDD_1V8_CDC

VDD_1V8_CDC

2

VDB_CDC

R189 1 0R2J

N/A 2

VDB_CDC

R190 1 0R2J

N/A 2

VCP_CDC

1

D

AVDD_CDC_F

L4

10Ohm/100Mhz N/A 1 2

L5

10Ohm/100Mhz N/A 1 2

R193 1 0R2J

PMU LDO5 change to camera 1.8V VDD_1V8_GEN

N/A 2

N/A 2 C208 2.2U6.3VX5RC2M N/A 2 C209 0.1U6.3VX5RC1K GND

1

VCP_CDC

1


AVDD_CDC_F

GND

0226 Codec 1.8V change to system 1.8V power VDD_1V8_GEN

1

1

AVDD_CDC_F

1 1

DACREF_CDC


D

GND VDD_1V8_DMIC

1

DACREF_CDC

1

N/A 2 C215 10U6.3VX5RC3M N/A 2 C216 0.1U6.3VX5RC1K GND

VDD_5V0_AC_BAT VPH_PWR_CHGR

VDD_SPK 1

1

VDD_SPK

L6

VPH

N/A

2

1


Unmount

DMIC

1

VDD_1V8_DMIC

80Ohm/100Mhz

VDD_1V8_DMIC

GND

1

R197 10KR1J /@

VDD_1V8_DMIC 6 5 4

DMIC_DAT_U23 DMIC_LR_U23


1

1

SPM0423HD4H-WB 04G160008210 2

R209 10KR1J N/A

N/A

Ground1Power(Vdd) Left/Right Data Ground2 Clock

1

1 2 3

DMIC_CS

2

U23

GND

2


2

1

1

Unmount 1

VDD_MIC_CDC

/@ 2 C221 1U6.3VX5RC2K N/A 2 C222 0.1U6.3VX5RC1K


Unmount

C

Codec Realtek ALC5642 VDD_1V8_CDC

CS

Drives data after

High

Rising clock edge

Falling clock edge

Low

Falling clock edge

Rising clock edge

C

High-Z after

1

Forte media: 04G160007713 KNOWLES/SPM0423HD4H-WB:04G160008210 VDD_SPK

R313 10KR1J N/A

MICBIAS1

2

1

ALC5642_CPVEE

1

N/A 2 C231 2.2U6.3VX5RC2M N/A 2 C227 2.2U6.3VX5RC2M

LOUTR LOUTL GPIO2/DMIC_SCL GPIO1/IRQ LDO1_EN

2

1

1 1


41 40 44

SCL SDA

38 39

GND R205 SPK_OUT_R- 1 0R1J

DMIC_LR CDC_IRQ# CDC_LDO1_EN_5642

CODEC_I2C_SCL CODEC_I2C_SDA


CDC_IRQ#

R211 R210

GND GND

Unmount

2 2

0R1J 0R1J

1 N/A 1 N/A


SIDE2 SIDE1

6 5

12G171030040


GND

GND SPK_OUT_R+_CON

2 N/A


GND C259 27P25VNPOC1J /@ A

0229 EMI add

HP_OUT_L

1

HP_OUT_R

1

2 C241 N/A HP_OUT_L_C 0.1U6.3VX5RC1K 2 C242 N/A HP_OUT_R_C 0.1U6.3VX5RC1K

R215 20R1F N/A

Unmount

R216 20R1F N/A

GND

Title : Codec ALC5642 C Date:

4

3

2

Engineer:


5

4 3 2 1

WTOB_CON_4P N/A

SPK_OUT_R-_CON

N/A

6,26,49,50 6,26,49,50

2

1

2


Unmount

13

DAP2_FS_5642 C243 27P25VNPOC1J /@

CON2 4 3 2 1

Unmount GND

2

2

R212 100R1J /@

LINEOUTR LINEOUTL

R202 SPK_OUT_R+ 1 0R1J

9 49 50 22

ALC5642 N/A


17 16


2

A

MONOOUTP MONOOUTN

BCLK2 LRCK2 DACDAT2 ADCDAT2

DAP_MCLK1_5642 DAP2_SCLK_5642

1 2

MCLK BCLK1 LRCK1 DACDAT1 ADCDAT1

AGND GND1 GND2 CPGND

30 29 31 32

SPK_OUT_L-_CON

1

37 36 35 33 34

13 14

B


GND

N/A

2

DAP_MCLK1_5642 DAP2_SCLK_5642 DAP2_FS_5642 DAP2_DOUT_5642 DAP2_DIN_5642

2

1

R203 R204 R206 R208 R207

R200 SPK_OUT_L- 1 0R1J

SPK_OUT_L+ SPK_OUT_LSPK_OUT_R+ SPK_OUT_R-

2

DAP_MCLK1 DAP2_SCLK DAP2_FS DAP2_DOUT DAP2_DIN

2N/A 2N/A 2N/A 2N/A 2N/A


1

MONOP MONON

GND 0R1J 0R1J 0R1J 0R1J 0R1J

Unmount

1 48 45 47

SPK_OUT_L+_CON

2

2

ALC5642_VREF1

N/A

GND

SPO_LP SPO_LN SPO_RP SPO_RN

DACREF VREF2 VREF1

28 28

1

1

10 12 11

HP_OUT_L HP_OUT_R

1

ALC5642_VREF2

HP_OUT_L HP_OUT_R

28 26 25

1

1

HPO_L HPO_R HPOFB

2

C228 N/A 2 4.7U6.3VX5RC2M C235 N/A 2 4.7U6.3VX5RC2M

13 13 13 13 13

DMIC_DAT DMIC_LR

Unmount R201 SPK_OUT_L+ 1 0R1J

1

IN1P/DMIC1_DAT IN1N/DMIC2_DAT/JD1 IN2P IN2N/JD2

2

MIC1_P MIC1_N

MIC1_P MIC1_N

5 6 7 8

DACREF_CDC

T30 DAP2

1 N/A 1 N/A

SPEAKER CONN.

C230 N/A 2.2U10VX5RC3K

1

ALC5642_CPVPP

GND DMIC_DAT

1 1 1 1 1

0R1J 0R1J

C229 N/A 2.2U10VX5RC3K 1 2

2

24 27

ALC5642_CPP2 ALC5642_CPN2 ALC5642_CPP1 ALC5642_CPN1

1

19 18 20 21

1

4

CPVPP CPVEE

B

28 28

2 2

2

MICBIAS

MICBIAS

CPP2 CPN2 CPP1 CPN1

2

AVDD MICVDD SPKVDDR SPKVDDL DCVDD DBVDD CPVDD

2

U24

GND

28

R214 R213

0229 EMI add

R198 1MR1J /@

Unmount

DMIC_DAT_U23 DMIC_LR_U23 GND

15 3 46 2 42 43 23

R199 /@

From T30

1

VCP_CDC

1

12 CDC_LDO1_EN

VDB_CDC

AVDD_CDC_F

CDC_LDO1_EN_5642

2


1

VCORE_CDC VDD_MIC_CDC 2

1 0R1J

VCORE_CDC

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 27

of

60

5

4

R217 470R1J

0229 EMI add

1 2

1 1

3

C270 220P50VNPOC2J /@

ESD

C269 220P50VNPOC2J /@

GND

GND

13

1

/@ 2 C336 1U6.3VX5RC2K /@ 2 C338 0.1U6.3VX5RC1K /@ 2 C339 0.1U6.3VX5RC1K

1

1 2

GND

GND

Change

Q5B UM6K1N N/A

R322 0R6 2 N/A

1

VDD_USB1_VBUS

VDD_USB1_VBUS_CONN

GND 0OHM 14,49 USB1_DP

3 RN1B N/A

4

1

14,49 USB1_DN

Unmount USB1_D_FN

2

GND

USB1_D_FP

90Ohm/100Mhz L11 /@ 1

2

Unmount

C


ESD

Also connect to SMB347

C253 0.1U6.3VX5RC1K /@

2

HPOUTR2_CONN


1

2 N/A 1

R236 1 0R2J

4

5

HPOUTR2

VDD_USB1_VBUS

R6712 100K -> 330K

HOOK_DET#

HOOK_DET

HPOUTL2_CONN

1201

R221 330KR1J N/A

Change

GND

2

williams 0607

GND

GND 2 N/A

2

C249, C250, C269, C270 change to 07019-00010000

VDD_1V8_GEN

GND

GND R235 1 0R2J

Unmount

D

ESD

HPOUTL2 MIC1P_R



3

2

R220 100KR1J N/A 2

2


N/A 2 10Ohm/100Mhz

C271 220P50VNPOC2J /@

4

L29 2MIC1P_R_LRC 1

1

MIC1_P 1

27

GND

0 ohm -> 68 ohms


1

R219 1 68R1J N/A

C279 220P50VNPOC2J /@

ESD

1

MIC1_N

R6775

MIC1P_R_CONN

2

C246 0.1U10VX5RC2K MIC1P_RR 1 2 N/A

1

27

1213

1213

1uF -> 0.1uF

2 N/A

Unmount

C251, C252, C271, C279 change to 07019-00010000

PR 0214 support iphone headphone

HP_DET#_CONN

R260 1 0R2J

2

D

2 N/A

MIC1P_R 1

GND

2

GND

R258 1 0R2J

1

EP101/0318 Add Cap.

HP_DET#

2

C245 10U6.3VX5RC3M N/A

2

2

2

1 1

C244 4.7U6.3VX5RC2M N/A R218 1KR1J N/A

C6701

1

Mic & Headphone Conn.

MIC1BIAS_IO

1 N/A

2

1

MICBIAS

MICBIAS

2

22pin FFC Connector

External. Microphone 27

3

C

0OHM GND

1 RN1A N/A

2

Also connect to SMB347 USB1_ID_CON

2 N/A

R6707 100K -> 330K

1

C254 0.1U6.3VX5RC1K N/A

R222 100KR1J /@

USB1_ID_CON 1

N/A 2 C255 220P50VNPOC2J

Change

2

EXT. Headphone

1201

R233 1 0R2J

USB1_ID

USB1_ID

EP101 PR 0213

1

R223 330KR1J 1 N/A 2

2

14 VDD_1V8_GEN

10Ohm/100Mhz

27 HP_OUT_R

HP_OUTR_R

1

N/A 2 L10 22U6.3VX5RC5M

2

2

GND

GND

VDD_USB1_VBUS

ESD

USB1_D_FN HPOUTR2_CONN HPOUTL2_CONN MIC1P_R_CONN

Unmount

Unmount

D2 IP4223-CZ6 /@

USB1_ID_CON

VDD_USB1_VBUS_CONN USB1_D_FP USB1_D_FN

GND 1

B

2

1KR1J R231

HPOUTR2 N/A

1

1

1

2

UART_DEBUG_RXD

TF201X add UART through Phone Jack 0930

1 3

2 N/A HPOUTL2 VI/O

R230 1 1KR1J

GND

12,24 UART_DEBUG_RXD

UART_DEBUG_TXD

VI/O

12,24 UART_DEBUG_TXD

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

HP_DET#_CONN HPOUTR2

C257 220P25VX7RC1K N/A

VI/O

C256 220P25VX7RC1K N/A

R229 330R1J /@

2 N/A HPOUTR2

VBUS

R228 330R1J /@

2 N/A HPOUTL2

R227 HPOUTR2_R 1 33R1J

VI/O

EP101 PR 0217D

R225 1 33R1J

HPOUTL2_R

1

N/A 2 L9 22U6.3VX5RC5M

2

1

1

HP_OUTR_L

N/A 2

EP101 PR 0215B RF request

2

N/A 2

R226 1 0R1J

1

R224 1 0R1J

1

27 HP_OUT_L

ESD C255 change to 07019-00010000

HP_DET#

2

6

1

5

13 HEAD_DET#

L8 N/A

4

HEAD_DET#

HPOUTL2

1

USB1_D_FP

1

GND

/@ 2 C337 1U6.3VX5RC2K /@ 2 C331 1U6.3VX5RC2K /@ 2 C332 1U6.3VX5RC2K /@ 2 C334 0.1U6.3VX5RC1K C335 /@ 2 0.1U6.3VX5RC1K

VDD_1V8_GEN

VDD_USB1_VBUS_CONN

1

1

2

R308 1KR1J N/A 5

HPOUTL2_SPRING

GND

HPOUTR2

R311 1 0R1J

N/A 2

HPOUTR2_SPRING

2

GND

GND

GND

1

1

1

C327 220P50VNPOC2J N/A 07019-00010000

C326 220P50VNPOC2J N/A 07019-00010000

ESD

2

2

GND

07019-00010000

C319 220P50VNPOC2J /@ 07019-00010000

2

2

2

1

ESD 220P50VNPOC2J/@

DOCK_5V 1

DOCK_5V_SPRING

2

Unmount

1

2

N/A 2

R257 10KR1J N/A

6

GND

DOCK_5V_SPRING R263 1 0R1J

C320

2

N/A 2 C328 220P50VNPOC2J

ESD 07019-00010000

Change

HPOUTL2_SPRING

1

HPOUTR2_SPRING

1

C321 10U6.3VX5RC3M /@ 11G233210625310

1

U51 EMI_SPRING_PAD N/A

1


1


1


A

1

Unmount GND GND

HPOUTR2

1

Q12A UM6K1N N/A

1

DOCK_5V_SPRING

HPOUTL2

VDD_1V8_GEN

13 LINOUT_DET

R321 0R6 2 N/A

0229 EMI add

1

1

GND

R256 330KR1J N/A

A

1

DOCK_5V

1 1

VDD_1V8_GEN

C284 0.1U6.3VX5RC1K N/A

R309 1MR1J N/A

2

GND

0229 EMI & Safety add DOCK_5V

2

DOCK_5V_IN

4

Q12B UM6K1N N/A

C319, C320, C326, C327, C328 change to 07019-00010000

GND

Title : Audio/USB Conn. Engineer:


23

Change

4pin Docking Connector

DOCK_IN#

DOCK_IN#

B

DOCK_5V

3

12

24

CON1 FPC_CON_22P 12018-00360200 N/A

GND

R293 330KR1J N/A

To Tegra3 GPIO_PU5

22 21 SIDE2 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SIDE1 1

4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 28

of

60

5

4

VDD_5V0_SYS

VDD_AC_BAT

Vin=5V

3

2

1

For once 5V boost unused

VCC_TCH

L12 120Ohm /@ 1 2

VCC_TCH

+3VSUS

to 5V boost enable

L14 120Ohm /@ 1 2

VCC_TCH

L15 120Ohm N/A 1 2

VCC_TCH

EN_5V0_SBY

7,48 TS_WAKEUP#

Connectivity refer to Touch sensor spec I/O

7,48

J2 TOUCH_Y30 TOUCH_Y32 TOUCH_Y34

2

TP_3V3

S-1167B31-I6T2G N/A 06G029075018

2

C262 0.1U6.3VX5RC1K /@

1 2 3

GND_TP

EN, High>1.5V

GND_TP

C263 1U6.3VX5RC2K N/A GND_TP

C264 0.1U6.3VX5RC1K N/A

GND_TP GND_TP

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

TOUCH_Y31 TOUCH_Y33

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

TOUCH_X2 TOUCH_X4 TOUCH_X6 TOUCH_X8 TOUCH_X10 TOUCH_X12 TOUCH_X14 TOUCH_X16 TOUCH_X18 TOUCH_X20

D

GND_TP

0610

修修修12018-00110000

FPC_CON_31P 12018-00110000 N/A

Vout=3.1V , Iout=150mA

EN, Low<0.25V

Unmount

P_+3V3_VO_20 1

TP_+3V_EN

2

VIN VOUT VSS2 VSS1 ON/OFF NC

2

6 5 4

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

TOUCH_X1 TOUCH_X3 TOUCH_X5 TOUCH_X7 GND_TP TOUCH_X9 TOUCH_X11 TOUCH_X13 TOUCH_X15 TOUCH_X17 TOUCH_X19 TOUCH_X21 EKTF3624_TDO

U30

GND_TP

1

R310 1 0R1J /@

7,48 TS_WAKEUP#

GND_TP

1

Unmount

3V_Power_Supply for Touch

C260 0.1U6.3VX5RC1K N/A

2

2

D

C261 1U6.3VX5RC2K N/A 2

R232 100KR1J N/A

1

1

1

P_+3V3_VIN_20

FPC1

From 5V boost Circuit

GND

R239 N/A 1 10KR1J 2

1

1 R241 0R1J

TS_IRQ#

R247 1 0R1J 1 0R1J R248

7 GEN2_I2C_SDA 7 GEN2_I2C_SCL

C

2

R244 1 0R1J

TP_RESET#

1 R242 2 N/A 10KR1J

2 N/A

TP_INT#

2 N/A 2 N/A

TP_SDA TP_SCL

TP_3V3 TP_RESET#_R TP_SDA

N/A

1 2.2KR1J 2 R243

TP_SCL

N/A

1 2.2KR1J 2 R245

TP_INT#

N/A

1 1MR1J

2 R246

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

TOUCH_Y2 TOUCH_Y4 TOUCH_Y6 TOUCH_Y8 TOUCH_Y10 TOUCH_Y12 TOUCH_Y14 TOUCH_Y16 TOUCH_Y18 TOUCH_Y20 TOUCH_Y22 TOUCH_Y24 TOUCH_Y26 TOUCH_Y28

GND

FPC_CON_31P 12018-00110000 N/A

TOUCH_Y24 TOUCH_Y23 TOUCH_Y22 TOUCH_Y21 TOUCH_Y20 TOUCH_Y19

EKTF3624_U_AVDD EKTF3624_U_V1P8

TOUCH_Y25 TOUCH_Y26 TOUCH_Y27 TOUCH_Y28 TOUCH_Y29 TOUCH_Y30 TOUCH_Y31 TOUCH_Y32


TP_3V3

1

7

N/A

Unmount


1

Unmount

TOUCH_X1 TOUCH_X2 TOUCH_X3 TOUCH_X4 TOUCH_X5 TOUCH_X6 TOUCH_X7

TP_3V3

GND_TP

GND_TP 50 49 48 47 46 45 44 43 42 41 40 39 38 37

GND_TP

C

GND_TP

N/A 2 C267 0.1U6.3VX5RC1K /@ 2 C268 0.1U6.3VX5RC1K

58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43

GND_TP

1

2

7 TS_RESET#_3V3

0R1J R238 N/A

1

Reset Interrupt

R240 0R1J /@

3624_RESET#_1036

2

2

2

R237 1MR1J N/A

2

Touch interface

TOUCH_SENSOR_CONFIG TOUCH_Y1 TOUCH_Y3 TOUCH_Y5 TOUCH_Y7 TOUCH_Y9 TOUCH_Y11 TOUCH_Y13 TOUCH_Y15 TOUCH_Y17 TOUCH_Y19 TOUCH_Y21 TOUCH_Y23 TOUCH_Y25 TOUCH_Y27 TOUCH_Y29

RESET#_1036 1

1

TP_3V3

FPC2

J3

GND_TP

GND

T9 /@ TPC26B TP_3V3

GND_TP EKTH1036_VCI

R252 2 0R1J

TP_3V3 1 N/A

1

N/A 2 C272 1U25VX5RC3K N/A 2 C275 1U25VX5RC3K


U26 EKTFQ3624-AS003BW N/A TOUCH_SPI_CS TOUCH_SPI_SCK TOUCH_SPI_MOSI TOUCH_SPI_MISO

R250 N/A TOUCH_SENSOR_CONFIG 1 100KR1J 2 1

2

EKTH1036_VOUT 1

EKTF3624_TDO

2 R251 100KR1J /@

GND_TP

Unmount

GND2 GND1 VCC3IO VCC3K VCC DAVCC/AVCC2 DAGND/AGND2 TP24 TP23 TP22 TP21 TP20 TP19 TP18

GND/JTAG_SEL/GNDIO CLKI/PA6 CLKO/PA7 SPI_CS/PA0 SPI_SCK/SCL/PA1 SPI_SDI/SDA/PA2 SPI_SDO/PA3 RESETB SCL/PA4 EXT_SYNC/PA8 EXTINT0/PA9 EXTINT1/PA10

R249 1 10KR1J 2 N/A

TP_3V3

EKTH1036_VH

1 2 3 4 5 6 7 8 9 10 11 12

EKTF3624

EKTF3624_TDO EKTF3624_UM_AVDD

T8 /@ TPC26B

TOUCH_M_CLK 1EKTF3624_JTAG_TMS TP_SCL TP_SDA 1EKTF3624_JTAG_TDO TP_RESET#_R TP_INT# TOUCH_EXT_SYNC 3624_RESET#_1036 TOUCH_SENSOR_CONFIG

SPI2_CS/PA11 SPI2_SCK/PA12 SPI2_SDI/PA13 SPI2_SDO/PA14 TDO/PB0 DAVCC/AVCC1 DAGND/AGND1 TP1 TP2 TP3 TP4 TP5

GND_TP TOUCH_TX_DRIVE TOUCH_EXT_SYNC TOUCH_SPI_MISO TOUCH_SPI_MOSI TOUCH_SPI_SCK TOUCH_SPI_CS RESET#_1036 TOUCH_M_CLK

1

TOUCH_Y4 TOUCH_Y3 TOUCH_Y2 TOUCH_Y1

EKTH1036

TOUCH_Y33 TOUCH_Y34

42 41 40 39 38 37 36 35 34 33 32 31 30 29

TP3 TP2 TP1 TP0 TX_DRIVE EXT_SYNC SPI_SDO SPI_SDI SPI_SCK SPI_CS RESETB CLKI VCCIO VCC3K

0224 change GND_TP to GND TP17 TP16 TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6

36 35 34 33 32 31 30 29 28 27 26 25

TOUCH_X8 TOUCH_X9 TOUCH_X10 TOUCH_X11 TOUCH_X12 TOUCH_X13 TOUCH_X14 TOUCH_X15 TOUCH_X16 TOUCH_X17 TOUCH_X18 TOUCH_X19 B

13 14 15 16 17 18 19 20 21 22 23 24

U25 EKTH1036BW N/A

TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31

TP32 TP33 TP34 TP35 VH VOUT C4P C3P C1N C1P C2P C2N VCI/AVDD AGND/VSS/GND

B

1 2 3 4 5 6 7 8 9 10 11 12 13 14

15 16 17 18 19 20 EKTH1036_C4P 21 EKTH1036_C3P 22 EKTH1036_C1N 23 EKTH1036_C1P 24 EKTH1036_C2P 25 EKTH1036_C2N 26 27 28

TOUCH_Y18 TOUCH_Y17 TOUCH_Y16 TOUCH_Y15 TOUCH_Y14 TOUCH_Y13 TOUCH_Y12 TOUCH_Y11 TOUCH_Y10 TOUCH_Y9 TOUCH_Y8 TOUCH_Y7 TOUCH_Y6 TOUCH_Y5

GND2 GND1 TP17 TP16 TP15 TP14 TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4

GND_TP

TOUCH_X20 TOUCH_X21

TOUCH_TX_DRIVE

1

N/A 2 C274 4.7U6.3VX5RC2M GND_TP

GND_TP GND_TP

1 2 1 GND_TP

A

EKTH1036_VOUT

R253 1 0R1J /@ R254 1 0R1J /@

2

1

2

EKTH1036_C1N C281 N/A 1U25VX5RC3K EKTH1036_C3P A

EKTH1036_C2P

2

Power & Charge Pump R255 1 0R1J /@

C285 N/A 1U10VX5RC2K

1

1

EKTH1036_C1P

N/A 2 C276 1U6.3VX5RC2K N/A 2 C277 0.1U6.3VX5RC1K N/A 2 C278 0.1U6.3VX5RC1K /@ 2 C280 0.1U6.3VX5RC1K

2

1

1

1

2

TP_3V3

2

C282 N/A 1U10VX5RC2K EKTH1036_C2N C283 N/A 1U25VX5RC3K

Title : Touch Sensor, Conn.

EKTH1036_C4P

Size C Date:

5

Engineer:


Unmount

4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 29

of

60

5

4

3

2

1

D

D

C

C

VDD_CELL_LCL

BAT_COINCELL 50

2

1

0804 C316 10U6.3VX5RC3M N/A

B

B

A

A

Title :Coin Cell ASUSTeK COMPUTER INC. EPAD Size B

Project Name

4

3

2

Richard Lin Rev

ME370T

Date: Tuesday, March 20, 2012 5

Engineer:

Sheet 1

2.0 30

of

60

4

Camera VDDIO 1.8V

3

2

Camera AVDD

Camera VCM Power

VDDIO_CAM

VDD_5V0_AC_BAT

VDD_5V0_AC_BAT

VPH_PWR_CHGR

AVDD_CAM1

0226 VDDIO_CAM change to PMU LDO5

1

1 2 3

D

S-1132B28-I6T2G /@

R262 1MR1J N/A

C399 1U6.3VX5RC2K /@

2

2

C398 1U6.3VX5RC2K /@


2

1


2 1

6 5 4

VCM_AVDD_EN

6 CAM2_LDO_EN

S-1132B28-I6T2G N/A

R261 1MR1J N/A

2


1 2 3

1

CAM1_AVDD_EN 1

6 CAM1_LDO_EN

Delete Q13, Q14, R258, R260, R263, C279 Change R259 from 1M -> 0ohm

VDDIO_CAM

AVDD_VCM U28


1

D

VPH_PWR_CHGR

U27 6 5 4

1

VDD_PMU_LDO5

N/A 2

2

R259 1 0R2J

MAX77663 LDO5

1

1

5

1201

1201

R3427 100K -> 1M

R3428 100K -> 1M


MIPI

5M Camera (Rear)

9 PWDN_5M 9 CAM_RST_5M

AVDD_VCM 9 9

CSI_CLKAP CSI_CLKAN

9 9

CSI_D1AN CSI_D1AP

9 9 9,25,26,44 9,25,26,44

CSI_D2AN CSI_D2AP

CSI_CLKAP CSI_CLKAN

CSI_CLKAP_R CSI_CLKAN_R

CSI_D1AN CSI_D1AP

CSI_D1AN_R CSI_D1AP_R

CSI_D2AN CSI_D2AP

CSI_D2AN_R CSI_D2AP_R CAM_I2C_SCL_5R CAM_I2C_SDA_5R


AVDD_CAM1 AVDD_CAM1 VDDIO_CAM 23 24

25 J4 9

N/A R265 1 15R1J

CAM_MCLK

CAM_MCLK_R_1M2

2

1 3 5 7 9 11 13 15 17 19

Unmount 9 9

C290 10P50VNPOC1J /@ CSI_CLKBP CSI_CLKBN

CSI_CLKBP CSI_CLKBN

26

1 3 5 7 9 11 13 15 17 19

SIDE3 SIDE4

AVDD_CAM1 PWDN_5M_R CAM_RST_5M_R

1 2 3 4 SIDE1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SIDE2 20 21 22 23 24 CON3 /@

SIDE1 SIDE2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

VDDIO_CAM

PWDN_2M 2 4 6 8 10 12 14 16 18 20

2 4 6 8 10 12 14 16 18 20

J4 2nd source PANASONIC/AXT520124 12G161H0020A

2

9 9

PWDN_2M

N/A 1 1MR1J

B

2

R266

C294 0.1U6.3VX5RC1K /@

1

1

1 C293 0.1U6.3VX5RC1K /@

2

C296 0.1U6.3VX5RC1K /@

2

C292 0.1U6.3VX5RC1K /@

2

2

R269

C291 0.1U6.3VX5RC1K /@

CSI_CLKAP CSI_CLKAN 1

CAM_I2C_SCL CAM_I2C_SDA 1

CSI_CLKBP CSI_CLKBN

2

CAM_RST_5M_R

CSI_D1BP CSI_D1BN

GND GND

N/A 1 1MR1J

CAM_RST_2M 12 CAM_I2C_SCL 9,25,26,44 CAM_I2C_SDA 9,25,26,44

R267

2

2

1

N/A 1 1MR1J

9

12016-00100000 BTOB_CON_20P N/A

B

PWDN_5M_R

PWDN_2M_R CAM_RST_2M_R

21 22

Unmount


1

CAM_MCLK_R_5M


2

2

Unmount

2

1

/@ R264 1 15R1J

CAM_MCLK 1

9

C

1.2M Camera (Front) 12018-00050000 FPC_CON_24P

2

C

CAM_RST_2M C295 0.1U6.3VX5RC1K /@

N/A 1 1MR1J

2

R268

GND

Unmount GND

Unmount

C301 0.1U6.3VX5RC1K /@

1

1

1 C300 0.1U6.3VX5RC1K /@

2

C299 0.1U6.3VX5RC1K /@

2

C298 0.1U6.3VX5RC1K /@

2

1

CSI_D1BP CSI_D1BN

2

2

2

C297 0.1U6.3VX5RC1K /@

1

CSI_D1AN CSI_D1AP 1

CSI_D2AN CSI_D2AP

C302 0.1U6.3VX5RC1K /@

RF Requst

A

A



4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 31

of

60

5

4

3

2

1

HOT_RST# inverse for PMIC VDD_5V0_AC_BAT

Reset Button

MAX77663 SD2 (2A) VDD_1V8_PMU_DCDC2

VPH_PWR_CHGR

VDD_1V8_GEN

HOT_RST_R1

3

1

1

PMU internal PD 200~400k

R279 330KR1J N/A

HOT_RST

D

SYS_RESET#

6,20,50

5

Q8B UM6K1N N/A

C304 1000P25VX7RC1K N/A

R271 100KR1J N/A 2

2

2

C305 1U6.3VX5RC2K /@

1

D4 N/A BAT54CW 2

1

3 D

SYS_RESET# to MAX77663 nRSTIO & T30 SYS_RESETn R312 N/A 1 0R1J 2

SYS_RESET#_SOURCE

2

G

N/A 2

1

RST_SW#

R277 1 0R1J

R278 4.7KR1J N/A 2

11

HOT_RST#

Q15 SI2305DS N/A

3

24

S

1

2

2

3

2

R276 10KR1J N/A D

4

1


Unmount

PWRON Key long press RESET for PMIC VDD_5V0_AC_BAT

FORCE_RECOVERY#

VPH_PWR_CHGR 1

+3VSUS 1

PWR_SW#_RESET_DELAY 11

G

3

3 D

CW:T30 pull high 50~100K internally. R305 330KR1J N/A

5 4

6 VOL_UP_BUTTON

2


18,24

6

2

TF201 0901 modify

Q F_RECOVERY#

R275 N/A 1 2 0R1J

FORCE_R_Q1

HOT_RST_R2

1

Q16B UM6K1N N/A

Q23 SI2305DS N/A

FORCE_R_Q2

Q17B UM6K1N N/A

2 1

3

C

S

1

4

2

2

2

PWR_SW#

R274 100KR1J N/A

2

R272 100KR1J N/A

2

VPH_PWR_CHGR

1


R273 100KR1J /@

1

VPH_PWR_CHGR

PWR_SW#_DELAY_RC2

Unmount

VDD_5V0_AC_BAT

3

PWR_SW#

VDD_5V0_AC_BAT

5

2

2

1

2

Q16A N/A UM6K1N 1 6

33

VDD_1V8_GEN R270 10MR1J N/A

Q17A UM6K1N N/A

C

C333 2.2U6.3VX5RC2M /@ GND

GND

Unmount

GND

VOL_UP H = 1.8V L = 0V

A

B

Q

0

0

0

0

1

1

1

0

1

1

1

1

B

B

8pin Button Connector CON4 N/A FPC_CON_8P 33 PWR_SW#_CTL 33 PWR_SW#_BUTTON

PWR_SW#_CTL

R314 1 0R1J

2 N/A

PWR_SW#_CTL_CONN

PWR_SW#_BUTTON

R315 1 0R1J

2 N/A

PWR_SW#_BUTTON_CONN

VOL_DWN_BUTTON VOL_UP_BUTTON KB_ROW0

R297 1 0R1J R286 1 0R1J R280 1 0R1J

2 N/A 2 N/A 2 N/A

VOL_DWN_BUTTON_R VOL_UP_BUTTON_R KB_ROW0_SW

T10 T11 T12 T14 T13 T17

1 1 1 1 1 1

PWR_SW#_CTL_CONN PWR_SW#_BUTTON_CONN VOL_DWN_BUTTON_R KB_ROW0_SW VOL_UP_BUTTON_R RST_SW#_BUTTON

8 7 6 5 4 3 2 1

1

6 VOL_DWN_BUTTON 6 VOL_UP_BUTTON 6,33 KB_ROW0

/@ /@ /@ /@ /@ /@

SIDE2

SIDE1

10

9

12018-00210800

2


8 7 6 5 4 3 2 1

Unmount

Change

RST SW

Unmount

2 N/A

PWR_SW#_CTL_CONN

1

PWR_SW#_BUTTON_CONN

1

VOL_UP_BUTTON_R

1

VOL_DWN_BUTTON_R

1

KB_ROW0_SW

1

RST_SW#_BUTTON

1

PWR_SW#_CTL

2

1

PWR_SW#_BUTTON

1

A

R304 1 0R1J

2

2

1

VOL_DWN_BUTTON

2

RST_SW# /@ C324 220P50VNPOC2J 07019-00010000 /@ C323 220P50VNPOC2J 07019-00010000 /@ C325 220P50VNPOC2J 07019-00010000 /@ C329 220P50VNPOC2J 07019-00010000 /@ C322 07019-00010000 220P50VNPOC2J /@ C330 07019-00010000 220P50VNPOC2J

2

1

VOL_UP_BUTTON

2

1

KB_ROW0

2

1

RST_SW#

Change C309 220P50VNPOC2J N/A 07019-00010000

GND

ESD C309 change to 07019-00010000

ESD change to 07019-00010000

N/A 2 C307 220P50VNPOC2J 07019-00010000 N/A 2 C308 220P50VNPOC2J 07019-00010000 N/A 2 C310 220P50VNPOC2J 07019-00010000 N/A 2 C311 220P50VNPOC2J 07019-00010000 N/A 2 C312 07019-00010000 220P50VNPOC2J A

Change

ESD C307, C308, C310, C311, C312 change to 07019-00010000

Title : Buttons /Conn. Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 32

of

60

5

4

3

2

1

ACOK#_PMIC to MAX77663 ACOK, check Polarity(active Low) on PMU side

VDD_5V0_AC_BAT

1

VPH_PWR_CHGR

2

PWR_SW#

32

11

2

1230 EMC add

C314 0.1U6.3VX5RC1K /@

3

3 D ONKEY_R1 R295 10KR1J N/A

GND 2

Unmount

R283 10KR1J N/A Q20 SI2305DS N/A

4

Q18B UM6K1N N/A PMU_ONKEY#

1 VPH_PWR_CHGR

2

1

12

ONKEY_R2

2

D


2

Signal to MAX77663

50

4

5

PMU_ONKEY#

PMU_ONKEY# to MAX77663 EN0, check Polarity on PMU side

Q21B UM6K1N N/A

Q22A UM6K1N N/A

1

VDD_5V0_AC_BAT

2

2

2MR1J R288 N/A

1

C

AP_ONKEY#

5

VPH_PWR_CHGR

ONKEY_PMIC

6

PWR_SW#_DELAY

1

3

3

R289 220KR1J N/A

R290 100KR1J N/A 2

PWR_SW#

AP_ONKEY# Q21A UM6K1N N/A

BAT_LOW#

VDD_5V0_AC_BAT

Q22B UM6K1N N/A 4

R287 N/A 1KR1J 1 2

1

1

R285 1MR1J N/A

G

S

2

2

6

PWR_SW#_CTL

R282 1MR1J N/A

32

2

1

C313 0.1U6.3VX5RC1K N/A

PWR_SW#_CTL_0ohm

3

PWR_SW#

PWR_SW#_BUTTON

PWR_SW#_CTL

5

2

2

R284 0R1J N/A

32

1

2 PWR_SW#_BUTTON

1

2

Tegra KB ROW0 D

VDD_1V8_GEN

PR 0217

1

KB_ROW0

Q19B N/A UM6K1N 4 3

5

6,32

Q19A N/A UM6K1N 6 1 KB_ROW0_NMOS

VPH_PWR_CHGR

DAU BD PWR_SW# BUTTON

1

R281 10KR1J N/A

Tegra KB COL0

VDD_5V0_AC_BAT

PWRBTN Logic

Page 32

1

6 PWR_SW#_BUTTON_R

2

Power Button

PWR_SW#_DELAY_RC1

6 1

Q18A UM6K1N N/A

C

2

C315 2.2U6.3VX5RC2M N/A

Charger Related Signals VDD_5V0_AC_BAT

1

VPH_PWR_CHGR

R299 N/A 1 10KR1J 2 RESET_IC

Signal to MAX77663 2

ACOK#_PMIC

ACOK#_PMIC

1 2

C318 10U6.3VX5RC3M N/A

U29 4 3

VDD NC

OUT VSS

BAT_LOW#_R

1 2

S-1000N34-I4T1G N/A

2 2

11

G

S

Q27 SI2305DS N/A

3 D

R301 LL_BAT_R 1 1KR1J

N/A 2 LL_BAT_T30

LL_BAT_T30

6 B

50

1 12 AP_CHARGING#

BAT_LOW#


R294 10KR1J N/A

Signal from SMB347 2

AP_CHARGING#

N/A 2

R302 100KR1J N/A

VDD_1V8_GEN

To Tegra3

R300 1 0R1J

2

ACOK#_PMIC_R

R303 1 0R1J N/A

C317 0.1U6.3VX5RC1K N/A

1

VBATT

3

RB520CS 2nd Source 07004-00030200 - SCHOTTKY BAT54TM SOD923 07G004045223 SCHOTTKY RB520CS-30 VMN2 [GA] ROHM 07G004250110 SCHOTTKY RB520G-30 SOD723 [GA] PANJIT

R296 100KR1J N/A

3% Battry capacity : 3.4V

VBATT

49

1

SMB347_ACOK#

Charger OD output (INOK/SYSOK, SMB347 E2 pin) PU 1M (VPH_PWR) on charger page(p.49) preset to ACtive Low L --> AC/USB IN

VDD_1V8_GEN

1

Signal from SMB347

2

R291 1MR1J N/A

2

B

AP_ACOK#

AP_ACOK#

D6 RB520CS_30 1 2 N/A

2

To Tegra3 12

2

R298 10KR1J N/A

VDD_5V0_AC_BAT

Battery Voltage Low Detection

VPH_PWR_CHGR

1

VDD_1V8_GEN

1 0R1J N/A

2 R292

SMB347_STAT 49

Charger OD output (STAT, SMB347 F5 pin) PU 1M (VPH_PWR) on charger page(p.49) preset to ACtive Low L --> charging H --> other status

A

A

From Tegra3

6 SMB347_USB51HC

1 0R1J N/A

2 R306

6 SMB347_SUSP

1 0R1J N/A

2 R307

SMB347_USB51HC_CHGR

SMB347_SUSP_CHGR

49

49

Signal to SMB347

ROW10, 11 for charger control

Title : T30 Core & Fuse Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 33

of

60

5

4

3

2

1

Unmount CLIP1 1 2 3 4 5

CLIP2 1 2 3 4 5

GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@

CLIP3 1 2 3 4 5


D

SHIELDING_5P 13GOK0310M100-10 /@

CLIP9 CLIP8 1 2 3 4 5

1 2 3 4 5

GND1 GND2 GND3 GND4 GND5


CLIP5 1 2 3 4 5

CLIP6 1 2 3 4 5


CLIP7 1 2 3 4 5


GND1 GND2 GND3 GND4 GND5 SHIELDING_5P 13GOK0310M100-10 /@ D

CLIP10 1 2 3 4 5



CLIP4 1 2 3 4 5



Unmount CLIP11

PTH

NPTH

H1 /@ 1 C138D75

H5 /@ 1 C138D75

H2

/@ 1 C138D75

H3

/@ 1 C59D59N

/@ 1 C138D75

H4

H11 /@ 1 C59D59N

H8

/@ 1 C138D75

CLIP13 1 2 3 4 5



H10

H7

/@ 1 C138D75

GND

/@ 1 C59D59N

H6

/@ 1 C138D75

C

H9

1 2 3 4 5

/@ 1 C138D75

H12 /@ 1 C43D43N

CLIP12 1 2 3 4 5

CLIP14 1 2 3 4 5



C


GND

U61 1

N/A

1 EMI_SPRING_PAD U62

1

N/A

1 EMI_SPRING_PAD

GND

B

B

A

A

Title : EMC, Screw hole Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 39

of

60

5

4

3

2

VDD_1V8_GEN

R4018 47KR1J /@

CW/0318 Add EMI Cap.

2

SDIO_CLK_SPI_CLK

2 R4002

SDIO_CMD_SPI_DI

SDIO_CMD_SPI_DI

15 SDMMC3_DAT0

SDMMC3_DAT0

1 0R1J

2 R4003

SDIO_DATA0_SPI_DO

SDIO_DATA0_SPI_DO

15 SDMMC3_DAT1

SDMMC3_DAT1

1 0R1J

2 R4004

SDIO_DATA1_SPI_IRQ

SDIO_DATA1_SPI_IRQ

15 SDMMC3_DAT2

SDMMC3_DAT2

1 0R1J

2 R4005

SDIO_DATA2_SPI_NC

SDIO_DATA2_SPI_NC

41

15 SDMMC3_DAT3

SDMMC3_DAT3

1 0R1J

2 R4006

SDIO_DATA3_SPI_CS

SDIO_DATA3_SPI_CS

41

2

41

12,41 WLAN_MAC_WAKEN

WF_RST#

WL_SHUTDOWN_N_RST_N

WLAN_MAC_WAKEN

WL_HOST_WAKE

WL_HOST_WAKE

1 2

SDIO_DATA1_SPI_IRQ C4008 100PF5VNPOC1J /@

1

D

C4011 100PF5VNPOC1J /@

SDIO_DATA3_SPI_CS



15,41

12,41

CW/0322 Add EMI VARISTOR.

6,41,43


WL_EN 1

1 2

WiFi_RTC_CLK

SDIO_CMD_SPI_DI

41

WL_SHUTDOWN_N_RST_N

CLK_32K_OUT

6,41,43 CLK_32K_OUT

41

2

1 0R1J

15,41 WF_RST#

SDIO_DATA2_SPI_NC C4009 100PF5VNPOC1J /@

1

SDMMC3_CMD


2

15 SDMMC3_CMD

CW/0228 Follow Cardhu, change to 0ohm.

SDIO_DATA0_SPI_DO

41 1

SDIO_CLK_SPI_CLK

2

SDIO_CLK_SPI_CLK

2 R4001

1

1 0R1J D

1

R4017 47KR1J /@ 2

Unmount

1

1

1 R4016 47KR1J /@ 2

R4015 47KR1J /@ 2

R4014 47KR1J /@ 2

R4013 47KR1J /@

1

1

1

2


R4012 47KR1J /@

2

1 2

Unmount

R4011 47KR1J /@

2

SDMMC3_CLK

1

1

Unmount

2

WIFI SDIO 15 SDMMC3_CLK

1

D4003 TVL040201AB0 /@

Unmount WL_EN

15,41

2

15,41 WIFI_EN C

C

remove FM

BT

0502

12,41 BT_UART3_RXD

BT_UART_TXD

12,41

12,41 BT_UART3_TXD

BT_UART_RXD

12,41

12,41 BT_UART3_RTS#

BT_UART_CTS_N

12,41

12,41 BT_UART3_CTS#

BT_UART_RTS_N

12,41

BT_RST_N

1

1MR1J R4089

2

BT_WAKE

CW/0322 Add PD

1

1MR1J R4090

remove FM audio interface,

1201 R4089 & R4090 100K -> 1M

GND 2

GND B

B

BT_WAKE

12,41 BT_WAKEUP

BT_WAKE

BT_HOST_WAKE

12,41 BT_IRQ#

BT_HOST_WAKE

BT_RST_N

BT_RST_N

2

1

12,41 BT_EN

12,41

BT PCM 0502

12,41

12,41


Unmount

12,41 DAP4_SCLK

BT_PCM_CLK

12,41

DAP4_FS

BT_PCM_SYNC

12,41

DAP4_DIN

12,41 DAP4_DOUT

GPS

BT_PCM_IN

12,41

BT_PCM_SYNC

12,41

BT_PCM_OUT

12,41

BT_PCM_IN

12,41

0502 GPS_nCTS

12,43 GPS_UART2_RTS#

GPS_nRTS

12,43 GPS_UART2_CTS#

GPS_TX

12,43 GPS_UART2_RXD

6,41,43 CLK_32K_OUT

1 1MR1J

12,43 12,43 12,43

GPS_RTCCLK

GPS_RTCCLK

6,41,43

GPS_POWER_ON#

GPS_POWER_ON#

2 GPS_POWER_ON#

remove proximity to 3G path control 0609

A

12,43


2 N/A

Unmount

R4091

CW/0322 Add PD

12,43

GPS_nRTS GPS_TX

1

12,43 GPS_PWRON

GPS_nCTS

GPS_RX

GPS_RX

12,43 GPS_UART2_TXD

A

BT_PCM_OUT

BT_PCM_CLK

1201 R4091 100K -> 1M

Title : RF Interface

GND

Size C Date:

5

Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 40

of

60

5

4

3

L4106

1.8V

2 N/A

1

VDD_1V8_GEN

2

1

0221 ME370T L4110 unmount R4105/R4110 0ohm

RF solution

WiFi_BT_VDDIO_1V8

Main Ant

120Ohm R4105 2.7NH/300mA 10G212000004010 2 1 N/A

0825

3.3V

D

+3VSUS

N/A 1

ANT_BT_WL_3

L4102 60Ohm/100Mhz 2 WiFi_BT_VCC_3V3

L4104 $1.3NH /@

NBS_L0603_H39_000S 10G213000003010

U7912 ANT_BT_WL_4

2

2

1

L4109 $1.3NH /@

U7913 1

D

N/A 1

EMI_SPRING_PAD 1

1

N/A

1 EMI_SPRING_PAD

L4110 0.5pF/50V 11G23200R564320 /@

Change 1

1

2

R4104 2 0R2J N/A

ANT_BT_WL_1

L4102 change to 0ohm

WiFi_BT_VCC_3V3

1

1 2

2

1

C9719 10U6.3VX5RC3M N/A

C4138 0.1U6.3VX5RC1K N/A

C4142 4.7U6.3VX5RC2M N/A

CLOSE PIN A2

C

2

C4143 0.1U6.3VX5RC1K N/A

2

1

WiFi_BT_VDDIO_1V8

U4303

C

Azurewave AW-NH665 0C011-00060000

2 C4145 N/A 0.1U6.3VX5RC1K 2 C4150 N/A 4.7U6.3VX5RC2M

1

VDD1P2_LNLDO1_OUT

Close to C2

1

Close to A3

1

Close to C1

1 1

VDD_2P5_OUT

N/A 2 C4140 4.7U6.3VX5RC2M N/A 2 C4149 0.1U6.3VX5RC1K N/A 2 C4144 0.1U6.3VX5RC1K

1

N/A 2 C4147 1U6.3VX5RC2K

1

2 C4151 N/A 0.1U6.3VX5RC1K

2 C4135 N/A 1U6.3VX5RC2K 2 C4136 N/A 4.7U6.3VX5RC2M 2 C4148 N/A 0.1U6.3VX5RC1K

Close to H2

Close to J3 VDD_1P4

1

1

SR_PA_OUT

2 C4146 N/A 0.1U6.3VX5RC1K

1

VDD1P2_LNLDO1_OUT

1

SR_PA_OUT

VDD1P2_LNLDO1_OUT

WiFi_BT_VCC_3V3 SR_PA_OUT

ANT_BT_WL_1

WiFi_BT_VDDIO_1V8

L4107 N/A 2 2.2UH Irat=1.7A

VDD_2P5_OUT

2

C4139 10U6.3VX5RC3M N/A

CBUCK_OUT

1

1

VDD_1P4

12 BT_HOST_WAKE

BT_HOST_WAKE

SR_PA_OUT VDD_1P4 VDD1P2_LNLDO1_OUT

R4133

12,40 BT_RST_N

1 0R1J N/A

2

BT_SHUTDOWN_N BT_RST_N

WL_GPIO_6 BT_WAKE

VDD1P2_LDO_OUT

1

N/A 2 C4366 4.7U6.3VX5RC2M

1

2 C4367 N/A 0.1U6.3VX5RC1K

R4132 0R1J N/A

AZWAVE/AW-NH665 0C011-00060000 N/A

VDD_WL_PA GND16 WL_UART_RX GND15 BT_PCM_OUT BT_PCM_SYNC SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK GND14 BT_UART_TXD BT_UART_CTS_N WL_HOST_WAKE BT_PCM_CLK BT_PCM_IN SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ

G9 G8 G7 G6 G5 G4 G3 G2 G1 F9 F8 F7 F6 F5 F4 F3 F2 F1

WiFi_BT_VCC_3V3 WL_UART_RX

1

T4306

/@

For Debug use only BT_PCM_OUT BT_PCM_SYNC SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK

BT_PCM_OUT 12 BT_PCM_SYNC 12 SDIO_CMD_SPI_DI SDIO_DATA2_SPI_NC SDIO_CLK_SPI_CLK 40

BT_UART_TXD BT_UART_CTS_N WL_HOST_WAKE BT_PCM_CLK BT_PCM_IN SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ

BT_UART_TXD 12 BT_UART_CTS_N 12 WL_HOST_WAKE 12 BT_PCM_CLK 12 BT_PCM_IN 12 SDIO_DATA3_SPI_CS SDIO_DATA0_SPI_DO SDIO_DATA1_SPI_IRQ

B

40 40

40 40 40

2

Close to D1 VDD1P2_LDO_OUT

GND1 VBAT_IN SR_PA_OUT GND2 ANT_FM_RX ANT_FM_TX FM_AUDIO_R FM_AUDIO_L GND3 CBUCK_OUT GND4 VOUT_2P5_OUT VOUT_2P5_IN GND5 BT_I2S_CLK BT_HOST_WAKE GND6 VDD_BT_PA VIN_LDO VDD_LN_OUT BT_SHUTDOWN_N BT_RST_N GND7 WL_GPIO_6 BT_I2S_WS BT_WAKE GND8

1

12,40 BT_WAKE

GND24 GND23 ANT_2G4 GND22 GND21 GND20 VDD_LN_IN HSIC_STROBE GND19 VDD_WL_PA_A_MODE NC2 GND18 ANT_AUX_EN GND17 ANT_MAIN_EN HSIC_DATA VDDIO_RF VDDIO

B

U4303 A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9

VDD1P2_CLDO_OUT WL_SHUTDOWN_N_RST_N RTC_CLK GND9 BT_I2S_DO WL_GPIO_5 BT_I2S_DI GND10 NC1 GND11 VDD_CORE WL_UART_TX WL_GPIO_2 GND12 WL_GPIO_1 BT_UART_RTS_N BT_UART_RXD GND13

WiFi_BT_VCC_3V3 SR_PA_OUT

D1 D2 D3 D4 D5 D6 D7 D8 D9 E1 E2 E3 E4 E5 E6 E7 E8 E9

SR_PA_OUT

Close to B9

J9 J8 J7 J6 J5 J4 J3 J2 J1 H9 H8 H7 H6 H5 H4 H3 H2 H1

Close to B3 & B4

Close to E2 15,40 WL_EN 15,40 WL_SHUTDOWN_N_RST_N A

1 0R1J

2 N/A

R4137

1 0R1J

2 /@

R4131

1 0R1J

2 N/A

VDD1P2_LDO_OUT

Unmount

WL_EN_RST_N BT_UART_RXD

BT_UART_RXD

RTC_CLK_EXT_WIFI

2

1

6,40,43 WiFi_RTC_CLK

R4136

/@ C4117 0.1U6.3VX5RC1K /@

1

WL_UART_TX

BT_UART_RTS_N

BT_UART_RTS_N

For Debug use only

12

A

12

WL_EN_RST_N 1

Unmount

T4107

R4138 1MR1J N/A

R4138 100K -> 1M

Title : Wifi/BT Combo

2

1201

Size C Date:

5

4

3

Engineer:


2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 41

of

60

5

4

3

2

02G561020900 02038-00010100

U7915

BCM4751

BCM47511

02G561020900

02038-00010100

09G061041350

09G061226010

N/A

1

GPS_BCM_IN3 2 C7919

1 1PF/25V (0201) N/A

1 2 5

/GPS

Unbalance_port1 Unbalance_port2 GND1 GND3

GND2

C7925 9.1NH 4

GPS_IN_BCM2

2GPS_IN_BCM0

1 N/A

BCM47511_VDD1P2_GRF

3

D

1

UPC8236T6N-E2-A

GPS_BCM_IN2 N/A C7917 1000PF/25V (0201)

1580MHZ 09G061041350

L4306 600Ohm/100Mhz N/A

L4308 1.8PF/50V N/A

2

U7915

7 6 5 4

1

GND2 VCC1 VCC2 GND1 OUTPUT INPUT POWER_SAVE

1

L4302 $4.7NH /@

U4301

SAW FILTER 1575.42MHZ SAW FILTER 1580MHZ

C4310 2.2U6.3VX5RC2M N/A

2

R4306 N/A 0R1J (0201)

ST Pre-LNA

C.S BCM4751IFBG FBGA100 C.S BCM47511IFBG FBGA100

1

2

0221 ME370T L4111 unmount R4316/R4317 0ohm

1

C4306 N/A 2.2U6.3VX5RC2M 2

J8 J9 K8 K10 E10

K6

H10

K7

GPS_VSSIF GPS_VSSPLL GPS_VSSLNA1 GPS_VSSLNA2 GNDIFP

VDD1p2_GRF

GPS_RFIP

GPS_VDDPLL

K9

REG_1V8

GPS_VDDIF

/GPS U4301 BCM4751IFBG GPS_IN_BCM0

J10

GPS_LNA_EN

Unmount

GPS_VDDLNA

D

09G061041350 09G061226010

2

2GPS_BCM_ANT3

1

REG_1V8

GPS_BCM_IN1

GPS_BCM_ANT1

U4302 1 2 3

1

L4303 5.6NH N/A

2

C7916 1000PF/25V N/A

2

2

1

600Ohm/100Mhz L4309 N/A 1 2

1

RF

GPS_AUXOP GPS_AUXON

J7 H8

26MHZ N/A

C4315 $0.22U6.3VX5RC2K

BCM47511_RTCCLK_R

0R1J

2 R4302 A8

N/A

Unmount

A7

R4305 N/A 1 100KR1J 2

GPS_VDD_IO_1V8

BCM47511_RST#

A5 J4

12,40 GPS_POWER_ON# U7909 1

H2 K1 B3

N/A

1

GPS_CAL TCXO LPO_IN ADCP VDDADC ADCN

CAL_REQ CLK

IF

SYS

IF

VSSADC1 VSSADC2 AUX_HI

1

6,40,41 GPS_RTCCLK

1

1

A4 G10 K2 F10 F8 G9

BCM47511_TCXO_OUT_26M /@

Unmount L4112 $1.3NH /@

6 5 4

GPS_SYNC/PPS_OUT

VDD_AUX_O VDD_AUX_IN

IF_VALID

HOST_REQ

RST_N

LNA_EN

REGPU

C_GPIO_6 C_GPIO_7

TM1 TM2 TM3

D_GPIO_5 D_GPIO_6

EMI_SPRING_PAD REF_CAP

1

N/A 1

D2 C1 N/A C7920 1000PF/50V 2 1

Ant_4 2

EMI_SPRING_PAD

10G212000004010 R4317 2.4P50VNPOC2J 2 N/A 1

L4115 $1.3NH /@

1

1

N/A

F2 F7 H3 H4 J2 G8 G7 J1

EMI_SPRING_PAD U7931

L4116 $1.3NH /@

N/A 1

1

RART/I2C

IF

SCL2/UART_TX SDA2/UART_RX UART_nRTS UART_nCTS

REG_1V8

K4 H6 H7

GPS_VDD_BAT_3V3

A6

C

GPS_LNA_EN

B6 A3 B5

GPS_VDD_IO_1V8

Unmount

A2 H1 J6

C4311 0.22U6.3VX5RC2K N/A

BCM47511_REF_CAP

C4312 1 2

N/A 0.01U10VX7RC1K

E1 D1 B2 A1

R4304 $100KR1J /@ GPS_TX GPS_RX GPS_nRTS GPS_nCTS

12 12 12 12

XA_1 XA_2 XA_3 XA_4 XA_5 XA_6 XA_7 XA_8

MEMORY

XD_0 XD_1 XD_2 XD_3 XD_4 XD_5 XD_6 XD_7

E5 B1 E6 D4 C4 E3 F6 E7

1

EMI_SPRING_PAD 1

SDA1 SCL1

H9 F9

U7930 Ant_3 2

U7908

B7

1

NC1/VCO/ENABLE/DISABLE# VCC NC2 NC3 GND OUTPUT

2

GPS_BCM_ANT1

1

1 2 3

/@

2

N/A C7918 1000PF/50V 2 1

2

2 L4111 8.2NH /@ C

Ant_2

2

10G212000004010 R4316 2.4P50VNPOC2J 2 N/A 1

Ant_1

1

X4301

G6 G4 G1 F1 G5 C10 C8 D5

Unmount B

GPS_VDD_BAT_3V3

D8 D6 D9

1

J5 BCM47511_VDD_PRE

C4308 2.2U6.3VX5RC2M N/A

1

H5 E9 G2 C7 C3

2

2

C4309 2.2U6.3VX5RC2M N/A

BCM47511_VDD1P2_CORE 1

K5 C6 D7 F3

GPS_VDD_IO_1V8

XD_8 XD_9 XD_10 XD_11 XD_12 XD_13 XD_14 XD_15

XA_17 XA_18 XA_19

XCS_N XWE_N XOE_N

VDD_BAT VDD_PRE

B

F5 E4 E2

PWR NC

VDDIFP VDDC1 VDDC2 VDDC3

AVSS1 AVSS2

VDD1p2_CORE

VSSC1 VSSC2 VSSC3 VSSC4 VSSC5

VDDIO1 VDDIO2 VDDIO3

C2 D10 B4 A9 A10 B9 C9 B10

E8 J3 K3

G3 F4 B8 C5 D3

VDD_1V8_GEN

GPS_VDD_IO_1V8 L4304 2

1

2

120Ohm

C4305 0.1U6.3VX5RC1K N/A

C4314 2.2U6.3VX5RC2M N/A

+3VSUS

GPS_VDD_BAT_3V3 GPS_VDD_RF 1

L4305 2

1 N/A

A

120Ohm 2

A

EP101 PR 0213

GPS_VDDIO 1

N/A

2

1

2

C4307 2.2U6.3VX5RC2M N/A

XA_9 XA_10 XA_11 XA_12 XA_13 XA_14 XA_15 XA_16

C4313 2.2U6.3VX5RC2M N/A

CW/0228 Check VDD_BAT & VDDIO & RST_N sequence.

Title : GPS Size C Date:

5

Engineer:


remove proximity to 3G path control 0609 4

3

2

Project Name

Richard Lin Rev

ME370T


Sheet 1

2.0 43

of

60

3

2

RX

2

VMID

2

1

1

/@ C3637 2 1

1 2

C3607 180pF/50V N/A R4453 0Ohm 1 N/A

1.8V

VDD_1V8_GEN

NFC_PVDD

1

VDD_5V0_AC_BAT

1

NFC_VBAT 1 R4412 0R2J

VPH_PWR_CHGR

1

NFC_PVDD

2 N/A

2 N/A

1

NFC_VBAT

C3616 180pF/50V N/A


PF1

NFC_IF1 NFC_SDA NFC_SCL NFC_IRQ

1

C4410 0.1U6.3VX5RC1K N/A

2

R4406 0R1J N/A

1

2

NFC_IF1

NFC_VEN

TX1 TX2 RX VMID PF1 PF2

18PF/50V N/A

A6 B6 C5 D5 E5 H2 F3 G2 G3 C6 E3 D3 C3 C2 B1 B2 B3 A1 A7 E6 H1 A2 F4 F5 H8 H5 B5 D2 H3 E2 E1 F1

U7921 feed3 1

2

1

D

N/A

Feed3

R4455 0Ohm 1 N/A

TX23

EMI_SPRING_PAD

C3638 10PF/50V /@

U7920 feed4 1

2

1

N/A

Feed4

C3634 10PF/50V N/A

EMI_SPRING_PAD

C3639 10PF/50V /@

C3642 39PF/50V 2 1 /@ C3635 39PF/50V 2 1

N/A C3636 39PF/50V 2 1 N/A C3643 39PF/50V 2 1 /@

NFC_PVDD

C

NFC_PVDD NFC_GPIO4 1

1

NFC_TVDD

C4409 1UF6.3VX5RC2K N/A

C3632 1

C3641 10PF/50V N/A

R4454 0Ohm 1 N/A

R4407 100KR1J N/A

NFC_GPIO6 2

2

2

C4408 0.1U6.3VX5RC1K N/A

1

NFC_PVDD 2

C4407 1UF6.3VX5RC2K N/A

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 RFU1 RFU2 RFU3 IFSEL0 IFSEL1 IFSEL2 TVSS2 TVSS1 PVSS DVSS AVSS2 AVSS1 XTAL1 XTAL2

UNMOUNT TX13

IF_SEL1 2

NFC_AVDD NFC_DVDD

VBAT VBAT2 VCO_VDD VDHF PMUVCC PMU_GND VSS AVDD_in AVDD_out DVDD PVDD TVDD TVDD_OUT VEN_MON VEN IF0 IF1 IF2 IF3 IRQ SVDD SIGIN SIGOUT SIMVCC SWIO EXT_SW_CTRL TX1 TX2 RX VMID ANT1 ANT2

R4408 0R1J /@ NFC_XTAL1 NFC_XTAL2

1

1

C4406 N/A 1UF6.3VX5RC2K

1

1

2

C4405 0.1U6.3VX5RC1K N/A

2

C

D8 F8 D1 C1 A8 G7 F6 G1 F2 A5 A4 G8 F7 E8 B7 E4 B4 C4 D4 A3 C8 E7 D7 B8 C7 D6 H6 H7 H4 G4 G5 G6

2

UNMOUNT


U4401 NFC_VCO NFC_VDHF

18PF/50V /@ C3640 2 1 18PF/50V TX22

2

PF2

NFC_VBAT

18PF/50V C3631 1

2

L4452 N/A 2TX21 1 560NH

1 R4411 0R2J

N/A

1

560NH R4405 1MR1J N/A

TX2

TX12

2

2

N/A

1

L4451 2TX11 1

2

TX1

R4452 0Ohm 1 N/A

1

NFC_SDA NFC_SCL NFC_IRQ NFC_GPIO4

2

N/A N/A N/A N/A

1

R4401 R4402 R4403 R4404

2

2 2 2 2

2

1 1 1 1

UNMOUNT

1

0R1J 0R1J 0R1J 0R1J

R4451 N/A 1KOhm C3620 100NF10V N/A

ANT Matching R9814 2KOhm N/A

2

NFC_SDA_R NFC_SCL_R NFC_IRQ_R NFC_GPIO4_R NFC_VEN

CAM_I2C_SDA CAM_I2C_SCL 13 NFC_IRQ_R 6 NFC_GPIO4_R 6 NFC_VEN

C3619 1 RXV

1NF/25V N/A

1

9,25,26,31 9,25,26,31

D

2

1

2

4

1

5

UNMOUNT

PN65NET1/C205020 N/A NFC_XTAL1 N/A X4401 27.12Mhz NFC_XTAL2

2

2

1

1

4


B

3 1

ADDRESS 28H 29H 2AH 2BH

2

IF0(ADDR0)IF1(ADDR1) 0 0 0 1 1 0 1 1


B

A

A

Title : NFC Engineer:


4

3

2

Project Name

Jamie Tseng Rev

ME370T


Sheet 1

2.0 44

of

60

5

4

SYSTEM Page.48 D

VDD_5V0_SYS

VBATT

Page.49

VDD_USB1_VBUS

Page.49

VPH_PWR_CHGR

D

VBATT

DOCK_5V

Page.49

1

+3VSUS

VDD_5V0_SYS

Page.49

2

Power

+3VSUS

Page.48

3

SMB347_DC_IN VDD_USB1_VBUS VDD_AC_BAT

MAX77663 SD0(6A)

Page.51

VDD_CPU

Page.51

VDD_CORE

Page.51

VDD_1V8_GEN

VDD_1V0_GEN

MAX77663 SD1(3A) VDD_1V2_SOC

MAX77663 SD2 (2A) VDD_1V8_GEN

MAX77663 SD3(2A)

Page.51

+1.35V

+1.35V

C

C

B

B

A

A

Title : BB-POWER I/F Engineer:


4

3

2

Project Name

Richard Lin Rev

ME370T Sheet


2.0 45

of

60

5

4

3

2

BAT=3V~4.2V

+3VSUS POWER SUPPLY

VDD_AC_BAT

+3VSUS_Iout = 2.5A Iq=50uA , Isd=1uA

+3VSUS

+3VO PL8201 N/A 80Ohm/100Mhz

2 1

P_+3VSO_VIN_S

11 10

P_+3VSO_EN_10

12 1

P_+3VSO_VINA_10 P_+3VSO_PS/SYNC_10

GND /@ PR8211 1

13 2 16

0Ohm 2

1

VIN2 VIN1

VOUT_1 VOUT_2

EN FB

4 5

GND

GND

PG

14

P_+3VSO_PG_10

PR8202 1MOHM 2 2

+3VO

GND1 GND2

1

PR8204 N/A 68KOhm

15 GND

1

1 2

P_+3VSO_FB_R_10

2 N/A

1

PC8201 N/A 4.7pF/50V

2 1

PR8206 /@ 1MOhm nbs_r0201_h12_000s

2 PR8203 N/A 180KOhm

GND

Vo=0.5*(1+R1/R2)=3.28V

PR8201 0Ohm N/A nbs_r0201_h10_000s

GND (<0.4V)

0805=>50mil

2

1

PS/SYNC

D

GND

P_+3VSO_FB_10

GND

PS/SYNC

N/A

VINA

PGND

1

N/A

3

TPS63020DSJR N/A

nbs_r0201_h10_000s

1

N/A

2

6 7

120 mil

2 /@ R0805 nbs_r0805_short_h28_000s

PJ8200 SHORT_PIN /@

PC8212 22UF/6.3V

L2_1 L2_2

2

1

L1_1 L1_2

PC8209 22UF/6.3V

8 9

2

N/A

PR8200 0Ohm PC8204 /@ 0.1UF/10V 1 2 N/A

PWM Mode

PJP8201 1

4.4x4.2x1.2mm PU8200

GND

10,21 EN_VDD_PNL

120mil

P_+3VSO_LX2_S

N/A PC8208 22UF/6.3V

1 2

N/A GND

2.2UH 2

Irat=2.75A 22UF/6.3V PC8205

1 2

22UF/6.3V PC8200

1

N/A GND

Power Save Mode

PL8200 1

P_+3VSO_LX1_S

2 2

1

P_+3VSO_VIN

0.1UF/10V PC8211

120mil D

1

>1.2V GND

External Clock PR8208

C

1

50 EN_3V3_SYS

C

P_+3VSO_EN_10 PC8207 1000PF/50V /@

2

PR8207 100KOhm r0201 /@

N/A 2

0Ohm r0201

2

1

VDD_5V0_SYS

+5VSUS POWER SUPPLY

10 EN_5V0_SBY

4 8

PR8403 1MR2F /@

5 11

RT9276_FB

1

EN

GND1 GND2

2

RT9276GQW /@

2 PC8403 10U6.3VX5RC3M /@

PC8405 0.1U6.3VX5RC1K /@

PR8404 110KOHM /@

B

1

1

PR8401 1MR1J /@

B

PC8401 10P25VNPOC1J /@

1

LBO PGND PGOOD#

2

3

LBI

2

VOUT FB/NC

RT9276_VOUT

2

LX VBAT

2

1

2 PR8400 100KR1J /@

7

1

2

PC8400 /@ N/A

RT9376_LBI

5VO

PU8400 9 6

Irat=1.7A

1

VDD_AC_BAT

PL8401 1

PL8400 /@ 80Ohm/100Mhz 1 2

/@ 2

r0805_short_h28

1

BAT=3V~4.2V

PJP8400 1

Iq=25uA , Isd=1uA

/@ 2.2UH 2 RT9276_SW

2

+5VSUS_Iin = 1A

1

PS/SYNC , EN Hi ----> over 1.2V Low --> under 0.4V

1

External Sync. Mode

PR8405 1MR1J RT9276_LBO_R

1

/@

2

VDD_1V8_GEN

PR8402 1MR1J N/A

1

2

7,29 EN_5V0_SBY

A

A

Title : 5V & 3.3V External Engineer:


4

3

2

Project Name

Timmy Wu Rev

ME370T


Sheet 1

2.0 48

of

60

5

4

3

1

BAT CON 453R2F PR8904 2 1 N/A

VBATT

PU8900

0Ohm

B1

MIDUSBIN

A2

10UF/16V 2 N/A 10UF/16V 2 N/A

B2

PC8916 1

22NF/16V N/A 2

USBIN1 USBIN2

BOOT

8

2

DCIN2

PC8917 1 PC8918 1

A4

0805

PC8919 PC8922 10UF/16V N/A

1U10VX5RC2K N/A SMB347_VDDCAP 2

1

SW1 C1

SW2

/@

1

USB1_ID

F1

1

2

VSYS1 OTG/ID VSYS2

For layout FETDRV

D4

STAT

VDD_AC_BAT

C2

PWR_I2C_SDA

SMB_I2C_SCL

F2

SMB_I2C_SDA

F3

D3

SDA

VCHG

SMB347_EN

C4

SMB347ET1699Y N/A

VDD_AC_BAT

1

1

1

2

VDD_AC_BAT

1

2 PC8906 N/A 22U6.3VX5RC5M

2

1 PC8907 N/A 0.1U6.3VX5RC1K

2

1 PC8908 N/A 1000P25VX7RC1K

C

0Ohm nbs_r0201_h12_000s N/A

VDD_AC_BAT

VDD_AC_BAT PRT8900 10KOHM N/A

P_CHG_SW

VDD_AC_BAT

2 PC8902 N/A 4.7UF6.3VX5RC2K 2 PC8904 N/A 0.1U6.3VX5RC1K

SMB347_THRM

USB5/1/HC(USB9/1.5/HC) EN

2 PC8911 N/A 22U6.3VX5RC5M

1

2 C3

2

THERM

D-

1

Charger preset to LOW enable

D+

1

VBATT

PR8901 10KR1J N/A

PR8906

D2

33 SMB347_USB51HC_CHGR

PC8920 47PF/50V 2 1 N/A

VBATT

1

1

E1 D1

SMB347_VDDCAP VBATT VBATT

GND1

100R1J USB1_D_FP_SMB347 1 100R1J 1 USB1_D_FN_SMB347

GND2

PR8902 2 PR8903 2

N/A

B4

SHORT_PIN 2 /@

INOK/SYSOK(CHG_DET_N)

F4

C

N/A

PJP8901 1

C5

14,28 USB1_DP 14,28 USB1_DN

E2

E3

SUSP VCHG

33 SMB347_ACOK#

E5

SCL VBATT

33 SMB347_SUSP_CHGR

PQ8902 P261AFEA N/A

5

CHGOUT2

0R2J 2 0R2J 2

E4

2

6,26,27,50

PR8907 1 PR8908 1

PWR_I2C_SCL

240 mil

8 7 6 D 5

CHGOUT1

6,26,27,50

D

WTOB_CON_6P N/A

D5

S

33 SMB347_STAT


1UH

B3

G

F5

6 5 4 3 2 1

VDDCAP

T8900

c0805

P_CHG_SW

A3

PD8901 MMSZ5245B-7-F N/A

N/A

SIDE1

6 5 4 3 2 1

4 3 2 1

PC8921 N/A 10UF/16V

2

1 PC8923 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s

2

2

1

1

PL8902

7

SIDE2

1

A1

MIDDCIN

1

B5

R9947 1 N/A 2

CON7312

DCIN1

1

VDD_USB1_VBUS SMB347_DC_IN

453R2F PR8905 2 1 N/A

SMB457_BOOT

BAT54CW

SMB347_DC_IN

A5

D

3 N/A

2

SMB347_USB_IN from Micro USB Conn.

1

PD8900

SMB347_VDDCAP

SMB347_DC_IN from Docking Conn. SMB347_USB_IN

2

1

2 PC8909 N/A 0.1U6.3VX5RC1K

1

N/A 2 PC8910 1000P25VX7RC1K

PC8869 N/A 470PF/50V nbs_c0603_h37_000s

1

P_CHG_SNB_S

2

1 PR9128 100KOhm 5% N/A 2

PR9121 100KOhm 5% /@

2

2

B

PR9129 100KOhm 5% N/A

SMB347_SUSP_CHGR

1

SMB347_EN

1

SMB347_USB51HC_CHGR

PR9127 100KOhm 5% /@

2

2

2

PR9120 100KOhm 5% N/A

PR8804 1Ohm N/A

PR9130 100KOhm 5% /@

B

VDD_AC_BAT

Delete PR9131 because PU resistor is placed on page33(R294) SMB347_STAT

A

A

Title : Charger SMB347 Engineer:


4

3

2

Project Name

Timmy Wu Rev

ME370T


Sheet 1

2.0 49

of

60

Main PMIC Page 1 of 3 (DC I/P, Reset, GPIO & Crystals)

PU900C

PC9105 N/A 0.1UF/6.3V nbs_c0201_h13_000s

1/3

GPIO_INA

G6

VDD_AC_BAT

INI2C 1

1

GPIO_INB

VDD_1V8_GEN

G5

N/A PC9111 0.1UF/6.3V nbs_c0201_h13_000s

1

2

2

MBATT

PC9106 N/A 0.1UF/6.3V nbs_c0201_h13_000s

A2

PC9110 0.1UF/6.3V N/A nbs_c0201_h13_000s

MON

PR9109 N/A 100KR1J nbs_r0201_h12_000s 5%

VDD_1V8_GEN PR9110 100KR1J N/A nbs_r0201_h12_000s 5%

PR9111 47KR1J N/A

G7

EN_AVDD_USB from MAX77663 GPIO2, check PU resister in PMU side(100k PU to VPH_PWR_CHGR)

2

GPIO0

VDD_AC_BAT

1

C3

VDD_AC_BAT

SDA SCL

1

F2 E2

2

PMU_I2C_SDA PMU_I2C_SCL

2 0R2J 2 0R2J

1

PR9131 1 PR9132 1

6,26,27,49 PWR_I2C_SDA 6,26,27,49 PWR_I2C_SCL

2

E3

2

2

1

VDD_1V8_GEN

1 0R1J

N/A 2

PMU_VBACKUP

D10 1

nbs_r0201_h12_000s

2

Note: 1.1K is not needed for this battery

GPIO2 GPIO3

PC9107 N/A 0.1UF/6.3V nbs_c0201_h13_000s

A10 MAX_XTAL_IN 2

BBATT

B10

XGND_1 XIN

X3101

1

32.768khz

VDD_1V8_GEN

MAX_XTAL_OUT

PMU_CGND

1 2 6,14 CORE_PWR_REQ 6 CPU_PWR_REQ

C10

XOUT

N/A PR9113 N/A 100KR1J nbs_r0201_h12_000s 5%

C9

Active Low Active - High

N/A PR9115 1 0R1J 2 nbs_r0201_h12_000s PR9116 N/A 1 0R1J 2 nbs_r0201_h12_000s

Active - High

GPIO5 GPIO6 GPIO7

C7

CORE_PWR_REQ_PMU

C5

CPU_PWR_REQ_PMU

C6 E10

E5

Active High or Low

33 ACOK#_PMIC

C8

6

D2

PWR_INT#

PMU_CLK32K_OUT_GPIO4

G3

PR9124 N/A 1 0R1J 2 nbs_r0201_h12_000s N/A PR9125 1 0R1J 2 nbs_r0201_h12_000s PR9126

2 N/A CLK_32K_IN

CLK_32K_IN

48 6

nbs_r0201_h12_000s

H3 G4

1 33R1J

EN_AVDD_USB 14 EN_3V3_SYS

CPU_PWR_REQ_PMU_GPIO PWM, VRTC domain

PR9122 N/A 1 0R1J 2 nbs_r0201_h12_000s

CPU_PWR_REQ 6

????

H4

0229 EMI add

NRST_IO

SYS_RESET#

F9 PC9109 0.1UF/6.3V nbs_c0201_h13_000s /@

XGND_2 D9

PMU_CLK32K_OUT

EN0

PR9117 1 33R1J 2 /@ nbs_r0201_h12_000s

EN2 SHDN

GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND(SNSN_SD4) GND(SNSP_SD4) GND(FB_SD4)

LID ACOK NIRQ

E4 D5 D6 D7 E6 E7 F3 F4 F5

SYS_RESET#

FB_SD0

6,20,32

CLK_32K_IN GPIOx GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7

EN1

CORE_PWR_REQ to MAX77663 EN1, PU resister R14 in CPU side (100k PU to VDD_1V8_GEN), delete R9114 CPU_PWR_REQ to MAX77663 EN2, PD resister R15 in CPU side(100k PD), delete R9118

EN_3V3_SYS_R

H8

SYS_RESET# to MAX77663 nRSTIO & T30 SYS_RESETn, R278 PU 4.7K to VDD_1V8_GEN on page.32, delete PR9112

32K_OUT PMU_ONKEY#_R_PMIC

Active - Low

26 AP_OVERHEAT#

GPIO4

EN_AVDD_USB_PMIC

G8

1

BAT_COINCELL

H7

2

30 BAT_COINCELL

GPIO1

MAX77663

PR9107

Alternate Mode Low-Power Mode Control Input Flexible Power Sequencer Output Flexible Power Sequencer Output Flexible Power Sequencer Output 32kHz Output (32K_OUT1) SD0 Dynamic Voltage Scaling Input SD1 Dynamic Voltage Scaling Input Reference Output 1.25V buffered reference output.

51

MAX77612AEMJ+ N/A

26 THERMAL#_R

1 0R1J

/@ /@ 2

nbs_r0201_h12_000s

1 0R1J

N/A 2

nbs_r0201_h12_000s

1

1

R2613

PJ9102 PR9114 PMU_ONKEY#_R

2

PJ9101 SHORT_PIN 1 2

33 PMU_ONKEY#

PC9108 0.1UF/6.3V nbs_c0201_h13_000s /@

PMU_CGND

2 SHORT_PIN /@

0229 EMI add

Title : PMIC 1/3 ASUSTeK COMPUTER INC. EPAD Size Custom Date:

Project Name

Engineer:

Timmy Wu Rev

ME370T


Sheet

2.0 50

of

60

Main PMIC Page 2 of 3 (Main DC/DC Converters)

VDD_AC_BAT PU900A

VDD_AC_BAT

VDD_1V0_GEN

2/3

AVSD

6000mA

LXB_SD0

Irat=4.2A N/A PL9305 1UH 1

Irat=4.2A N/A

H6 J6

2

VDD_AC_BAT

PGA_SD0_1(PG_SD0) PGA_SD0_2(PG_SD0)

LXA_SD0

J3 J4

PGB_SD0_1(PG_SD4) PGB_SD0_2(PG_SD4)

PJP9306 VDD_AC_BAT_INB_SD0

2

1

R0805 nbs_r0805_short_h28_000s

H2 J2 PC9303 10UF/6.3V N/A

FB_SD0 SNSP_SD0 SNSN_SD0

VDD_AC_BAT

F6

VDD_AC_BAT_IN_SD1

2

1

R0603

H10 J10

IN_SD1_1 IN_SD1_2

PC9304 10UF/6.3V N/A

LX_SD1_1 LX_SD1_2

PCE9301 100UF/6.3V /@

GND FB_SD0

50

F7 F8

PL9306 2

N/A

FB_SD0

G9 G10

VDD_CPU_SENSE

5

GND_CPU_SENSE

5

1UH

VDD_1V2_SOC

PJP9312

LX_SD1

VDD_PMU_1V2_DCDC1_RS

2 /@

1

Irat=4.2A N/A

R0805

nbs_r0805_short_h28_000s

3000mA

1

/@

PJP9307 1

N/A

INB_SD0_1(IN_SD4) INB_SD0_2(IN_SD4)

2

2

PJP9301 SHORT_PIN /@

F10 2

PG_SD1

1

/@ 1

H5 J5

+ remove and bypass the shunt after routing

2

LXB_SD0_1(LX_SD4) LXB_SD0_2(LX_SD4)

J7 J8

1

LXA_SD0_1(LX_SD0) LXA_SD0_2(LX_SD0)

1

INA_SD0(IN_SD4) INA_SD0(IN_SD0)

2

2

1

H9 J9 PC9302 10UF/6.3V N/A

22UF/6.3V PC9308

VDD_AC_BAT_INA_SD0

1

2

R0805 nbs_r0805_short_h28_000s

1UH

22UF/6.3V PC9309

/@ 1

PL9304

22UF/6.3V PC9307

B2 PJP9305

remove and bypass the shunt after routing

PJP9302 SHORT_PIN /@ 2

N/A

For layout

VDD_AC_BAT

1UH

N/A

2520/2.3A

E1 F1

FB_SD2

D3

FB_SD2

PC9310 10UF/6.3V nbs_c0603_h37_000s N/A

PC9312 10UF/6.3V nbs_c0603_h37_000s N/A

1

2

/@

R0805 nbs_r0805_short_h28_000s remove and bypass the shunt after routing


LX_SD3_1 LX_SD3_2

C1 C2

LX_SD3

+1.35V 2 1UH

N/A

2520/2.3A PG_SD3

D1

PR9151 0R1J nbs_r0201_h12_000s

2

1

N/A nbs_c0805_h55_000s D4

D_SD3

FB_SD3

C4


remove and bypass the shunt after routing

FB_SD3

2

1

MAX_D_SD3

1

PC9306 10UF/6.3V N/A

2000mA

2

PC9318 N/A 1U6.3VX5RC2K nbs_c0402_h22_000s

IN_SD3_1 IN_SD3_2

1

B1 A1

2

2

1

VDD_AC_BAT N/A

PG_SD2_1 PG_SD2_2

22UF/6.3V PC9311

VDD_AC_BAT_IN_SD3 1

R0603

LX_SD2_1 LX_SD2_2

VDD_1V8_PMU_DCDC2

2

PL9302 2

2

PJP9311 1

1

/@

2000mA

PJP9309

1

1

IN_SD2_1 IN_SD2_2

PC9305 10UF/6.3V N/A

VDD_1V8_GEN LX_SD2

2


5 5

PL9303 G1 G2

1

H1 J1

VDD_CORE_SENSE GND_CORE_SENSE

2

2

1

R0603

VDD_AC_BAT_IN_SD2

E9 E8

1

2

1

PJP9308 1

2

/@

D8

2

VDD_AC_BAT

MAX77663

FB_SD1 SNSP_SD1 SNSN_SD1

PR9152 0R1J nbs_r0201_h12_000s /@

MAX77612AEMJ+ N/A

Unmount D_SD3 Logic Level SD3 Default Voltage MBATT (logic high) 1.35V Unconnected 1.5V GND (logic low) 1.2V

Title : PMIC 2/3 ASUSTeK COMPUTER INC. EPAD Size C Date:

Project Name

Engineer:

Timmy Wu Rev

ME370T


Sheet

2.0 51

of

60

Main PMIC Page 3 of 3 (LDO's)

PU900B 3/3

PR9205

B8

IN_LDO0_1

OUT_LDO1

PMU_LDO_OUT_1

B9

2

150mA

A6

IN_LDO2

OUT_LDO2

1

2


B4

IN_LDO4_6

2

PMU_LDO_OUT_4

B3

2 OUT_LDO6

PMU_LDO_7_8_IN_1V35

IN_LDO7_8

N/A PR9215 2 0R2J nbs_r0402_h16_000s

1

PR9216 /@ 2 0R2J nbs_r0402_h16_000s

1

PC9211 N/A 4.7U6.3VX5RC2M nbs_c0402_h22_000s

PR9217 N/A 2 0R2J nbs_r0402_h16_000s

1

VDD_PMU_LDO4_1V2

to T30 AVDD_DSI_CSI

VDD_PMU_LDO6_3V_1V8

to T30 VDDIO_SDMMC1 No use

VDD_PMU_LDO7_1V2

to T30 AVDD_DSI_CSI

1 N/A PC9217 1U6.3VX5RC2K nbs_c0402_h22_000s

300mA

PMU_LDO_OUT_8

A9 2

OUT_LDO8

MAX77612AEMJ+ N/A

1

0R2J nbs_r0402_h16_000s

A8

2

2

2

1

VDD_PMU_LDO3_2V8

to eMMC Vcore(VCORE_EMMC_S)

to Camera 1.8V


PMU_LDO_OUT_7

A7 1

OUT_LDO7

+1.35V

VDD_PMU_LDO2_2V8

to T30 VDD_DDR_RX

VDD_PMU_LDO5


PMU_LDO_OUT_6

B5

150mA

450mA

N/A


1

OUT_LDO4 150mA

2


PMU_LDO_OUT_5

A5

1

PMU_LDO_4_6_IN_VPH

1

PR9209

PR9213 N/A 2 0R2J nbs_r0402_h16_000s

1

PC9207 N/A 2.2U6.3VX5RC2M nbs_c0402_h22_000s

1

OUT_LDO5 150mA

1

2 0R2J nbs_r0402_h16_000s


IN_LDO3_5

N/A PC9215 1U6.3VX5RC2K nbs_c0402_h22_000s

N/A

2

VDD_AC_BAT

PR9212 N/A 2 0R2J nbs_r0402_h16_000s

1

1 2

PR9208

A4

no use

PMU_LDO_OUT_3

A3

1

PMU_LDO_3_5_IN_3V3

1

MAX77663

PR9207 N/A 2 0R2J nbs_r0402_h16_000s

VDD_PMU_LDO0_1V0

to T30 VDD_DDR_HS

VDD_PMU_LDO1

PMU_LDO_OUT_2

B6

150mA

OUT_LDO3


1

PMU_LDO_2_IN_3V3

300mA

+3VSUS


1


2

PR9206 N/A 2 0R2J nbs_r0402_h16_000s

1

2

+3VSUS

1

1

2 0R2J nbs_r0402_h16_000s

PMU_LDO_0_1_IN_1V35

1

2

N/A

2

+1.35V

N/A PR9210 2 0R2J nbs_r0402_h16_000s

PMU_LDO_OUT_0

B7 1

OUT_LDO0 150mA

N/A PC9212 2.2U6.3VX5RC2M nbs_c0402_h22_000s

PR9218 N/A 2 0R2J nbs_r0402_h16_000s

1

VDD_PMU_LDO8_1V2

to T30 AVDD_PLLx

Title : PMIC 3/3 ASUSTeK COMPUTER INC. EPAD Size C Date:

Project Name

Engineer:

Timmy Wu Rev

ME370T


Sheet

2.0 52

of

60

nexus 7 schematic

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