CHAPTER 4
FUNCTION OF COMBINATIONAL LOGIC CIRCUIT OUTLINE •
HALF-ADDER ANF FULL ADDER CIRCUIT
•
4-BIT PARALLEL BINARY RIPPLE CARRY ADDER
•
4-BIT PARALLEL BINARY CARRY LOOKAHEAD ADDER
•
BCD ADDER CIRCUIT
•
DECODER
•
ENCODER
•
MULTIPLEXER
•
DEMULTIPLEXER
•
CODE CONVERTER
•
PARITY GENERATOR & CHECKER
In the previous chapter, we already look at how combinational circuit operates. Now we will look at some specific function logic circuit. 4.1 HALF ADDER AND FULL ADDER CIRCUIT An adder circuit will add up two 1-bit binary numbers and produces the SUM and CARRY. The difference between half adder and full adder is that a full adder has a CARRY IN input besides the two 1-bit binary input. This adder circuit is a component in a computer ALU. Before we start with the design, let‟s revise on binary arithmetic operation. Binary addition 00 0 0 1 1 1 0 1 1 1 0 1(carry) 000 0 0 1 0 1 1 0 0 1 1 1 1 1 1(carry)
REMEMBER Binary arithmetic operations are not the same with Boolean expression operation.
Half Adder Circuit A half adder circuit will a 1-bit binary number (lets name it as „A‟) with 1bit binary number („B‟) and will produce 1-bit SUM and 1-bit CARRY OUT ( C O for short) output. So, this circuit will have two input (a and b) and two output (SUM and C o ) Figure 4.1 Block Diagram of a half adder.
A
FA
It‟s a good practice to start every design with a block diagram get the whole picture of the system
SUM
Co
B
Now, we start by building the truth table. Figure 4.2 Truth table for a half adder
A (input)
B (input)
SUM (output)
C o (output)
0 (low) 0 (low) 1 (high) 1 (high)
0 (low) 1 (high) 0 (low) 1 (high)
0 (low) 1 (high) 1 (high) 0 (low)
0 (low) 0 (low) 0 (low) 1 (high)
1
From the truth table we get the expression for SUM and C o below.
SUM A B A B A B Co A B Drawing the combined two circuit, Figure 4.3 Circuit for a half adder
A
SUM
B
Co
Or Figure 4.4 Circuit for a half adder (using X-OR)
A
SUM
B
Co
For a full adder circuit, it has an extra 1-bit input C in . Therefore, the truth table will have three 1-bit inputs and two 1-bit outputs. Figure 4.4 Block diagram for a full adder circuit
A
Cin
FA
SUM
Co
B
Figure 4.6 Truth table for a full adder
A (input)
B (input)
C in (input)
0 (low) 0 (low) 0 (low) 0 (low) 1 (high) 1 (high) 1 (high) 1 (high)
0 (low) 0 (low) 1 (high) 1 (high) 0 (low) 0 (low) 1 (high) 1 (high)
0 (low) 1 (high) 0 (low) 1 (high) 0 (low) 1 (high) 0 (low) 1 (high)
SUM (output) 0 (low) 1 (high) 1 (high) 0 (low) 1 (high) 0 (low) 0 (low) 1 (high)
C o (output) 0 (low) 0 (low) 0 (low) 1 (high) 0 (low) 1 (high) 1 (high) 1 (high)
2
From the truth table, we get expression SUM and C o . SUM A B Cin A B Cin A B Cin A B Cin
A (B Cin B Cin ) A (B Cin B C) in A (B Cin ) A (B Cin ) A (B Cin )
C o A B Cin A B Cin A B Cin A B Cin A B Cin A B Cin A B (Cin Cin ) A B Cin A B Cin A B A B Cin A (B Cin B) A B Cin A (Cin B)
Try to do simplification of Co using the k-map and compare the result.
A B Cin A Cin A B
Cin (A B A) A B Cin (B A) A B A Cin B Cin A B
As a result, the circuit will be Figure 4.7 Full adder circuit
A B
Cin
SUM
Co
Full adder using two half adder. Take a look back at the un-simplified C o . Let‟s do the simplification using different theorem to get a simplified expression in XOR form.
C o A B Cin A B Cin A B Cin A B Cin A B Cin A B Cin A B
Cin (A B A B) A B Cin (A B) A B
Therefore the circuit will be like this
3
Figure 4.8 Modified full adder circuit
A B
Can you spot the two half adder in figure 4.8?
SUM
Cin
Co
In a block diagram, a full adder build from two half adder are shown in figure 4.9. Figure 4.9 Modified full adder circuit
A
A
HA
HA
B
SUM
Cin
Co
4.2 4-BIT PARALLEL BINARY RIPPLE CARRY ADDER In short, a 4-bit parallel binary ripple carry adder is a circuit that will add up a 4-bit binary number (A4, A3, A2 and A1) with another 4-bit binary adder (B0, B3, B2 and B1) and 1-bit CARRY IN ( C in ) that produce a 4-bit SUM (0, 3, 2 and1) and 1-bit CARRY OUT ( C 4 ) output. Figure 4.10 Block diagram of a 4-bit parallel binary adder
4-bit binary number A A4 A3 A2 A1
C4
4-BIT PARALLEL BINARY ADDER
S4 S3 S2 S1 4-bit binary SUM
B4 B3 B2 B1 4-bit binary number B
Cin
REMEMBER C in are disabled by connecting it to ground (logic „0‟). NEVER let any input floating.
This circuit is actually comprises of four 1-bit adder (with the C in of the LSB is grounded/disabled) or with three 1-bit full adder and one 1-bit half adder (we don‟t need the C in anyway). The term ripple is to describe the carry that „rippled‟ from one full adder to the next one.
4
Figure 4.11 Block diagram of a 4-bit parallel binary adder using four 1bit full adder
A4
A3
A2
C3
C4
FA (MSB)
C2
FA
B4
C1
FA
B3
S3
A1
FA
B2
S2
Cin
B1
S1
S0
Operation of a 4-bit Parallel Adder Example 4.1 If [A] = 01012 and [B] = 11012 are applied to a 4-bit parallel adder, what is the resulting [] and C4? REMEMBER The „[ ] „ bracket is to indicate a register. Therefore, [A] can be more than 1-bit binary. We will see more of this notation in register and counter Chapter 6. Figure 4.12 Solution for example 4.1
0 1
1 1
0 0
1 1
FA (MSB)
FA
FA
FA
1
1
0
1
3 = A3+B3+C3 = 1+0+1 = 0 + 1 (carry)
2 = A2+B2+C2 = 1+1+0 = 0 + 1 (carry)
1 = A1+B1+C1 = 0+0+1 = 1 + 0 (carry)
Cin
0 = A0+B0+Cin = 1+1+0 = 0 + 1 (carry)
In example 4.1, the operation (in decimal) is 5+13=18 (taking C4 as MSB for ). This analysis is for an unsigned binary operation. In a signed binary operation, it is 5 (3) 2 (by ignoring C4). This is also correct. Example 4.2 If [A] = 01012 and [B] = 0100 2 are applied to a 4-bit parallel adder, what is the resulting [] and C4?
5
Figure 4.12 Solution for example 4.1
0 0
1 1
0 0
1 0
FA (MSB)
FA
FA
FA
0
1
0
0
S3 = A3+B3+C3 = 0+0+1 =1+0 (carry)
S2 = A2+B2+C2 = 1+1+0 =0+1 (carry)
S1 = A1+B1+C1 = 0+0+0 = 0+ 0 (carry)
Cin
S0 = A0+B0+Cin = 1+0+0 = 1 +0 (carry)
In example 4.2, the analysis is for an unsigned binary operation is 5 4 9 (taking C4 as MSB for ). In a signed binary operation, it is 5 (4) 7 (by ignoring C4). This is not correct (supposed to be +9) because there is an overflow occurred. Because this circuit only adds without knowing whether it is a signed or unsigned number, another circuit for detecting overflow occurrence and do the correction are required (we will not cover this overflow circuit in this subject). So, we have an adder. But an ALU still need to do subtraction. We can build a dedicated subtractor for this, or alternatively, we can still use the adder for subtractor. This can be done by changing the addend to its 2‟s complement form ( A B A (B) ). Although a dedicated subtractor circuit may benefit in term of speed, but it will also increase cost.
To change a binary number into its 2‟s complement form, first we need to complement the entire bit and add „1‟. We can complement a binary bit using a NOT gate. It‟s a simple solution, but we lose the „add‟ function of the adder. We need a means to control the operation of the adder to „add‟ or „sub‟. This where the XOR gate comes in. Let‟s do some examination on XOR gate first.
6
Figure 4.13 XOR gate characteristic
0 0
0
0 1
1
1 0
1
1 1
0
A B Z 0 0 1 1
0 1 0 1
0 1 1 0
When A is 0, B = Z → not inverted When A is 1, B = Z → inverted
From figure 4.13, we can use a XOR gate for inverting the bits, by setting the control bit (A) a high (1), or not by setting A to low (0). The next part is to add „1‟ to the complemented binary numbers. Remember the Cin that are connected to ground? We can use this to add „1‟, and also as a control bit to control the XOR. Figure 4.14 show the adder/subtractor circuit. 4-bit binary number A A4 A3 A2 A1 Co
Adder/Subtractor Control 4-BIT PARALLEL BINARY ADDER
S4 S3 S2 S1 4-bit binary SUM
B1 B2 B3 B4
The bar on top of the adder label but not on top of subtractor label indicates that: if it 0 →add if it 1 →sub
4-bit binary number B
Figure 4.14 4-bit parallel adder/ subtractor
The 74LS283: 4-bit Parallel Adder To connect four 1-bit full-adder to build a 4-bit parallel adder for an application is a tedious work. The 74LS283 is a 4-bit parallel adder in form of integrated circuit (IC). An IC is a specific function combinational logic circuit. The number of the IC described its family, technology and operation.
7
Figure 4.11 IC 74LS283: 4-bit parallel adder pin diagram (left) and logic symbol (right)
Vcc (16) Σ2
1
B2
2
A2
3
Σ1
4
A1
5
B1 C0 GND
16 15 14
12
A4
10
8
A3 Σ3
11
7
B3
13
74LS283 6
Vc c
9
B4 Σ4 C4
(5) (3) (14) (12) (6) (2) (15) (11) (7)
S
1 2 3
A 1
4
S
1 2 3
2 3 4
B
(4) (1) (13) (10)
4 Co
C4
(9)
(8) Gnd
74LS83: 4-bit Binary Adder with Fast Carry LAB IC‟s IC 74LS83: 4bit parallel adder with fast carry pin diagram (left) and logic symbol (right)
Vcc (5) (10) A4
1
Σ3
2
A3
3
B3
4
Vc c Σ2
16 15 14 13
74LS83 5 6
12 11
B2
7
10
A2
8
9
B4 Σ4 C4
(8) (3) (1)
C0 GND B1 A1 Σ1
(11) (7) (4) (16) (13)
S
1 2 3
A 1
4
S
1 2 3
2 3 4
B
(9) (6) (2) (15)
4 Co
C4
(14)
(12) Gnd
We can also cascade (connect) two of this IC to build an 8-bit parallel adder. The C4 of the lower nibble are connected to the Cin of the upper nibble.
8
Figure 4.12 Cascading two unit of IC 74LS283 to build an 8-bit adder
Vcc
Vcc
(16)
A1
(5)
A2
(3)
A3
(14)
A4
(12)
B1
(6)
B2
(2)
B3
(15)
B4
(11) (7)
1 2
(16)
A
3
1
4
1 2
2 3 4
B
(4) (1) (13) (10)
1 2 3 4
3 4 Co
C4
(9)
A5
(5)
A6
(3)
A7
(14)
A8
(12)
B5
(6)
B6
(2)
B7
(15)
B8
(11) (7)
Gnd (8)
1 2
A
3
1
4
1 2
2 3 4
B
(4)
5
(1)
6
(13)
7
(10)
8
3 4 Co
C4
(9)
C8
Gnd (8)
4.3 4-BIT CARRY LOOK-AHEAD ADDER One shortcoming of a ripple carry adder is that every carry generated from each full adder (stage) introduce some delay before the next stage can evaluate its carry to be send to the next stage. This delay is accumulated, and the more number of stages there is, the bigger the delay. A carry look-ahead adder eliminates these ripple carry by anticipating the C4 (for a 4-bit adder case). Actually, carry can be categorized into two types, generated carry ( C g ) and propagated carry ( C p ). Generated carry ( C g ): Carry generated when A B 1 . So, C g A B Propagated carry ( C p ): Carry is propagated when either A or B =1 and Cin=1. The Cin will be propagated to the Cout. Therefore, Cout C g C p Cin Now let‟s apply this equation to a ripple carry adder.
9
Figure 4.13 4 stage adder
STAGE 4
STAGE 3
A4
A3
Cout4
FA
B4 3
A1
Cout2
Cin4
STAGE 1
A2
Cout3 FA (MSB)
STAGE 2
FA
C in3
FA Cin1
Cin2
B3 2
C out1
B2 1
Cg2 A 2 B2
Cg4 A 4 B4
Cg3 A3 B3
Cp4 A 4 B4
C p3 A 3 B3 C p2 A 2 B2
B1 0
Cg1 A1 B1
Cp1 A1 B1
from the equation Cout C g C p Cin the Cout for each stage is: for stage 1: C out1 C g1 C p1 Cin1
for stage 2 C out2 C g2 C p2 Cin2
and Cin2 C out1 C g1 C p1 Cin1
therefore C out2 C g2 C p2 (C g1 C p1 Cin1 ) C g2 C p2 C g1 C p2 C p1 Cin1
for stage 3 C out3 C g3 C p3 Cin3
and Cin3 C out2 C g2 C p2 C g1 C p2 C p1 Cin1
10
therefore C out3 C g3 C p3 (C g2 C p2 C g1 C p2 C p1 Cin1 )
C g3 C p3 C g2 C p3 C p2 C g1 C p3 C p2 C p1 Cin1
for stage 4 C out4 C g4 C p4 Cin4
and Cin4 Cout3 Cg3 C p3 Cg2 C p3 C p2 Cg1 C p3 C p2 C p1 Cin1
therefore C out4 C g4 C p4 (C g3 C p3 C g2 C p3 C p2 C g1 C p3 C p2 C p1 Cin1 )
C g4 C p4 C g3 C p4 C p3 C g2 C p4 C p3 C p2 C g1
1
B1
FA
A1
2
3 4
B1
FA
B1
FA
B1
FA
Cin A1 A1 A1
Figure 4.14 4 stage carry look ahead adder
Cin
C p4 C p3 C p2 C p1 C in1
11
4.4 BCD ADDER A 4-bit parallel adder can be used as a 1-digit BCD adder (1 BCD digit uses 4-bit). Keep in mind that there is an illegal BCD code (1010 and onwards). For a BCD addition, if the resulting code is larger than decimal 9, a correction process must be done. The corrections are done by adding a decimal 6. So, we need two unit of 74LS283, one for the addition and the other for the correction (adding 6). Besides that, we will also need a circuit to detect whether correction need to be done or not. Detection is done from the sum outputs of the addition IC. So we have the C4, S4, S3, S2 and S1as the input for our detection circuit (we will use notation S instead of because the output of the addition IC is not final yet). Let‟s take a look at every condition that a correction need to be done: 1. Whenever C4 is HIGH (1) (C4 are actually S5) →sum more than decimal 15 or 2. Whenever both is S4 and S3 are HIGH (1) →sum more than decimal 12 or 3. Whenever S4 and S2 are both HIGH (1) while S3 are LOW (0). In Boolean expression (let X as output of the correction circuit, if X=1, correction is needed):
X C 4 S 4 S3 S 4 S3 S 2
C 4 S4 (S3 S3 S2 ) C 4 S4 (S3 S2 ) For adding the decimal 6, we will just use the X output from the correction circuit and feed it into the correcting adder input B3 and B2 while the other input are grounded.
12
Figure 4.15 1 digit BCD adder
Vcc
Vcc
(16)
A1 A2 A3 A4 B1 B2 B3 B4
(16)
S
(5) (3)
(3)
BCD Digit 1
(14)
S1
(12)
S2
(6)
S3
(2)
BCD Digit 2
(15)
S4
(14)
(4)
1
(12)
(1) (13)
(6)
(10)
(2)
S
2 3 4
(15)
(11) (7)
S
(5)
(4) (1) (13) (10)
S5 S6 S7 S8
(11) Co
C4
(9)
(7)
Co
C4
Gnd
(9)
Gnd
(8)
C8 (not used)
(8)
Carry forward to next digit
X
4.5 DECODER Decoder is a circuit that will detect a combination of binary code at its input and give out the one corresponding output. That means, there is only one output line that will be active (either HIGH or LOW) for every combination of binary code. For a 4-bit decoder (four input), there will be 16 possible combination (2n=24=16; n=bit). Therefore it will have 16 output lines. Figure 4.16 Decoder block diagram
A0 A1 A2
DECODER
An
O0 O1 O2 O2
INPUT
n
OUTPUT
REMEMBER For an decoder, n
if there is n input, the circuit will have 2 output
13
Basic Binary Decoder Figure 2.17 show a basic 2-bit decoder circuit and its truth table. From the truth table, we can see that only one output is active (in this case HIGH) at all time. Figure 4.17 2-bit Binary Decoder
(MSB)
A
B
INPUT A B
O0 A B
0 0 1 1
O1 A B O2 A B O4 A B
0 1 0 1
O0 1 0 0 0
OUTPUT O1 O2 0 1 0 0
0 0 1 0
O3 0 0 0 1
A 3-bit binary decoder has three input lines and eight output line. Figure 4.18 shows an active-LOW output decoder. Notice that the NAND gate is used rather than AND to get an active-LOW output. Figure 4.18 3-bit Binary Decoder
(MSB)
A
C
B
O0 A B C O1 A B C O2 A B C O3 A B C O4 A B C O5 A B C O6 A B C O7 A B C INPUT A B C
O0
O1
O2
OUTPUT O3 O4 O5
O6
O7
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
14
The most common decoder is a 4-bit decoder. It also known as a 4-lineto-16-line decoder (because it has four input and 16 output) or a 1-of-16 decoder (because only one output for any given input combination). Figure 4.19 Logic symbol for a 4-line-to16-line (1-of16) decoder
BIN/DEC
1 2 4 8
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
The 74LS138: 1-for-8 Decoder This IC is a 1-for-8 (or 3-line-to-8-line) decoder. It has three input line and eight active low output. For expansion purposes, it also has three EN input ( E1 , E 2 and E3 ) that must all be active. Figure 4.20 IC 74LS138: 1-for-8 decoder pin diagram (left), logic symbol (right) and internal circuitry (bottom).
(16) Vcc A0
1
16
Vcc
A0
A1
2
15
O0
A1
A2
3
14
O1
A2
E1
4
13
O2
E2
5
12
O3
E3
6
11
O4
7
10
O5
O7 GND
74LS138
8
9
(1) (2) (3)
0
1
1
2
2
4
3 4
(4)
5
E1 E2 E3
(5)
(15) (14) (13) (12) (11) (10)
6
&
(6)
7
(9) (7)
GND
O6
(8)
A2 A1 A0 E1 E2 E3 07
06
05
04
03
02
01
00
15
To form a 1-for-32 decoder, four unit of this IC can be cascaded. The EN will be used to select which IC will be active (remember that a decoder can only have one active output at one time) from the A3 and A4 input. We will also need an inverter. Figure 4.21 Four IC 74LS138 cascaded to form 1-for-32 decoder
A4 A3 A2 A1 A0
0 (1) (2) (3)
1
1
2
2
4
3 4
(4) (5)
5
&
+5V (6)
6 7
(15)
8
(14)
(1)
(13)
(2)
(12)
(3)
(11) (10) (9) (7)
1
9
2
10 11
4
12 (4) (5)
13 14
&
(6)
15
(15)
16
(14)
(1)
(13)
(2)
(12)
(3)
(11)
1
17
2
18
4
19 20
(10)
(4)
(9)
(5)
(7)
21
&
(6)
22 23
(15)
24
(14)
(1)
(13)
(2)
(12)
(3)
(11) (10) (9) (7)
1
25
2
26
4
27 28
(4) (5)
29
&
(6)
30 31
(15) (14) (13) (12) (11) (10) (9) (7)
The 74HC154: 1-of-16 Decoder This is a 1-to-16 decoder in form of an IC. It has 16 active-LOW outputs. It also has other input such as CS1 and CS 2 . These two input must be both LOW to enable (EN) this IC (if not, the output will always be HIGH). Figure 4.22 IC 74HC154: 1-for-16 decoder pin diagram (left) and logic symbol (right)
(24) Vcc
0
Vc c
1
23
A0
2
3
22
A1
Y3
4
21
A2
A0
Y4
5
20
A3
A1
Y0
1
24
Y1
2
Y2
Y5
6
Y6
7
18
Y7
8
17
Y8
9
16
Y9
10
15
Y1 0
11
14
GND
12
13
19
74HC154
CS 2 CS 1 Y1 5 Y1 4 Y1 3 Y1 2 Y1 1
A2 A3
(23) (22) (21) (20)
3 1
4
2
5
4
6
8
7 8 9 10 11 12
CS2 CS1
(18) (19)
13
&
14
GN D
15
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (14) (15) (16) (17)
(12)
16
The purpose of having the two enable input is for cascading. As an example, two unit of this IC can be cascaded to perform as a 1-for-32 decoder. Figure 4.23 Two unit of IC 74HC154 cascaded to form a 1-for32 decoder.
(23)
A0
(22)
A1
(21)
A2
(20)
A3
Low order (1) 0 (2) 1 (3) 2 (4) 3 (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 (10) 9 (11) 10 (13) 11 (14) 12 (15) 13 (16) 14 (17) 15
1 2 4 8
CS2
A4
&
CS1
High order (1)
16 17 18 (23) (22) (21) (20)
19 1
20
2
21
4
22
8
23 24 25 26 27 28 29
CS2 CS1
&
30 31
(2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (14) (15) (16) (17)
The 74HC42: BCD-to-Decimal Decoder A BCD-to-Decimal has four input lines and ten output lines. Thus, it‟s called 4 line-to-10 line decoder or a 1-for-10 decoder. The operation is like a 74HC154 (1-of-16 Decoder), but only has 10 output lines (because BCD only has ten symbol). Figure 4.24 show the logic symbol of this IC. Figure 4.24 IC 74HC42 : BCD-toDecimal decoder Logic symbol
(16) Vcc
0 1 2
A0 A1 A2 A3
(15) (14) (13) (12)
3 1 2
4
74HC42
4
5 6
8
7 8 9
(1) (2) (3) (4) (5) (6) (7) (9) (10) (11)
GND (8)
17
The 74LS47 BCD-to-7-Segment Decoder This IC can be used to drive a common anode 7-segment display. Besides that, it also has additional capabilities such as: LT : Use for lamp test. When connected to LOW, all of the segments are turned on.
(ii)
RBI : Ripple blanking input. Disable the IC when LOW.
(iii)
BI / RBO : Can be used as either input or output. Used for zero suppression. Zero suppression is to blank out the non essential zero when using several 7-segment display to display a multi digit numbers. There are two type of zero suppression: a. Leading zero suppression (figure 4.26): for example take number 20. If we are using 4 7-segment display (so it can display up to 9999) without leading zero suppression, the display will be 0020 (the non-essential zero didn‟t blank out). In short, used for whole number. b. Trailing zero suppression (figure 4.27): for example take number .1400. If we are using 4 7-segment display (so it can display up to .9999) without trailing zero suppression, the display will be .14 (the non-essential zero didn‟t blank out). In short, used for fractional number. (16) B
1
16
Vc c
C
2
15
f
LT
3
BI RBO
4
RBI
5
14
74LS47
g
13
a
12
b
D
6
11
c
A
7
10
d
8
9
e
GND
(4)
Vcc (7) BCD INPUTS
Figure 4.25 IC 74HC47 : BCD-to-7segment decoder pin diagram (left) and logic symbol (right)
(i)
LT RBI
(1) (2) (6)
1
a
2
b
4
c
8
d e
(3)
f (5)
GN D
g
BI RBO
(13) (12) (11) (10) (9) (15) (14)
(8)
18
1
c
b
a
BI RBO 2
d
4
RBI
LT
8 e f g
a
BI RBO
c
b
1 2
e
d
4
RBI
LT
8
f g
a
BI RBO 1
c
b
LT
(7) (1) (2) (6)
(3) (5)
(7) (1) (2) (6)
(3) (5)
(7) 2
d
4 8
e f g
a
BI RBO
c
b
g
f
e
d
2
8
4
1
RBI
(4) (13) (12) (11) (10) (9) (15) (14)
(4) (13) (12) (11) (10) (9) (15) (14)
(4) (13) (1) (2) (6)
(3) (5)
(7) (1) (2) (6)
(3) (5)
LT
BI RBO
c
b
a
2
1
4 d
LT RBI LT RBI a (12) (11) (10) (9) (15) (14)
(4) (13) (12) (11) (10) (9) (15) (14)
RBI
LT RBI LT RBI
(7) (1)
8 e f g
a
BI RBO
c
b
1 2
e
d
4 8
f g
1
c
b
BI RBO 2
d
4 8 e f g
a
BI RBO
c
b
1 2
d
4 8 e f g
(4) (13) (12) (11)
(9)
(10)
(15) (14)
(4) (13) (12) (11)
(9)
(10)
(15) (14)
(4) (13) (12) (11)
(9)
(10)
(15) (14)
(4) (13) (12) (11)
(9)
(10)
(15) (14)
19
(2) (6)
(3) (5)
(7) (1) (2) (6)
(3) (5)
(7) (1) (2) (6)
(3) (5)
(7) (1) (2) (6)
(3) (5)
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
Figure 4.27 Zero trailing configuration for IC 74HC47
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Figure 4.26 Zero leading configuration for IC 74HC47
4.6 ENCODER Encoder performs the reverse operation of a decoder. Instead of having a coded input like a decoder, encoder will produce a coded input depending on the input. If for decoder only one output can be active at one time, encoder only allows one active input at a time. Figure 4.28 Encoder block diagram
A0 A1 A2 A2
O0 O1 O2
ENCODER
O
n
n
INPUT
OUTPUT
Decimal-to-BCD Encoder A basic decimal-to-binary encoder required 9 input line (we don‟t need the input for decimal 0 because all output are LOW when there is no HIGH input) and four output line. Figure 4.29 Decimal-toBCD encoder circuit (left) and truth table (right).
123456789
A0 (LSB) A1 A2 A3
REMEMBER
Decimal Digit 0 1 2 3 4 5 6 7 8 9
BCD CODE
A3 0 0 0 0 0 0 0 0 1 1
A2
A1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
A0 0 1 0 1 0 1 0 1 0 1
To ensure correct operation, only one input can be active at one time.
20
The 74HC147: Decimal-to-BCD Priority Encoder. A normal encoder only can have one active input at a time. This is a problem in a case where other inputs are accidentally active. This where the advantage of the 74HC147. It is also called as 10 line-to-4 line priority encoder. The word „priority‟ in the IC name is to describe its ability to accept more than one active input at a time, but only the highest input number are encoded. For example, if input 4 and 8 are active, the output (because it is active LOW) will be 0111 2(810). (16) D4
1
16
Vc c
D5
2
15
NC
D6
3
14
A3
D7 D 8
4
A2
6
A1
7
GND
8
5
13
74LS147
12 11 10 9
(11) (12) (13)
D 3 D 2 D 1 D 9 A0
(1) (2) (3) (4) (5 (10)
1
Vcc
2
1
3
2
4
4
5
8
(9) (7) (6) (14)
A0 A1 A2 A3
BCD OUTPUT
Figure 4.30 IC 74HC147 : Decimal-toBCD encoder pin diagram (left), logic symbol (right) and truth table (bottom)
6 7 8 9
GN D (8)
D1 1 X X X X X X X X 0
D2 1 X X X X X X X 0 1
D3 1 X X X X X X 0 1 1
D4 1 X X X X X 0 1 1 1
D5 1 X X X X 0 1 1 1 1
D6 1 X X X 0 1 1 1 1 1
D7 1 X X 0 1 1 1 1 1 1
D8 1 X 0 1 1 1 1 1 1 1
D9 1 0 1 1 1 1 1 1 1 1
A3 1 0 0 1 1 1 1 1 1 1
A2 1 1 1 0 0 0 0 1 1 1
A1 1 1 1 0 0 1 1 0 0 1
21
A0 1 0 1 0 1 0 1 0 1 0
The 74LS148: 8-line-to-3-line Encoder This IC has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes: (i) (ii)
Enable input, EI (input): must be LOW for the IC to function. Enable output, EO (output): LOW when EI=LOW and all input inactive. GS (output): LOW when EI=LOW and any input is active.
(iii)
(16)
Figure 4.31 IC 74HC148 : Decimal-toBinary encoder pin diagram (left), logic symbol (right) and truth table (bottom)
D4
1
16
D5
2
15
D6
3
14
D7
4
13
EI
5
A2
6
11
A1
7
10
GND
8
9
74LS148
12
Vc c
(5)
EO G S D 3 D 2 D 1 D 0 A0
(10) (11) (12) (13) (1) (2) (3) (4)
EI
Vcc
0
EO GS
(15) (14)
1 2
1
3
2
4
4
(9)
A0
(7)
A1
(6)
A2
5 6 7
GN D (8)
EI
D0
D1
D2
D3
D4
D5
D6
D7
A2
A1
A0
GS
EO
1 0 0 0 0 0 0 0 0 0
X 1 X X X X X X X 0
X 1 X X X X X X 0 1
X 1 X X X X X 0 1 1
X 1 X X X X 0 1 1 1
X 1 X X X 0 1 1 1 1
X 1 X X 0 1 1 1 1 1
X 1 X 0 1 1 1 1 1 1
X 1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1
1 1 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 1
Similar to other IC‟s, two unit of this IC‟s can be cascaded to form a 16 line-to-4 line decoder with some external gates.
22
4
5
6
15 (4)
(3)
14
7
(6)
3
13 (2)
(1)
(13)
(12)
(11)
(14)
(15)
2
12
4
EO GS
1
11
2
A1
0
10
(7)
EI
(10)
(5)
7
9
(9)
6
8
(4)
(3)
(2)
5
7
1
A0
6
4
(14)
4
2
(15)
3
1
EO GS
2
5
(6)
1
4 (1)
(12)
(11)
0
3 (13)
2
1
(7)
EI
(10)
(5)
0
(9)
Figure 4.32 Cascading two unit of IC 74HC148 to form a 16 line-to-4 line decoder
A3
A2
4.7 MULTIPLEXER Multiplexer (or MUX for short) is also called a data selector. We have more than one „DATA‟ input that will be selected by using the „SELECT‟ to be passed through the MUX to the output line (only one output line exists). Figure 4.33 Multiplexer block diagram
MUX
I0 I1 I2
Z
I3
A MUX operation is similar to a Drink Vending Machine. We have a selection of drinks that will be dispense in a same compartment.
In-1 DATA INPUT
OUTPUT 2
n
SELECT
23
A Basic 4 Input MUX For a four input MUX, we need 2-bit select input (this will give us four possible binary combination) to address which input to be selected and then passed through to the output. Figure 4.33 4 input multiplexer circuit (left) and truth table (right).
I3 S1 0 0 1 1
I2 Z
I1
S0 OUTPUT 0 Z = I0 1 Z = I1 0 Z = I2 1 Z = I3
I0
S1
S0
The 74LS151: 8 line-to-1 line MUX/ Data selector This IC has eight active high input line for data, two outputs (one is inverted), and three active high SELECT inputs to address the eight data input. It also has another active low EN input for expanding purposes. Figure 4.34 IC 74LS151 : 8 line-to-1 line MUX pin diagram (left) and logic symbol (right)
(16) I3
1
16
Vcc
I2
2
15
I4
I1
3
14
I5
I0
4
13
I6
Z
5
12
I7
(4) I0
Vcc
S0
(3) I1
S1
I2
S2
(2)
74LS151
6
(10) (9)
(1) I3 (15)
Z
(11)
11
S0 (14)
EN
7
10
S1
GND
8
9
S2
(13) (12)
I4
(5)
I5
(6)
Z Z
I6 I7
(7) EN
GND (8)
24
Using an inverter and an OR gate, two unit of this IC can be cascaded to form a 16 line-to-1 line MUX. Figure 4.35 Two unit IC 74LS151 cascaded to form a 16 line-to-1 line MUX
(SELECT) S0 S1 S2 S3
(3) DATA INPUT
(2) (1) (15) (14) (13) (12) (7)
I0
S0
I1
S1
I2
S2
(11)
(4)
(10)
(3)
(9)
(2)
I3 I4
(5)
DATA INPUT
(4)
I5 I6 I7 EN
(1) (15) (14) (13) (12) (7)
I0
S0
I1
S1
I2
S2
(11) (10) (9)
I3 I4
(5)
I5 I6 I7 EN Z
MUX for Logic Function Generation A MUX can also be configured to generate logic function. For a three input logic function (eight possible input combinations), we need an 8 line-to-1 line MUX. The SELECT input will be the logic function input and all the MUX data input will permanently be connected to HIGH (1) or LOW (0) depending on the truth table. Figure 4.36 show how MUX can be used to generate logic function.
25
Figure 4.36: Using MUX to perform logic function
S2
S1
INPUT A B C 0 0 0 0
0 0 1 1
1 1 1 1
0 0 1 1
0 1 0 1 0 1 0 1
S0
VCC (4)
OUTPUT Z
I0
Vcc
S0
(3)
0 1 1 1
I1
I0 (GND) I1 (VCC) I2 (VCC) I3 (VCC)
0 1 0 1
S1
(2) I2
S2
(11) (10) (9)
C B A
(1) I3 (15)
I4 (GND) I5 (VCC) I6 (GND) I7 (VCC)
(14) (13) (12)
I4
(5)
I5
(6)
Z Z
I6 I7
(7) EN
4.8 DEMULTIPLEXER A demultiplexer (DEMUX for short) perform the reverse operation of a MUX. It has one data input and several output lines. Data are channeled to one of the outputs lines depending on the SELECT input. Figure 4.37 Demultiplexer block diagram
DEMUX O0 O1 O2 I O3
A DEMUX operation is like a paper sorter in a Photostat machine. Each tray will has one complete copy of the document.
On-1
DATA IN 2
n
DATA OUTPUT
SELECT
26
The 74ALS138: 1 line-to- 8 line DEMUX We have seen this IC in topic 4.5 (decoder). This IC can also perform as a DEMUX. Remember that this IC has three inputs (A0, A1 and A2) that can be use as SELECT and the eight outputs is already similar to a DEMUX. But remember that DEMUX has one more input, that is the „DATA IN‟. What left of the IC input pins are the three EN ( E1 , E2 and E3). So, we can use either of this input for „DATA IN‟ but remember that all the output is inverted. Therefore, it‟s more practical for using E1 or E2 than E3 (because we need an extra inverter). (16)
Figure 4.38 IC 74LS138: 1-for-8 decoder/ demultiplexer (in DEMUX configuration)
Vcc A0 A1 A2
(1) (2) (3)
0
1
1
2
2
4
3 4
DATA IN
E1 (4) E2 (5)
5 6
&
E3 (6)
GN D
5V
7
(15) (14) (13) (12) (11) (10) (9) (7)
(8)
4.9 COMPARATOR Comparator circuit, just like its name, will compare two binary numbers. The simplest comparator will just detect equality (non equality) while a more complex circuit can also determine which binary number is larger. For bit equality/ non equality check, we can use XOR (or XNOR) gate. Figure 4.39: Revision on XOR operation
0 0
0
0 1
1
1 1
0
1 0
1
Input is equal, output =„0‟
Input is not equal, output =„1‟
So, a 4-bit binary comparator (to detect equality only) can be build by using four XOR gate and a AND gate.
27
Figure 4.40: 4-bit equality comparator.
A3 A2 A1 A0
1st Binary number
If all the input bit are equal, Z =‘0’; Else, Z= ‘1' Z
B3 B2 B1 B0
2nd Binary number
2-bit Magnitude Comparator This circuit will compare two 2-bit binary inputs A (A1, A0) with another 2-bit binary number B (B1, B0) and determine whether it is equal, and if not, which one is greater. So this circuit will have four inputs and three output.
A1 M = 1, if A=B
COMPARATOR
Figure 4.41: Block diagram of a magnitude detector.
A0
B1
N = 1, if A>B P =1, if A
B0
*only one output can be active at a time
Therefore, the truth table are: Figure 4.42: 2-bit magnitude detector truth table.
A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
(DEC) (0) (0) (0) (0) (1) (1) (1) (2) (2) (2) (2) (2) (3) (3) (3) (3)
B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
(DEC) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3)
M 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
OUTPUT N 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
28
P 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
Using three k-map (one for each output), we will get the expression for M, N and P. M (A1 B1) (A0 B0)
N A1 B1 A0 B1 B0 A1 A0 B0 P A1 B1 A0 B1 B0 A1 A0 B0 M N Drawing the circuit give us: Figure 4.43: 2-bit magnitude detector circuit
A1 A0
B1 B0
M
N P
4-bit Magnitude Comparator Circuit. Just like an IC‟s, 2 unit of 2-bit magnitude comparator can be cascaded to perform as a 4-bit magnitude detector (with some external gate). Figure 4.43: 4-bit magnitude comparator circuit using two 2-bit magnitude comparator
A3 A2
M N
B3
M = 1, if A=B
P
B2
N = 1, if A>B
P =1, if A
M N
B1
P
B0
29
The 74HC85:4-bit Magnitude Comparator. Comparator is also available in IC form. It has eight input line for the two sets of 4-bit binary number (A3, A2, A1, A0, B3, B2, B1 and B0), and another three inputs for cascading option. Figure 4.44 IC 74LS85 : 4-bit Magnitude Comparator pin diagram (left) and logic symbol (right).
(16) 1
16
Vc c
A
2
15
A3
A=Bin
3
14
B2
A>Bin
4
A
5
A=Bout
6
11
B1
A>Bout
7
10
A0
GND
8
9
B0
B3
13
74HC85
12
(15) (13) (12)
A2
(10)
A1
(4) (3) (2) (1) (14) (11) (9)
A3
Vcc
A2 A1 A0 A
A
A=Bin
A=Bout
A>Bin
A>Bout
(5) (6) (7)
B3 B2 B1 B0
GN D (8)
For the IC to function, pin 3 needs to be connected to HIGH while pin 2 and 4 connected to LOW. This connection is necessary for a single IC operation and also for the lowest-order IC in a cascaded comparator. Figure 4.44 2 unit of IC 74LS85 cascaded to form an 8-bit Magnitude Comparator
Lower-order comparator (15) (13) (12) +5V
(10) (4) (3) (2) (1) (14) (11) (9)
Higher-order comparator (15)
A3
(13)
A2
(12)
A1
(10)
A0 A
A
A=Bin
A=Bout
A>Bin B3 B2 B1 B0
A>Bout
(5)
(4)
(6)
(3)
(7)
(2) (1) (14) (11) (9)
A7 A6 A5 A4 A
A
A=Bin
A=Bout
A>Bin
A>Bout
(5) (6) (7)
B7 B6 B5 B4
30
4.10 CODE CONVERTER Code converter circuit contains combinational logic gates to convert one code to another.
BCD-to-Binary Conversion This circuit wills covert a two digit BCD (from 0 to 99) into binary value. It has eight input (each BCD consist of 4-bit) and seven output (7-bit is sufficient to represent decimal 99). The conversion steps are: (i)
Figure 4.45 BCD –tobinary conversion: Step 1
Find the binary number for each of the BCD digit value (remember that each digit has a different weight). Let examine a two digit BCD code.
8
BCD NUMBERS
BCD CODE
WEIGHT (in decimal)
80
BINARY NUMBERS
7
D1
C1
B1
A1
D0
C0
B0
A0
1
0
0
0
0
1
1
1
40
20
10
8
4
2
1 BINARY NUMBERS
1
0
1
0
0
0
0
2
1
0
1
0
0
0
0
2
0
1
0
1
0
0
0
2
0
1
0
1
0
0
0
2
0
0
1
0
1
0
0
2
0
0
1
0
1
0
0
2
0
0
0
1
0
1
0
2
0
0
0
1
0
1
0
2
(ii)
Add up all the binary that represent every BCD digit.
For this purpose, we need two unit of 74LS283 (4-bit parallel binary adder) because we have eight inputs. For interconnecting these IC, let take a look at the binary number (this time in table form)
31
Figure 4.45 BCD –tobinary conversion: Step 2 (Truth table)
INPUT BCD BIT
b6
b5
D1 C1 B1 A1 D0 C0 B0 A0
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
OUTPUT
D1
Figure 4.46 BCD –tobinary conversion circuit
D1
C1
B1
b4 1 0 1 0 0 0 0 0 D1+ B1
C1
A1
D0
C0
B0
b2
0 1 0 1 1 0 0 0 C1+ A1+ D0
b1
0 0 1 0 0 1 0 0 B1+ C0
b0
0 0 0 1 0 0 1 0 A1+ B0
0 0 0 0 0 0 0 1 A0
A0
(5) (3) (14) (12) (6) (2) (15) (11) (7)
(5) (3) (14) (12) (6) (2) (15) (11) (7)
(iii)
b3
1 2 3
A 1
4
S
1 2 3
2 3 4
B
(4) (1) (13) (10)
4 Co
C4
(9)
1 2 3
A 1
4
S
1 2 3
B
2 3 4
(4) (1) (13) (10)
4 Co
b6
b5
b4
b3
b2
b1
The result is the BCD in binary.
32
b0
Binary-to-Gray Code Conversion We have discussed about this in chapter 2. The steps are: (i) (ii) Figure 4.47 Binary –togray code conversion circuit
Retain the MSB – simple, just connect to gray leftmost bit. Add adjacent binary bit, discard carry – use XOR gate.
B0
G0
B1
G1
B2
G2
B3
G3
B4 (MSB)
G4
Gray code -to-Binary conversion The steps are: (i) (ii)
Figure 4.48 Gray code – to-Binary conversion circuit
Retain the leftmost bit. Add the converted gray bit to the adjacent binary bit, discard carry.
G0
B0
G1
B1
G2
B2
G3
B3
G4
B4 (MSB)
33
4.11 PARITY BIT GENERATOR & CHECKER Parity bits are determined by the numbers of „1‟s in the code (data string) by summing up all the bits (discarding carry). If the result are: „0‟ – the number of „1‟s are even „1‟ – the number of „1‟s are odd The summing can be done by using XOR gate. Then it can be generated (depending on system used, whether even or odd parity system) and transmitted along with the data. Figure 4.49 Even parity generator
A6 A5 A4 A3 A2 A1
A6 A5 A4 A3 A2 A1 Even parity
Even parity generator
Figure 4.49 Odd parity generator
A6 A5 A4 A3 A2 A1
Transmitted Data
A6 A5 A4 A3 A2 A1 Odd parity
Odd parity generator
Transmitted Data
To check the parity bit with the data (this is at the receiver), calculate back the parity bit (same circuit as parity generator) and then whether the result is the same with the parity bit received (done by using XNOR) 34
Figure 4.49 Even parity checker
A6 A5 A4 A3 A2 A1 Even parity
A6 A5 A4 A3 A2 A1
Even parity checker Received Data
Figure 4.49 Even parity checker
A6 A5 A4 A3 A2 A1 Even parity
0=error
A6 A5 A4 A3 A2 A1
Odd parity checker Received Data
0=error
35
TUTORIAL OBJECTIVE QUESTION
1.
2.
Which of the following input and output value are incorrect for the 4-bit parallel binary adder/subtractor circuit in figure above? [A]
[B]
Adder/Subtractor
Cout
[]
(a)
1101
0110
0
1
0011
(b)
1001
1000
0
1
0001
(c )
1111
1011
1
0
0100
(d)
0101
1000
1
0
1011
In general, a multiplexer has (a)
one data input, several data outputs and selection inputs
(b)
several data input, several data output and selection inputs
(c)
one data input, one data output and one selection input
(d)
several data input, one data output and selection inputs
36
3.
4.
5.
Table 3 is a truth table for a 2-to-4 line decoder priority encoder. Which of the inputs and outputs combination is correct? Table 3 Inputs Outputs En
A1
A0
D0
D1
D2
D3
(a)
0
x
x
0
0
0
1
(b)
1
0
0
1
0
0
1
(c)
1
0
1
0
1
0
1
(d)
1
1
1
0
0
1
1
Table 4 is a truth table for a priority encoder. Which of the inputs and outputs combination is incorrect? Table 4 Inputs Outputs D3
D2
D1
D0
A1
A0
Y
(a)
0
0
0
0
x
x
0
(b)
0
0
0
1
0
0
1
(c)
0
0
1
x
0
1
1
(d)
1
x
x
x
1
0
1
A _____________ is a combinational circuit element that selects data from one of many inputs and directs it to a single output. (a)
encoder
(b)
multiplexer
(c)
decoder
(d)
demultiplexer
37
6.
What is the combinational logic circuit in Figure Q2 represent? (a)
3-to-8 decoder
(b)
3-to-8 encoder
(c)
BCD-to-7 segment decoder
(d)
8-to-3 encoder
7.
If all the inputs are applied simultaneously to the ripple adder shown in Figure Q3, how long does it take before the SUM and C4 become valid? Assume that the delay of each gate (within each adder stage) is tp. (a)
2 tp.
(b)
4 tp.
(c)
3 tp.
(d)
5 tp.
38
Figure 8 8.
9
The full-adder in Figure 8 is tested under all input conditions with the input waveforms shown. From your observation of the SUM and COUT waveforms, is it operating properly, and if not, what is the most likely fault?
(a)
Yes, the output SUM and COUT are correct.
(b)
No, the input CIN is accidentally connected to VCC.
(c)
No, the input B is accidentally connected to VCC.
(d)
No, the input A is accidentally connected to VCC.
The following data input has been applied to the multiplexer in Figure 9a) : D0 0 , D1 1 , D2 1 and D3 0 . The data-select inputs to the multiplexer are sequenced as shown by the waveforms in Figure 9(b), determine the output waveform.
(a) (b) (c) (d)
39
10.
11.
12.
13.
To expand a 4 bit parallel adder to an 8 bit parallel adder you must (a)
use 4 bit adders with no connections
(b)
use two 4 bit adders and connect to the sum outputs of one to the bit output of the other
(c)
use eight 4 bit adders with no interconnections
(d)
use two 4 bit adders with the carry output of one connected to the carry input of the other
If a 74LS85 magnitude comparator has A = 1011 and B = 1001 on the inputs, the outputs are: (a)
A>B = 0, A
(b)
A>B = 1, A< B = 0, A=B=0
(c)
A>B =1, A
(d)
A>B=0, A< B=0, A=B=1
A BCD to 7 segment decoder has 0100 on the inputs. The active output segments are: (a)
a,c,f,g
(b)
b,c,e,f
(c)
b,c,f,g
(d)
b,d,e,g
Data selectors are basically the same as: (a)
decoders
(b)
multiplexers
(c)
demultiplexers
(d)
encoder
40
SUBJECTIVE QUESTION 1.
The 74LS148 : 8-to-3 encoder This IC has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes: i) ii) iii)
Enable input, EI (input) : must be LOW for the IC to function. Enable output EO (output) : LOW when EI = LOW and all inputs are inactive. GS (output) : LOW when EI = LOW and any input is active.
Show how two units of 74LS148 can be used as a 16-to-4 encoder. Please state the pin number representing the D15 input (i.e. the most significant bit). 2.
Design a circuit that behaves as a 3-to-8 decoder. Use only two types of logic gates, i.e. NOT gates and AND gates.
3.
Using a 3:8 decoder in Figure 3, implement the following logic function: F(A,B,C) = A BC AB
Figure 3 4.
Match the names with the circuit diagram in Figure 4, leave blank if diagram isn’t there. (e) (f) (g) (h)
RS Latch JK Flip Flop Decoder Gated D Latch
: ______ : ______ : ______ : ______
(a) (b) (c) (d)
Master-Slave flip flop 4-bit Multiplexer Full Adder 4-bit register
: _______ : _______ : _______ : _______
41
B
A
F
C
J
D E d2
d3
D
SET
CLR
d0
d1
Q
D
Q
SET
CLR
Q
D
Q
SET
CLR
D
Q
Q
SET
CLR
Out
Q
Q
Load Clk
d2
d3 In
D
SET
CLR
Q
Q
D
SET
CLR
d1
Q
D
Q
SET
CLR
Q
Q
Clk
d0 D
SET
CLR
Q
Q
I
H
G
Figure 4
5.
A full adder can be implemented in many different ways. One of the method is by combining two half adders. Beginning with the truth table, design the circuit that function as a half adder, with the least number of gates. Then, design a full-adder circuit using the two half-adders.
42
6.
The logic diagram, truth table and logic symbol for an eight input multiplexer (74151) are given in Figure 6. By using this eight input multiplexer, design a circuit that will perform a 16 bit parallel to serial conversion. Sketch the output waveform if the input to the multiplexer is 1 1 0 0 0 1 1 1 1 0 1 0 1 1 0 1.
Figure 6 7.
Consider a 4-bit parallel adder as shown in Figure 7. It is necessary to build a look ahead carry circuit which generates the carry C3 to be fed to the full-adder of the most significant bit position. Derive C3 in terms of C0, A0, B0, A1, B1, A2 and B2. B2
B3
B1
A3
A0
A1
A2
C3
C4
B0
C2
C0
C1
Penambah penuh/ Full Adder
Penambah penuh/ Full Adder
Penambah penuh/ Full Adder
Penambah penuh/ Full Adder
S3
S2
S1
S0
Figure 7 43
8.
Figure Q8 shows the logic symbol of the integrated circuit 74151: 3 line-to-8 line multiplexer. Show in the given figure how this IC can be connected to perform the following logic expression. Label completely and include this sheet in your answer script.
Z A B C (16) (4)
Vcc
I0
S0
(3) I1
S1
I2
S2
(2)
(11) (10) (9)
(1) I3 (15) (14) (13) (12)
I4
(5)
I5
(6)
Z Z
I6 I7
(7) EN
GND (8)
9.
Prove (using Boolean theorem) that the circuit in figure 9 is equivalent to a full-adder. A
A
HA
HA
SUM
Cin
B
Co
Figure 9
10.
For the circuit in figure 10, determine the output if the input are: A4
A3
C3
C4
FA (MSB)
C2
FA
B4 S3
A2
C1
FA
B3 S2
A1
FA
B2 S1
Cin
B1 S0
Figure 10 a. [A] = 01112 and [B] = 11012 b. [A] =11012 and [B] = 10012 c. [A] = 00012 and [B] = 11112
44
11.
For the circuit in figure 10, determine the input [A] if the output and input [B] are: a. [B] = 01112 and [Σ] = 11012 b. [B] =11012 and [Σ] = 10012 c. [B] = 00012 and [Σ] = 11112
12.
By using circuit in figure 12, determine and fill in the empty field in table 1 with the correct answer (all numbers are unsigned) 4-bit binary number A A4 A3 A2 A1 Adder/Subtractor Control
Co
4 3 2 1 4-bit binary SUM
B1 B2 B3 B4
4-bit binary number B
4-BIT PARALLEL BINARY ADDER
Figure 12 BINARY NUMBER (A)
BINARY NUMBER (B)
SUM (S) SUB
A4
13.
A3
A2
A1
0 1
1 0
0 0
1 0
0
0
1
1
DEC
B4
B3
B2
B1
7
0 0 0
0
1
0
8 4
0
1
0
DEC
3 2
S4
0 1 1 0 0
S3
S2
S1
DEC
9
1 0
0 0
0 0
1 0
9 0
By using circuit in figure 12, determine and fill in the empty field in table 1 with the correct answer (all numbers are 4-bit signed). Comment on the result. BINARY NUMBER (A)
BINARY NUMBER (B)
SUM (S) SUB
A4
A3
A2
A1
DEC
B4
B3
B2
B1
DEC
0 0
1 1
1 0
1 1
7 5 -8 4 3
0
0
1
0
2
0 0
1 0
0 1
0 1
0
0
1
0
2
0 1 1 0 0
S4
S3
S2
S1
DEC
0
0
1
0
2
1 0
0 0
0 0
1 0
0
45
14.
Draw the complete connection for the two IC‟s (7483) in figure 14 to operate as an 8-bit adder. Label all the inputs and outputs completely.
Vcc
Vcc
(5) (10) (8)
1 2
(3)
(10) (8)
A
3
(1)
1
4
(11) (7)
1 2
2 3 4
B
(4)
(5)
(3)
(9)
(1)
(6) (2)
(11)
(15)
(7) (4)
3
(16) (13)
(16)
4 Co
C4
(14)
(13)
1 2
A
3
1
4
1 2
2 3 4
B
(9) (6) (2) (15)
3 4 Co
(12)
C4
(14)
(12)
Gnd
Gnd
Figure 14 15
For the circuit you build in figure 14, determine the output if the input are: a. [A] =1101 01112 and [B] = 1101 11012 b. [A] =1011 11012 and [B] = 0011 10012 c. [A] =1001 00012 and [B] = 0101 11112
16.
Design a 4-bit carry look-ahead adder. Start by deriving the Boolean equation for Cout and the draw the complete circuit. What are the advantages and disadvantages of this circuit compared with ripple carry adder?
17.
What are the output of the decoder in figure 7 if the inputs are: (16) Vcc A0 A1 A2
(1) (2) (3)
0
1
1
2
2
4
3 4
(4)
5
E1 E2 E3
(5)
6
&
(6)
7
(15) (14) (13) (12) (11) (10)
a. b. c. d.
A0=0,A1=1,A2=1, A0=0,A0=1,A2=1, A0=1,A1=1,A2=1, A0=1,A1=0,A2=1,
E1 =0, E 2 =0 and E3 =0 E1 =0, E 2 =0 and E3 =1 E1 =0, E 2 =1 and E3 =1 E1 =0, E 2 =0 and E3 =0
(9) (7)
GND (8)
Figure 17 18.
Show how 4 units of ICs in figure 7 can be connected to perform as a 5 line-to-32 line decoder.
46
19.
What are the differences between a binary to BCD decoder with a 4 line-to-16 line decoder?
20.
Explain the „trailing zero suppression‟ and „leading zero suppression‟ configuration. When these two configurations are used?
21.
What are the advantages of using a priority encoder compared to a normal encoder?
22.
Fill in the truth table 1 for encoder in figure 22. D4
1
16
Vcc
D5
2
15
NC
D6
3
14
A3
D7
4
13
D3
D8
5
12
D2
A2
6
11
D1
A1
7
10
D9
8
9
A0
74LS147
D1
D2 D3 D4 D5 D6 D7 D8 D9 A3 A2 A1 A0
1 X X X X X X X X 0
1 X X X X X X X 0 1
Figure 22
1 X X X X X X 0 1 1
1 X X X X X 0 1 1 1
1 X X X X 0 1 1 1 1
1 X X X 0 1 1 1 1 1
1 X X 0 1 1 1 1 1 1
1 X 0 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1
23.
Explain the characteristic of pin labeled EI, EO and GS in IC 74148. Shows how two units of these ICs can be cascaded to perform as 16 line-to-4 line encoder.
24.
Show how 4 unit of 74LS151 (MUX) can be cascaded to perform as a 32 line-to-1 line MUX.
25.
Show how 74LS151 (MUX) can be used to implement this logic circuit.
Z ABCD 26.
Explain why in using 74138 ICs as a DEMUX, Data In is connected to the ACTIVE-LOW enabled input instead of the ACTIVE-HIGH enable input?
27.
Design a 2-bit magnitude relative detector that takes two 2-bit binary numbers; x1x0 and y1y0, and determines whether they are equal and if not, which one is larger. There are three outputs, defined as follows: M=1 only if the two input numbers are equal N=1 only if x1x0 is greater than y1y0 P=1 only if y1y0 is greater than x1x0 Start from truth table, then used Boolean theorem and/or karnaugh map to get the simplified Boolean expression before drawing the circuit.
47
28.
Show (in detail) how the circuit you design in question 27 can be used as a 4-bit magnitude relative detector starting from the truth table.
29.
Explain the design of BCD to binary code converter using your own understanding. Figure 2 (a) show the logic symbol of 74LS138, 1-to-8 decoder. Waveform A0, A1, A2 and E2 shown in Figure 2 (b) are applied to this decoder. Assume that E1 and E3 are tied to LOW (0). Draw the waveform for outputs O 0 , O 3 , O 6 and O 7 A0
0 A0 A1 A2
(1) (2) (3)
1
1
2
2
4
3 4
E1 E2 E3
(4) (5) (6)
5
&
6 7
(15) (14)
A1 A2
(13) (12)
E2
(11) (10) (9)
O0 O3
(7)
O6 O7
30.
Given the circuit diagram of Figure 3(a), complete the timing diagram of Figure 3(b) for QA, QB and QC.
48
31.
Show how 74LS151 (MUX) below can be used to perform the following Boolean expression. Y (A B C) (A B C) (A B C) (A B C)
32.
A decoder IC 74LS138 (3-to-8 decoder) shown in Figure Q3(d) can be used to implement combinational logic function. i) Implement GENAP circuit using this IC. GENAP circuit has four-bit binary inputs A (A3A2A1A0). It has one output Z that will be HIGH (1) when A is an even numbers. Show all steps. ii) What are the modifications necessary so that this circuit will produce a HIGH (1) output when the input is odd numbers?
33.
Show how a 4-bit parallel ripple carry adder (shown below) can be use to add three 1-bit binary numbers X, Y and Z, and produce 2bit output, SUM and CARRY. Label the circuit accordingly.
(10) (8) (3) (1) (11) (7) (4) (16) (13)
1 2 3
A 1
4
S
1 2 3
B
2 3 4
(9) (6) (2) (15)
4 Co
C4
(14)
49
34.
The 74LS148 is a 8 line-to-3 line encoder. This IC has eight active LOW input lines and three active LOW output line. It also has three other pin for expanding purposes:
Enable input, EI (input): must be LOW for the IC to function. Enable output, EO (output): LOW when EI=LOW and all input inactive. GS (output): LOW when EI=LOW and any input is active.
Complete the following truth table for this IC. EI D0 D1 D2 D3 D4 D5
1 0 0 1 0
35.
1 1 0 1 0
1 1 1 0 0
1 1 0 1 1
1 1 0 1 1
1 1 1 1 0
1 0 1 1 1
D6
D7
0 1 1 0 1
1 1 1 1 1
Show how a 3 line-to-8 line decoder (shown below) can be use to implement the following function. Label the circuit accordingly.
A2
A1
0 (1) (2) (3)
1
1
2
2
4
3 4
Z A B C A B B C
(4)
5
E1 E2 E3
36.
Show how a 8 line-to-1 line multiplexer (shown below) can be use to implement the following function. Label the circuit accordingly.
(5)
6
&
(6)
7
(4) I0
S0
I1
S1
I2
S2
(3) (2)
A0
(15) (14) (13) (12) (11) (10) (9) (7)
(11) (10) (9)
(1)
Z (A B C) (A B C) (A B C) (A B C)
I3 (15) (14) (13) (12)
I4
(5)
I5
(6)
Z Z
I6 I7
(7) EN
50
GS
EO
37.
Figure below shows the logic symbol of a 2-bit relative magnitude detector. Show how two unit of this circuit can be cascaded along with other logic gates to compare a 3-bit binary numbers X2X1X0 and Y2Y1Y0.
A0
B1
COMPARATOR
A1
B0
38.
M = 1, if A=B N = 1, if A>B P =1, if A
Figure 2 (a) show the logic symbol of 74LS138, 1-to-8 decoder. Waveform A0, A1, A2 and E3 shown in Figure 2 (b) are applied to this decoder. Assume that E1 and E 2 are tied to LOW (0). Draw the waveform for outputs O 0 , O 3 , O 6 and O 7
A0 0 A0 A1 A2
(1) (2) (3)
1
1
2
2
4
3 4
E1 E2 E3
(4) (5) (6)
5
&
6 7
(15) (14) (13) (12)
A1 A2
(11) (10)
E3
(9) (7)
O0 O3 O6 O7
51
39.
Figure 3 show the logic symbol of 74LS151, 8-to-1 line multiplexer. Show how it can be used to generate function Z A B C (A C) . Label completely. (4) (3) (2) (1) (15) (14) (13) (12) (7)
40.
I0
S0
I1
S1
I2
S2
(11) (10) (9)
I3 I4
(5)
I5
(6)
Z Z
I6 I7 EN
Show how one (1) unit of IC74LS151 can be use to implement the following function.
Z B ACD ACD
52
SUBJECT:
EXPERIMENT 6:
ELECTRICAL ENGINEERING LABORATORY BEE 2291 DIGITAL ELECTRONICS Building a Full-adder Logic Circuit (1) A
A
FA
FA
SUM
Cin
B
Co
Figure 2 PRELAB TASK
LAB TASK
1. By using Boolean theorem, show that a full-adder can be implemented by using two half-adder shown in Figure 2.
1. Construct 2 half adder circuit. 2. By using the two half adder you constructed, build the circuit in Figure 2 on the protoboard. 3. Connect the inputs (A, B and Cin) to the data switch and output (SUM and Co) to the LED. Make sure every IC is connected to +5V and ground properly. 4. Build a truth table based on the output of this circuit by using all the possible input combination.
EXPERIMENT 7:
Building a Full-adder Logic Circuit (2)
A
Cin
FA
SUM
Co
B Figure 3 PRELAB TASK
1. Build truth table for a full-adder with input A, B and Cin, and output SUM and Co. This will be the theoretical output. 2. Obtain the simplest Boolean expression for SUM and Co. Draw your circuit. 3. Re-draw your circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment).
53
LAB TASK
1. Construct the circuit on the protoboard. 2. Connect the inputs (A, B and Cin) to the data switch and output (SUM and Co) to the LED. Make sure every IC is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination and verify that the results are similar with the theoretical full-adder truth table. 4. Both circuit in experiment 6 and experiment 7 can perform as a full adder. In your opinion, which design is better? Justify your answer.
EXPERIMENT 8:
Using a 3 line-to-8 line Decoder as a Full Adder (16)
B Cin
(1) (2) (3)
1 2 4
+5V (4) (5)
0 1 2
74138
A
SELECT
Vcc
3 4 5 6
&
(6)
7
(15) (14) (13)
S
(12) (11) (10)
Cout
(9) (7)
GND (8)
Figure 1 PRELAB TASK
LAB TASK
1. By using any method you prefer, prove that a decoder with connection shown in figure 1 can be used as a full adder. Hint: refer to the decoder datasheet.
1. Construct this circuit on the protoboard. 2. Connect the inputs (A, B, and Cin) to the data switch and output (SUM and Cout) to the LED. Make sure every IC is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination. 4. Verify that the result correct. 5. In your opinion, what is the advantages of this circuit compared with the full adder circuit you built in experiment 4?
54
Using a Multiplexer for Implement Logic Function (4)
(2) (1)
(14) (13) (12)
S0
I1
S1
I2
S2
I3
(15)
(7)
Vcc
I0
(3)
74151
EXPERIMENT 9:
I4 I5
(11) (10) (9)
(5)
C B A
Z
(6)
I6 I7 EN
Figure 1 PRELAB TASK
1. By using any method you prefer, prove that a multiplexer with connection shown in figure 1 can be used to implement logic function below.
Z A B C
LAB TASK
1. Construct this circuit on the protoboard. 2. Connect the inputs (A, B, and C) to the data switch and output (Z) to the LED. Make sure every IC is connected to +5V and ground properly. 3. Build a truth table based on the output of this circuit by using all the possible input combination. 4. Verify that the result correct. 5. What necessary changes must be made if the circuit is now needed to implement the following function?
Z A B C EXPERIMENT 10:
Building a 1-digit BCD Adder BCD number A
Co
4-BIT PARALLEL BINARY ADDER
Carry to next BCD digit
BCD number B Illegal Code Checker
Correction Circuit
Result in valid BCD
Figure 1: Block Diagram of a BCD Adder
55
PRELAB TASK
1. In your own words, explain how the circuit operates based on Figure 4.15 (refer to teaching module). 2. Figure 4.15 shows a BCD adder circuit using 74LS283. This lab only has 74LS83. Modify this circuit so it can be implemented using 74LS83. Refer to datasheet or teaching module for the pin assignment.
LAB TASK
1. Construct the circuit on the protoboard. TIPS: you are advised to do this block by block. Start with adder block, and then add the checker and lastly the correction. You are encouraged to check each block output first before proceeding with adding another block. 2. Connect the inputs to the data switch and output to the LED. Make sure every IC is connected to +5V and ground properly. 3. Verify that the circuit is functioning correctly by performing five (5) BCD addition operations. 4. Based on this experiment, what are the disadvantages of using BCD code in a digital circuit compared with binary?
56
CHAPTER 5
LATCH & FLIP-FLOP
OUTLINE •
NAND LATCH
•
NOR LATCH
•
D LATCH
•
EDGE TRIGGERED SC FLIP-FLOP
•
EDGE TRIGGERED JK FLIP-FLOP
•
EDGE TRIGGERED D FLIP-FLOP
•
FLIP-FLOP CHARACTERISTIC
•
FLIP-FLOP APPLICTION
57
Up until this chapter, we‟ve been only discussing about logic circuit without any memory element. Without memory element, the logic circuit cannot „remember‟ the previous output state and because of this, the output will change (or re-evaluate) every time input changes. A logic circuit with memory element (temporary), are capable of storing (holding) it previous output level until the opposite input received. A logic gate itself is a non-memory element, but by interconnecting (and feedback) several gate, it can perform as memory circuit. Memory element device are a bistable multivibrator type device because it has two stable states, SET and RESET. Example of this kind of device is latch and flip-flops (FF). The difference between these two is the way they change their output (we will look at this later). 5.1 NAND LATCH A NAND latch is build from two NAND gate interconnected with the other. It has two input, SET(S) and CLEAR(C), and two output Q and Q (the inverted Q) Figure 5.1 NAND latch
REMEMBER S
Q
CLEAR (C) and RESET (R) can be use interchangeably.
Q
C
Now let‟s analyze this circuit. There are two inputs, so we have four possible input combinations. Notice that the outputs are feed back into the gate. Therefore we need to assume the initial value of Q for every possible input combination. That gives us a total of eight possible conditions. Case 1: S=1; C=1; Q=1 Figure 5.2 NAND latch: Case 1
S
1 1
0
C
1
Before
Q
S
1 1 0 1
Q
C
0
1
Q
Q
After
As we can see in figure 5.2, the output Q (after) is the same with Q (before).
58
Case 2: S=1; C=1; Q=0 Figure 5.3 NAND latch: Case 2
S
1 0
1
C
1
Q
S
1 0 1 0
Q
C
1
1
Before
Q
Q
After
As we can see in figure 5.3, the output Q (after) is the same with Q (before). Case 3: S=1; C=0; Q=0 Figure 5.4 NAND latch: Case 3
S
1 0
1
C
0
Q
S
1 0 1 0
Q
C
1
0
Before
Q
Q
After
As we can see in figure 5.4, the output Q (after) is the same with Q (before). Case 4: S=1; C=0; Q=1 Figure 5.5 NAND latch: Case 4
S
1 1
0
C
0
Before
Q
S
1 1
S
1 0 1
1
Q
Q
C
0
1
0
Q
C
1
0
After
As we can see in figure 5.5, the output Q (after) changes from 1 to 0.
59
Q
Q
Case 5: S=0; C=1; Q=0 Figure 5.6 NAND latch: Case 5
S
0 0
1
C
1
Q
S
0 0
S
0 1 1
0
Q
Q
C
1
1
1
Q
C
0
1
Before
Q
Q
After
As we can see in figure 5.6, the output Q (after) changes from 0 to 1. Case 6: S=0; C=1; Q=1 Figure 5.7 NAND latch: Case 6
S
0 1
0
C
1
Q
S
0 1 0 1
Q
C
0
1
Before
Q
Q
After
As we can see in figure 5.7, the output Q (after) is the same with Q (before). Case 7: S=0; C=0; Q=0 Figure 5.8 NAND latch: Case 7
S
0 0
1
C
0
Before
Q
S
0 0
S
0 1 1
0
Q
Q
C
0
1
1
Q
C
1
0
Q
Q
After
As we can see in figure 5.8, the output Q (after) changes from 0 to 1 but Q= Q . This output is not valid because the two outputs supposed to be the invert of each other.
60
Case 8: S=0; C=0; Q=1 Figure 5.9 NAND latch: Case 8
0
S
1
0
C
0
Q
S
0 1 1 1
Q
C
Before
1
0
Q
Q
After
As we can see in figure 5.9, the output Q (after) is the same but Q= Q . This output is not valid because the two outputs supposed to be the invert of each other. As a result, a complete analysis are summarize in table 5.10 Figure 5.10 Summarize analysis result of the NAND latch
Input S C 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Before Q Q 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
After Q Q 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 0
invalid invalid Q:01 Q:11 Q:00 Q:10 Q:00 Q:11
IGNORE SET CLEAR HOLD
To summarize the result, Figure 5.11 NAND latch truth table
Input S C 0 0 1 1
0 1 0 1
OUTPUT invalid SET CLEAR HOLD
From truth table in figure 5.11, it‟s clear that NAND latch uses active LOW input for S (to SET) and C (to clear). Therefore, the input S=C=0 should not be used because we are trying to SET and RESET at the same time. The logic symbol for this circuit are shown n figure 5.12 (notice the bubble at the input to indicates active LOW).
61
Figure 5.12 NAND latch
S
Q
FF C
Q
We also have learned in chapter 3 that NAND gate can be represented by a negative-OR (OR with bubble at both inputs) and this is shown in figure 5.13. Figure 5.13 NAND latch (alternate form)
S
Q
Q
C
1
1
1
Q
0
1
1
0
CLEAR
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
0
0
HOLD
C
1
CLEAR
1
HOLD
0
SET
1
HOLD
S
HOLD
Figure 5.14 Waveform for example 5.1
SET
Example 5.1 The waveforms in figure 5.14 are applied to a NAND latch. Assume that initially Q=0, determine the Q waveform.
One of the NAND latch common application is for de-bouncing circuit. In a mechanical switch, it‟s almost impossible to obtain a „clean‟ transition. This phenomenon is known as contact bounce.
62
Figure 5.15 Switching bounce (top) and debouncing using NAND latch.
+5V
Bouncing +5V
1
Vout
Switch comes to rest in position 2
0V
2 Switch to position 2
+5V
1
S
Q
Vout
+5V
FF
0V
C
2
Switch to position 2
+5V
5.2 NOR LATCH Just like a NAND latch, a NOR latch is build from two NOR gate interconnected with the other. It has two inputs, SET(S) and CLEAR(C), and two output Q and Q (the inverted Q). Figure 5.16 NOR latch
S
REMEMBER Note that the output Q and
Q
Q are at the opposite pin (compared to NAND latch) Q
C
Now let‟s analyze this circuit. There are two inputs, so we have four possible input combinations. Notice that the outputs are feed back into the gate. Therefore we need to assume the initial value of Q for every possible input combination. That gives us a total of eight possible conditions. Case 1: S=1; C=1; Q=1 Figure 5.17 NOR latch: Case 1
S
1 0
1
C
1
Before
Q
S
1 0 0 0
Q
C
0
1
Q
Q
After
As we can see in figure 5.17, this input combination is invalid because the output Q is the same with Q . Case 2: S=1; C=1; Q=0 63
Figure 5.18 NOR latch: Case 2
S
1 1
0
C
1
Q
S
1 1 0 1
Q
C
0
1
Q
1
S
0 0 0
Q
C
0
1
Before
Q
Q
After
As we can see in figure 5.18, this input combination is invalid because the output Q is the same with Q . Case 3: S=1; C=0; Q=0 Figure 5.19 NOR latch: Case 3
S
1 1
0
C
0
Q
Q
S
1 0 0
S
1 0 1
0
C
Q
0
0
Q
C
1
0
Before
After
As we can see in figure 5.19, the output Q changes from 0 to 1 Case 4: S=1; C=0; Q=1 Figure 5.20 NOR latch: Case 4
S
1 0
1
C
0
Q
S
1 0 1 0
Q
Before
C
1
0
Q
Q
After
As we can see in figure 5.20, the output Q remains as 1.
Case 5: S=0; C=1; Q=0
64
Q
Q
Figure 5.21 NOR latch: Case 5
S
0 1
0
C
1
Q
S
0 1 0 1
Q
C
0
1
Before
Q
Q
After
As we can see in figure 5.21, the output Q remains 0. Case 6: S=0; C=1; Q=1 Figure 5.22 NOR latch: Case 6
S
0 0
1
C
1
Q
S
0 0
S
0 1 0
0
Q
Q
C
0
1
1
Q
Before
C
0
1
After
As we can see in figure 5.22, the output Q changes from 1 to 0. Case 7: S=0; C=0; Q=0 Figure 5.23 NOR latch: Case 7
S
0 1
0
C
0
Q
S
0 1 0 1
Q
C
0
0
Before
Q
Q
After
As we can see in figure 5.23, the output Q remains the same. Case 8: S=0; C=0; Q=1 Figure 5.24 NAND latch: Case 6
S
0 0
1
C
0
Before
Q
S
0 0 1 0
Q
C
1
0
Q
Q
After
As we can see in figure 5.24, the output Q remains the same. As a result, a complete analysis are summarize in figure 5.25
65
Q
Q
Figure 5.25 Summarize analysis result of the NOR latch
Input S C 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Before Q Q 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
After Q Q 0 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0
Q:00 Q:11 Q:00 Q:10 Q:01 Q:11 invalid invalid
HOLD SET CLEAR IGNORE
To summarize the result, Figure 5.26 NOR latch truth table
Input S C 0 0 1 1
0 1 0 1
OUTPUT HOLD CLEAR SET invalid
From truth table in figure 5.26, it‟s clear that NOR latch uses active HIGH input for S (to SET) and C (to clear). Therefore, the input S=C=1 should not be used because we are trying to SET and RESET at the same time. The logic symbol for this circuit are shown n figure 5.27. Figure 5.27 NOR latch
S
Q
FF C
Q
We also have learned in chapter 3 that NOR gate can be represented by a negative-AND (ANDR with bubble at both inputs) and this is shown in figure 5.28. Figure 5.28 NOR latch (alternate form)
S
C
Q
Q
Example 5.2 The waveforms in figure 5.29 are applied to a NOR latch. Assume that
66
0
0
0
0
1
1
0
0
0
0
C
0
0
0
1
0
0
0
0
0
0
1
0
Q
0
1
1
0
0
0
1
1
1
1
0
0
CLEAR
CLEAR
HOLD
HOLD
1
SET
0
HOLD
S
HOLD
Figure 5.29 Waveform for example 5.2
SET
initially Q=0, determine the Q waveform.
An example application for a NOR latch is for a door alarm system shown in figure 5.30. The door is connected to a switch that connects the S input to the ground. When the door is open, the connection to ground are open, and the S input are pulled-up to Vcc (1). Thus, triggering the alarm. Alarm will continue to sound even when the door is closed again, until the reset switch is pressed (assuming the door is already closed). Figure 5.30 NOR latch in an alarm system
+5V
S
Q
+5V
C
Will open when door is open
5.3 D LATCH A D latch are also called a transparent latch because its ability to copy the D input to its output Q. It has two input, D and EN (enable), and two output, Q and Q . Figure 5.31 D latch
D Q EN Q
The D latch will copy the input D waveform when the EN input is HIGH 67
(1) and will hold the present Q value when EN is LOW (0). Figure 5.32 D latch truth table
Input D EN 0 1 X
1 1 0
OUTPUT Q Q 0 1 1 0 Q Q
Example 5.3 Determine the output Q of a D latch when waveform D and EN shown in figure 5.33 are applied. (Assume that initially Q=0). Figure 5.33 Waveform for example 5.3
D EN Q Q=D (tranparent)
HOLD (no change)
Q=D (tranparent)
5.4 EDGE TRIGGERED SC FLIP-FLOP (SC FF) The main difference between this and a latch is that the output level can only be change during the transition of the clock input. This transition may either be the positive-going-transition (PGT) or the negative-goingtransition (NGT) but not both. Figure 5.34 The PGT and NGT of clock signal.
CLOCK PGT
NGT
Therefore a SC FF has three input, SET (S), CLEAR (C) and CLOCK (CLK) and two output, Q and Q .
68
Figure 5.35 SC FF internal circuitry, PGT SC-FF symbol (bottom left) and NGT SCFF (bottom right)
S
Q
Edge detector circuit
CLK
Q
C
S
Q
S
CLK
Q
CLK
C
Q
C
Q
The truth table for an SC-FF is shown in figure 5.36. It can be seen that an edge triggered SC FF operate just like a NOR latch, but the transition only happens at clock transition. Figure 5.36 SC FF (PGT) truth table.
INPUT
OUTPUT
S
C
CLK
Q
0 0 1 1
0 1 0 1
↑ ↑ ↑ ↑
HOLD CLEAR SET INVALID
Let us examine when the same input waveform in figure 5.29 are applied to an edge triggered SC FF. Figure 5.35 SC FF (NGT) waveform.
S
0
1
0
0
0
0
1
1
0
0
0
0
C
0
0
0
1
0
0
0
0
0
0
1
0
CLK Q
0
1
1
0
SET
Q (NOR LATCH)
0
1
1
0
0
0
1
HOLD
CLEAR
0
0
0
1
1
1
1
1
HOLD
SET
1
1
1
0
HOLD
0
69
Figure 5.36 SC FF (PGT) waveform.
S
0
1
0
0
0
0
1
1
0
0
0
0
C
0
0
0
1
0
0
0
0
0
0
1
0
CLK Q
0
0
0
0
1
0
HOLD
HOLD
Q (NOR LATCH)
0
1
0
0
1
HOLD
0
0
1
1
1
0
HOLD
SET
1
1
1
1
0
CLEAR
0
0
It can be seen that the output level transition appear to be delayed (because it can only change at clock transition).
Method for edge triggering The simplest method of edge triggering is by using a NOT gate and a AND gate. Remember that in practice, all gates will introduce a delay to the output. This principle is used in this edge triggering circuit. Figure 5.37 PGT edge detection circuit (left) and NGT edge detection circuit (right).
Edge detection circuit (PGT)
a
clock
Edge detection circuit (NGT)
c
a
clock
b Delayed due to inverter
b Delayed due to inverter
a b c
c
Spike produced
a Spike produced
b c
70
5.5 EDGE TRIGGERED JK FLIP-FLOP (JK FF) One of the shortcomings of an edge-triggered SC FF is the existence invalid input combination. This can be overcome by using an edgetriggered JK FF. Figure 5.38 JK FF internal circuitry, PGT JK-FF symbol (bottom left) and NGT JKFF (bottom right)
J
Q
Edge detector circuit
CLK
Q
K
J
Q
J
CLK
Q
CLK
K
Q
K
Q
When inputs of JK FF are both high when it is triggered, it will invert the previous output state (Q). This condition is called „toggle‟. Figure 5.39 JK FF (PGT) truth table.
INPUT
OUTPUT
S
C
CLK
Q
0 0 1 1
0 1 0 1
↑ ↑ ↑ ↑
HOLD CLEAR SET TOGGLE
Let us examine when input waveform in figure 5.40 are applied to an edge triggered JK FF. Figure 5.40 JK FF (NGT) waveform.
J
0
1
0
0
0
0
1
1
1
1
0
0
K
0
0
0
1
1
0
0
1
1
1
1
0
CLK Q
0
1
1
SET
0
0
CLEAR
0
0
HOLD
1
1
0
0
TOGGLE TOGGLE
0
CLEAR
71
Figure 5.41 JK FF (PGT) waveform.
J
0
1
1
1
0
0
1
1
1
1
0
0
K
0
0
0
1
1
0
0
1
1
1
1
0
CLK Q
0
1
1
HOLD
0
0
0
CLEAR
SET
0
1
SET
1
0
TOGGLE
0
0
CLEAR
Asynchronous Preset and Clear Input. For any edge-triggered FF, the inputs (besides the clock) are called synchronous input. This is because the output can only change state when a clock transition occurs. Most FF in IC form also has a asynchronous input labeled preset (PRE) and clear (CLR) that can affect the state of the FF regardless of the clock. These two inputs are both active-low (indicated by bubbles). Low input at PRE will set the FF output to HIGH (1) and low input at CLR will reset the FF output to LOW (0). Figure 5.42 JK FF (with asynchronous input) internal circuitry, PGT JK-FF symbol (bottom left) and NGT JKFF (bottom right)
PRE J CLK
Q
Edge detector circuit
Q
K CLR PRE
J
PRE
Q
CLK
J
Q
CLK
K
Q CLR
K
Q CLR
When a asynchronous input are applied, it will immediately affect the state of the output regardless of the clock signal. While a asynchronous input is active, the FF will ignore all the other synchronous inputs until it become un-active again. In other word, asynchronous inputs have higher priority than synchronous input.
72
Figure 5.43 JK FF (PGT) with asynchronous inputs waveform.
CLK J K PRE CLR
TOGGLE
SET
TOGGLE
CLR
HOLD
TOGGLE
SET
HOLD
TOGGLE
PRE
TOGGLE
HOLD
PRE
HOLD
Q
The 74112: Dual J-K Flip-Flop with Preset and Clear. Figure 5.44 Dual J-K FlipFlop with Preset and Clear pin diagram (left) and logic symbol (right)
Vcc
CLK 1
1
16
K1
2
15
J1
3
14
PRE 1
Vcc CLR 1 CLR 2
(16)
(4) (3)
(5)
PRE
J
Q
K
Q
(1) (2)
4
13
CLK 2
(15)
Q1
5
12
K2
(10)
Q1
6
11
J2
(11)
Q2
7
10
PRE 2
(13)
GND
8
9
Q2
(12) (14)
(6)
CLR
(9)
PRE
J
Q
K
Q
(7)
CLR
(8) Gnd
73
5.6 EDGE TRIGGERED D FLIP-FLOP (D FF) An edge triggered D FF only has one input, D (D=data) and clock for edge triggering. When triggered, value of D will be transferred to output (Q). This is useful for synchronizing especially in storing data (we can control when data are to be stored). Figure 5.45 Edge triggered D-FF (PGT) truth table
OUTPUT S
CLK
Q
0 1
↑ ↑
0 1
An edge triggered J-K FF or an edge triggered SC FF can be used to perform as D FF as shown in figure 5.45. Figure 5.46 Edge triggered D-FF (PGT)
D
Q
CLK
D
S
Q
CLK
D
J
Q
K
Q
CLK
Q
C
Q
Waveform D1 and D2 in figure 5.47 are applied to two different PGT edge triggering D FF. Assuming initially Q=0, sketch Q1and Q2. Figure 5.47 Edge triggered D FF waveform response
CLK
D1
0
1
1
0
1
1
0
0
1
1
0
D2
0
1
0
0
1
1
0
0
1
1
0
Q1
0
1
1
0
1
1
0
0
1
1
0
Q2
0
1
0
0
1
1
0
0
1
1
0
From figure 5.47, it can be seen that data that pass through a D FF a resynchronize by the clock input. This is important in data transmission where data pulses are delayed, (or stretch) need to be re-synchronized. The limitation is that the stretch pulse must not exceed one clock pulse.
74
5.7 FLIP-FLOP CHARACTERISTICS Every FF has different characteristic depending on the type and technology. These characteristic are stated in the device datasheet. Propagation delay This is the time interval between the time when input are applied to the time when output changes. It can be categorized into four types: 1. tPLH : time measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output. 2. tPHL : time measured from the triggering edge of the clock pulse to the HIGH-to-LOW transition of the output. Figure 5.48 Propagation delay: tPLH (left) and tPHL (right)
50% of triggering edge
50% of triggering edge
CLK
CLK
Q
Q
50% of the HIGH to LOW transition of Q
50% of the LOW to HIGH transition of Q
tPHL
tPLH
3. tPLH : time measured from the leading edge of the PRESET input to the LOW-to-HIGH transition of the output. 4. tPHL : time measured from the leading edge of the RESET input to the HIGH-to-LOW transition of the output. Figure 5.49 Propagation delay: tPLH for PRESET (left) and tPHL for RESET (right)
50% of leading edge
50% of the leading edge
PRE
CLR
Q
Q
50% of the HIGH to LOW transition of Q
50% of the LOW to HIGH transition of Q
tPLH
tPHL
Pulse Widths Minimum pulse width for the inputs and clock. Typically the clock is specified by the minimum HIGH time and its minimum LOW time. 75
Set-up Time (ts) Minimum time for the input to be at a constant level (ready) before the triggering occurs. Figure 5.50 Set-up time: tS for HIGH input (left) and tS for LOW input (right)
50% of the HIGH to LOW transition of D
50% of the LOW to HIGH transition of D
D
D
CLK
CLK 50% of triggering edge
50% of triggering edge
Set-up time (ts)
Set-up time (ts)
Hold Time (th) Minimum time needed for an input signal to remain at constant level (hold) after the triggering edge before it can change it states. Figure 5.51 Hold time
50% of the HIGH to LOW transition of D
D
CLK 50% of triggering edge
Hold time (th)
Maximum Clock Frequency (fmax) Maximum frequency for the clock to ensure a reliable FF operation. Power Dissipation (P) The power consumption for device. Calculated by using the formula below:
P VCC I CC
When building a circuit, make sure the power supply is capable to deliver enough power.
For a circuit that uses ten FF with each dissipated 20mW, the total power needed are 0.2W (20mW X 10). If each FF operates on +5V (dc), the amount of current needed are 40mA.
76
5.8 FLIP-FLOP APPLICATION We have look at several type of flip-flop. Now we will take a look at its application. A single FF cannot do much, but when several FF are connected together and with some other logic gates, it can be used for many applications. Frequency Divider A frequency divider circuit will divide the clock with 2 for every stage. A JK FF with its J and K input connected to HIGH (so it will always in toggle mode) is required for each stage. Figure 5.52 shows a 4 stage frequency divider. Figure 5.52 A 4 stage frequency divider and waveform (bottom)
1 J
Q
J
Q
J
Q
J
Q
CLK
K
K QA
K QB
K QC
QD
CLK QA QB QC QD
It can be seen from the waveform for each stage, the frequency are halves. If the clock frequency are 10Hz:
QA=10/2=5Hz QB=10/4=2.5Hz QC=10/8=1.25Hz QD=10/16=0.625Hz
77
Asynchronous Counter A counter function is to count (in binary) from decimal 0 to decimal number N-1 (where N is the MOD of the counter). Asynchronous don‟t have a common clock signal and because of output from one FF are feed into another FF, the signal is called rippled. Thus, asynchronous counter are also called ripple counter. Figure 5.53 shows a MOD-16 counter. Figure 5.53 MOD -16 counter and waveform (bottom)
1 J
Q
J
Q
J
Q
J
Q
CLK
K
K
K
QA
K
QB
QC
QD
CLK QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
QD (MSB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
DEC
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 0
1
2
3
4
5
6
7
From figure 5.53, it can be seen that a MOD-16 counter counts from 00002 (010) till 11112 (1510). It also consists of 4 JK FF (because counting to 11112 (1510) require at least 4-bit with all the J and K input connected to HIGH (JK FF always in toggle mode). The rule for determining the minimum number of JK FF required is:
MODnumber 2 n
(where n number of JK FF)
Therefore a MOD-8 will required three JK FF while a MOD-32 will required five JK FF. We will look more on counter in the next chapter.
78
ONE-SHOT A one-shot device (a.k.a. monostable multivibrator) has only one stable state. It will always be in it stable state and when triggered, move to its unstable state and remains for a determine time before returning to its stable state. The time its stays in the unstable state determine the pulse width. Figure 5.54 Basic OneShot Device
+5V
Trigger
Q
A basic one-shot device consists of logic gates and inverter (shown in figure 5.54). This device stable state is Q=LOW (0). When triggered: 1. Output of NOR will become LOW (0) 2. Output of INVERTER will become HIGH (0), Q=HIGH (1) 3. Because Q= HIGH (1), output of NOR will stay LOW (0), although triggering has stop. 4. Capacitor will be charge until certain level before the INVERTER will interpret it as HIGH (0) and the output becomes LOW (0), Q = LOW (0) and NOR output become HIGH (1). It will stay low until another triggering occurs. The time for the device to stays in its unstable state are determine by the capacitor and resistor value (RC time constant).
79
SUBJECT:
EXPERIMENT 11:
PRELAB TASK
LAB TASK
ELECTRICAL ENGINEERING LABORATORY BEE 2291 DIGITAL ELECTRONICS NAND LATCH
1. Draw a NAND latch circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 1. 1. Construct the circuit 1 on the protoboard. 2. Connect the inputs (SET and RESET) to the data switch and two outputs to the LED. Make sure every IC is connected to +5V and ground properly. 3. Verify that the latch operates correctly. 4. Write a short comment on the „illegal input‟ condition.
EXPERIMENT 12:
PRELAB TASK
LAB TASK
NOR LATCH
1. Draw a NOR latch circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 2. 1. Construct circuit 2 on the protoboard. 2. Connect the inputs (SET and RESET) to the data switch and two outputs to the LED. Make sure every IC is connected to +5V and ground properly. 3. Verify that the latch is operating correctly. 4. Write a short comment on the „illegal input‟ condition.
EXPERIMENT 13:
PRELAB TASK
LAB TASK
D LATCH
1. Draw a D latch circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 3. 1. Construct circuit 3 on the protoboard. 2. Connect the inputs (D and EN) to the data switch and two outputs to the LED. Make sure every IC is connected to +5V and ground properly. 3. Verify that the latch is operating correctly. 4. Comment on what happen during the „transparent‟ states.
80
EXPERIMENT 14:
PRELAB TASK
LAB TASK
EDGE TRIGGERED SC FLIP FLOP
1. Draw a SC Flip-flop circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 4. 1. Construct circuit 4 on the protoboard. 2. Connect the inputs (S and C) to the data switch and CLK input to pulse generator and two outputs to the LED. Make sure every IC is connected to +5V and ground properly. 3. Verify that the circuit is functioning correctly. 4. Write a short discussion on the difference in term of output transition of this circuit compared to NOR latch.
EXPERIMENT 15:
PRELAB TASK
EDGE TRIGGERED JK FLIP FLOP
1. Study the operation of IC74LS76 (refer to datasheet). 2. In your own words, write a short explanation about the asynchronous input of this IC (the
LAB TASK
PRE and CLR input).
1. Construct the circuit on the protoboard. 2. Connect the inputs (J, K, PRE and CLR ) to the data switch, and CLK input to pulse generator and two outputs to the LED. 3. Make sure every IC is connected to +5V and ground properly. 4. Write a short discussion on the advantages of using JK flip-flop compared with SC flip-flop.
EXPERIMENT 16:
D LATCH
PRELAB TASK
1. Show (in drawings) how a JK flip-flop can be modified to operate as D flip-flop. 2. Re-draw this circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment).
LAB TASK
1. Connect the inputs, D the data switch, and CLK input to pulse generator and two outputs to the LED. 2. Make sure every IC is connected to +5V and ground properly. 3. Verify that the IC‟s is functioning correctly. 4. Write a short discussion on the difference between D latch and D flip-flop.
81
CHAPTER 6
COUNTER AND REGISTER
OUTLINE •
ASYNCHRONOUS COUNTER
•
SYNCHRONOUS COUNTER
•
STATE MACHINE
•
SERIAL IN / SERIAL OUT SHIFT REGISTER
•
SERIAL IN / PARALLEL OUT SHIFT REGISTER
•
PARALLEL IN / SERIAL OUT SHIFT REGISTER
•
PARALLEL IN / PARALLEL OUT SHIFT REGISTER
82
In chapter 5, we have discussed about the basic of counter. In this chapter, we will go into the detail of counter, the types and IC available. 6.1 ASYNCHRONOUS COUNTER In the previous chapter, the counters we‟ve been discussing are only in block diagram level. Now we are going to design and build a counter using an IC.
Design and Implementation of MOD-8 Counter using 74112 For a MOD-8 counter, three JK FF are required. The block diagram and expected waveform are shown in figure 6.1 Figure 6.1 MOD-8 Counter
1 J
Q
J
Q
J
Q
REMEMBER
CLK
K
K
J=K=1 for toggle operation
K
QA
QB
QC
CLK QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
QC (MSB)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DEC
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Therefore, the implementation using 74112 will require two unit of this IC (because we need three JK FF while 74112 only contain 2 JK FF).
83
Figure 6.2 Implementing a MOD-8 counter using 74112
1 (4) (3) CLK
(4) PRE
J
Q
(1) (2)
K
Q
(5)
(3)
QA
(1)
(6)
CLR
(15)
Q
(5)
(6)
CLR
(10) PRE
J
Q
(13) (12)
Q
K
(15)
(10) (11)
(2)
PRE
J
K
Q
(9)
QB (7)
(11)
PRE
J
(12)
K
CLR
(14)
Q
(9)
QC
(13) Q
REMEMBER J=K=1 for toggle operation PRE=CLR=1 for synchronous operation
(7)
CLR
Implementation of MOD-16 Counter using 74112 Figure 6.3 MOD -16 counter
1 (4) (3) CLK
(4) PRE
J
Q
(1) (2)
K
Q
(5)
(3)
QA
(1)
(6)
(2)
CLR
(15)
K
Q
(5)
QD (6)
CLR
(10) (9)
(11)
(13)
QB
(13)
(12)
(7)
(12)
(14)
Q
(15)
(10) (11)
PRE
J
PRE
J
Q
K
Q CLR
(14)
PRE
J
Q
K
Q
(9)
QC
REMEMBER J=K=1 for toggle operation PRE=CLR=1 for synchronous operation
(7)
CLR
Implementation of MOD-10 Counter Up till now, we‟ve only discussing about counter with MOD number 2n (e.g. MOD-8, MOD 16). To build a counter with MOD number other than 2n, other logic gates are needed for resetting the counter to 0. Let‟s take a MOD-10 counter as an example. Step 1: Determining amount of JK FF needed. For a MOD-10 counter, we need 4 unit of JK FF (because 1010=10102, that means 4-bit). Step 2: Determining the ‘reset’ logic A 4 JK FF counter is in essence a MOD-16 counter. To make it into a MOD-10 counter, it needs to be reset, after it reaches 10012 (910). In other words, when the output is 10102 (1010), it will immediately 84
reset/clear all the JK FF by sending a low signal to the CLR input. This is done by using a NAND gate with the input connected to QD and QB (because 10102 mean that QD and QB are equal to HIGH while QC and QA are equal to LOW). Step 3: Drawing the block diagram Figure 6.4 Block diagram of a MOD-10 counter
1 PRE
J
PRE
Q
J
PRE
Q
J
PRE
Q
J
Q
CLK
K
K CLR
K CLR
K CLR
QA
CLR
QB
QC
QD
CLK QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QB
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
QC
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
QD (MSB)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
DEC
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
Glitch
Glitch
Although output 10102 (1010) appeared (suppose to be until 10012 (910)), this output only last for a fraction of a second before it will reset the counter and are hardly noticeable. It will only appear as a glitch rather than a pulse.
Step 4: Circuit implementation 1 (4) (3) CLK
(4) PRE
J
Q
(1) (2)
K
Q
(5)
(3)
QA
(1)
(6)
CLR
(15)
(14)
Q
(5)
QD (6)
CLR
(10) PRE
J
Q
(13) (12)
Q
K
(15)
(10) (11)
(2)
PRE
J
K
Q CLR
(9)
(11)
QB
(13)
(7)
(12) (14)
PRE
J
Q
K
Q
(9)
QC (7)
CLR
85
The 74LS293: Decade Counter,4-bit Binary Counter It can be seen that it‟s quite tedious to use 74112 IC for counter implementation. As a better option, we have 4-bit binary counter IC (74LS293). This decade counter is divided into two part, divide by eight and divide by two. It is triggered by using NGT edge of clock pulse. Figure 5.58 IC 74LS293: Decade Counter,4-bit Binary Counter pin diagram (left), logic symbol (right) and internal circuitry (bottom).
Vcc (14)
NC
1
14
Vcc
NC
2
13
MR2
(10)
NC
3
12
MR1
(11)
Q2
4
11
CP1
Q1
5
10
CP0
NC
6
9
Q0
7
8
Q3
GND
74LS293
(12) (13)
CP0
Q4
CP1
Q2 Q1
MR1 MR2
Q0
&
(8) (4) (5) (9)
(8) Gnd
1 PRE
PRE
J
Q
J
PRE
Q
J
PRE
Q
J
Q
CP0
K
K CLR
K CLR
K CLR
CLR
CP1 MR1 MR2
Q0
Q1
Q2
Q3
Note that the output of Q0 is not „hardwired‟ to the clock input of the next JK FF. Therefore it needs to be connected externally. The purpose is to add flexibility for this IC. The MR (master reset) is used for counter with MOD number not equal to 2n (will reset all the JK FF when both are input are HIGH). Figure 6.5 MOD-10 counter using 74LS293
CLK
(10) (11)
(12) (13)
CP0
Q4 Q2
CP1
Q1 MR1 MR2
&
Q0
(8) (4) (5) (9)
QD(MSB) QC QB
A MOD-10 counter is also known as decade counter
QA
86
Figure 6.6 MOD-11 counter using 74LS293
(10)
CLK
CP0
(11)
MR1
CP0
(11)
CLK
(9)
Q0
&
MR2
(10)
NC
(5)
Q1
(12)
Q2
MR1
(13)
MR2
QB
Because there only two MR‟s, an external AND gate are used because 1110 (10112).
QA
QD(MSB)
(5)
Q0
&
REMEMBER
(4)
Q1
(12)
QC
(8)
Q4
CP1
QD(MSB)
(4)
Q2
CP1
(13)
Figure 6.7 MOD-6 counter using 74LS293
(8)
Q4
(9)
QC
REMEMBER
QB
Because MOD-6 only requires 3 JK FF (3-bit), the 1‟st JK FF is not connected.
QA NOT USED
So we have look at few types of counter. But the entire counter we‟ve seen so far is a count-up type. For a count-down type counter, the connection is shown below. Figure 6.8 MOD-8 Down Counter (right) and waveform (below).
1 J
QA
J
QB
J
QC
K
Q
K
Q
K
Q
Notice how the clock connection differs from a count-up counter.
CLK
CLK QA
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
QB
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
QC (MSB)
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
0
DEC
Figure 6.9 MOD-16 Down counter
1 J
QA
J
QB
J
QC
J
QD
K
Q
K
Q
K
Q
K
Q
CLK
87
6.2 SYNCHRONOUS COUNTER The problem with asynchronous counter is that because the signal are rippled from one FF to another, the delay for each FF are accumulated (remember the case of a ripple carry adder). This problem can be overcome by using synchronous counter (a.k.a. parallel counter). Unlike asynchronous counter, synchronous counter has a common clock signal. Thus, all the changes at the output happen at the same time for the entire FF.
Figure 6.10 MOD-16 counter counting steps
Therefore, we cannot set both J and K to HIGH (like an asynchronous counter) but we need to control which FF will toggle at which specific time. To do this lets examine the counting steps. COUNT QD QC QB QA (LSB) (MSB) 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 From the table, it can be seen that: 1. QA (LSB) will toggle at every triggering edge. Thus J1=K1=1 2. QB will toggle at every triggering edge when QA=1. Thus J2=K2=QA 3. QC will toggle at every triggering edge when both QA and QB are HIGH (1). Thus, J3 K3 Q A Q B 4. QD (MSB) will toggle at every triggering edge when both Q A and QB and QC are HIGH (1). Thus, J4 K4 Q A Q B Q C
88
Because of the AND operation, it‟s obvious that these counter requires extra circuitry and the final circuit are shown in figure 6.11. Figure 6.11 MOD-16 synchronous counter
1 J1
J2
Q
J3
Q
K2
K1
J4
Q
K3
Q
K4
CLK
QA
QB
QC
QD
For a synchronous counter with MOD number not equal with 2 n, we will use the CLR input to reset the counter (same as the asynchronous counter).
Figure 6.12 MOD-10 (decade) synchronous counter
1 J1 K1
J2
Q
J3
Q
K2 CLR
J4
Q
K3 CLR
Q
K4 CLR
CLR
CLK
QA
QB
QC
QD
Presetable Synchronous Counter A pressetable counter allows user to preset (load) the start of the counting sequence. There are two type of preset, asynchronous and synchronous. This operation (preset) is also referred a parallel loading. Figure 6.13 shows a 4-bit presettable asynchronous counter.
89
Figure 6.13 4-bit Presetable Synchronous Counter
P0
P1
P2
P3
1 J1
PRE
Q
J2
PRE
Q
J3
K2
K1 CLR
PRE
Q
J4
K3 CLR
PRE
Q
K4 CLR
CLR
CLK
PE (Parallel load)
QA
QB
QC
QD
From figure 5.66, a presetable synchronous counter has a 4-bit parallel data input (P0 to P3). Notice that these inputs are connected to a NAND gate. This NAND gate acts like an enable or disable gate. Inputs from parallel data input are enabled only when the other input (PE) is LOW and these input value will be „stored‟ in the counter (each JK FF will stored 1 bit). Because of these JK FF uses asynchronous PRE and CLR, the synchronous input (CLK) are ignored until PE goes back to HIGH. Only then the counting will start. The 74LS163: Synchronous 4-bit Counter A part from being a synchronous counter, this IC also allows parallel enable feature. This feature enables the IC to be loads with value to start the counting (load). Thus, it is called a presetable (because can be preset) synchronous counter. Note that this IC triggers on PGT. Figure 6.14 74LS163 : Synchronous 4-bit Counter with Parallel Load
Vcc (16) SR CP
1
16
2
15
P0
3
14
P1
4
13
74LS293
Vcc TC Q0 Q1
P2
5
12
Q2
P3
6
11
Q3
CE P
7
10
CET
GND
8
9
PE
(9) (3) (4) (5) (6) (2)
PE
Q3
P0
Q2
P1
Q1
P2
Q0
P3
(11) (12) (13) (14)
CP
(7)
CE P (10) CET (1) SR
TC
(15)
(8) Gnd
90
Synchronous Down/Up Counter In previous chapter (asynchronous counter), we saw that an up counter can be modified to a down counter by changing the clock input of the next FF to the inverted output. To design an up/down counter (which we can choose by a control line), we will use an AND gate to function as an enable/disable gate. Figure 6.15 shows a 3-bit up/down synchronous counter. It will count down when control is HIGH (1) (gate 2 and 4 will be enabled) and up when control is LOW (0) (gate 1 and 3 will be enabled). Figure 6.15 MOD-8 synchronous up/down counter
1
J1
QA
1
J2
QB
3
J1
QC
K1
QA
2
K2
QB
4
K1
QC
UP/ DOWN CLK
The 74LS191: Presetable 4-bit Up/Down Synchronous Counter This IC offers two mode of operation, count up or count down depending on the U/D input. If U/D is HIGH (1), it will count down and if U/D is LOW (0), it will count up. CE (count enable) must also be low to enable this IC. Just like 74LS163, this IC also offer parallel load feature for presetting this counter. Figure 6.16 74LS191: Presetable 4-bit Up/Down Synchronous Counter pin diagram (left) and logic symbol (right)
Vcc (16) P1
1
16
Vcc
Q1
2
15
P0
Q0
3
14
CE
4
13
74LS293
CP RC
5
12
TC
6
11
PL
Q3
7
10
GND
8
9
U/D Q2
P2 P3
(11) (15) (1) (10) (9) (14) (5) (4) (13)
PL
Q3
P0
Q2
P1
Q1
P2
Q0
P3
(7) (6) (2) (3)
CP U/D
TC
(15)
CE RC (8) Gnd
91
5.3 STATE MACHINE State machine can be view as a synchronous counter with „irregular‟ sequence unlike a normal counter. State machine are also called a sequential circuit. In general, a state machine can be divided into two type:
Moore machine: the next state (output) depends only on the present internal state.
Mealy machine: the next state (output) depends on the present internal state and input at that time.
Designing a state machine follows steps below (you may skip certain steps depending on the task): 1. State diagram: Diagram that shows all the transition of states when clock are triggered. Amount of FF needed are also determine depending on the bit. 2. Next state table: Table that listed all the present state along with its next state. 3. Excitation table: Listed all the J and K connection for all FF for the transition in next state table to occur. This is done by following the JK FF transition table. Figure 6.17 JK FF transition table
Output Transition Qn Qn+1 0 → 0 0 → 1 1 → 0 1 → 1
FF Inputs J K 0 X 1 X X 1 X 0
4. K-map: To determine the simplified logic expression for all the J and K input. 5. Circuit implementation: Draw the complete circuit.
92
Moore Machine Task 1: Design a 3-bit Gray code up counter. Step 1: State diagram Figure 6.18 State diagram of a count up Gray code counter
000
001
100
011
101
010
111
You may want to do some revision on Gray code first before going into this section.
110
Because this is a 3-bit state machine, three JK FF are required. Note that JK FF C is the MSB. Figure 6.19 MOD-8 synchronous up/down counter
JA
QA
FF A KA
QA
JB
QB
FF B KB
QB
JC
QC
FF C KC
QC
Step 2: Next state table Present State QC QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Next State QC QB QA 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 1
It is advisable to arrange the table based on the present state in incremental binary counting order.
93
Step 3: Excitation table Present State QC QB Q A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Next State QC QB Q A 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 1 0 1
FF C JC KC 0 X 0 X 1 X 0 X X 1 X 0 X 0 X 0
FF B JB KB 0 X 1 X X 0 X 0 0 X 0 X X 0 X 1
FF A J A KA 1 X X 0 0 X X 1 0 X X 1 1 X X 0
Step 4: K-map (We need 6 K-map, two for each JK FF). FF C K input
J input QA
0
1
00
0
0
01
1
0
11
x
x
10
x
x
QC∙QB
QB QA QB QA
QA
0
1
00
x
x
01
x
x
11
0
0
10
1
0
QC∙QB
JC QB QA K C QB QA
FF B K input
J input QA
QA
0
1
00
x
x
x
01
0
0
x
x
11
0
1
0
0
10
x
x
0
1
00
0
1
01
x
11 10
QC∙QB
QC∙QB
QC QA
QC QA
J B QC QA
K B QC QA
94
FF A K input
J input QA
0
1
00
1
x
01
0
x
11
1
x
10
0
x
QC∙QB
QC QB QC QB
QA
0
1
00
x
0
01
x
1
11
x
0
10
x
1
QC∙QB
QC QB
J A QC QB
K A QC QB
QC QB
Step 5: Circuit implementation Figure 6.20 Gray code up counter JA
QA
JB
FF A KA
QB
FF B
QA
KB
QB
JC
QC
FF C KC
QC
CLK
Task 2: Design a 3-bit Moore state machine with state diagram shown in figure 6.21. Figure 6.21 State diagram for task 2
110 000
100
011
101
001
010
111
95
Step 2: Next state table Present State QC QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Next State QC QB QA 1 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0
Step 3: Excitation table PRESENT STATE QC QB QA 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
NEXT STATE Q C QB Q A 1 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0
FF C JC KC 1 X 0 X 0 X 0 X X 0 X 1 X 1 X 1
FF B JB KB 0 X 1 X X 1 X 1 0 X 1 X X 1 X 0
FF A J A KA 0 X X 0 1 X X 1 1 X X 1 0 X X 1
Step 4: K-map (We need 6 K-map, two for each JK FF). FF C K input
J input QA
0
1
00
1
0
01
0
0
11
x
x
10
x
x
QC∙QB
QB QA
QB
QA
0
1
00
x
x
01
x
x
11
1
1
10
0
1
QC∙QB
JC QB QA
K C QB QA
QA
96
FF B K input
J input QA
0
1
00
0
1
01
x
x
11
x
x
10
0
1
QC∙QB
QA QA
QA
0
1
00
x
x
01
1
1
11
1
0
10
x
x
QC∙QB
J B QA QC
K B QC Q A
FF A K input
J input QA
0
1
00
0
x
01
1
x
11
0
x
10
1
x
QC∙QB
Q C Q B
QC QB
QB
QA
0
1
00
x
0
01
x
1
11
x
1
10
x
1
QC∙QB
J A QC QB K A QB QC
QC
Step 5: Circuit implementation Figure 6.20 Gray code up counter JA
QA
FF A KA
QA
JB
QB
FF B KB
QB
JC
QC
FF C KC
QC
CLK
97
Mealy Machine Because of a Mealy machine output(s) also depend on the present input(s); the input will be treated just like another state variable. Task: Design an up/down Gray code counter. If input Y is LOW (0), it will count down, and if Y is HIGH (1), it will count up.
Figure 6.21 State diagram for task 3
Y=1
000 Y=1
001 Y=0
Y=0
Y=1 Y=0
100 Y=1
011
Y=0
Y=0
101
010 Y=0
Y=1
Y=1
Y=0 Y=0
111
110
Y=1
Y=1
Step 2: Next State Table PRESENT NEXT STATE NEXT STATE STATE (Y=0) (Y=1) QC QB QA QC QB QA QC QB QA 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 1
98
Step 4: K-map FF C J input QA∙Y 00 01 QC∙QB
11
10
K input QA∙Y 00 01 QC∙QB
11
10
00
1
0
0
0
00
x
x
x
x
01
0
1
0
0
01
x
x
x
x
11
x
x
x
x
11
1
0
x
0
10
x
x
x
x
10
0
1
0
0
K input QA∙Y 00 01 QC∙QB
11
10
J C Q A (Q B Y ) K C Q A (Q B Y)
FF B J input QA∙Y 00 01 QC∙QB
11
10
00
0
0
1
0
00
x
x
x
x
01
x
x
x
x
01
0
0
0
1
11
x
x
x
x
11
0
0
1
0
10
0
0
0
1
10
x
x
x
x
J B Q A (Q C Y )
K C Q A (Q C Y )
FF A J input QA∙Y 00 01 QC∙QB
11
10
K input QA∙Y 00 01 QC∙QB
11
10
00
0
1
x
x
00
x
x
0
1
01
1
0
x
x
01
x
x
1
0
11
0
1
x
x
11
x
x
0
1
10
1
0
0
x
10
x
x
1
0
J A QC Q B Y K A QC Q B Y
99
Figure 6.22 Circuit For task 3
Y QA QA QB QC
JC
QC
FF C KC
QC
JB
QB
FF B KB
QB
JA
QA
FF A KA
QA
5.4 SERIAL IN / SERIAL OUT SHIFT REGISTER (SISO) This register takes in serial data; shift it, the output data in serial format. The shift operation may be a shift right, left or both (depending on the design). Figure 6.23 Basic Data Movement of a Shift Right SISO (above) and Shift Left SISO (below)
Data in
Data out
Data out
A register in a microcomputer has capabilities to do both type of shifting.
Data in
A basic 4-bit SISO register (right shift) comprises of four PGT edgetriggered D FF. Data from input will move from input of the FF to the input of the next one at every PGT. Therefore, it will take four clock pulses for the data from DATA IN to get to the DATA OUT. Figure 6.24 A 4-bit Shift Right SISO
DATA IN
D
Q
QA
D
Q
QB
D
Q
QC
D
Q
DATA OUT
CLK
100
Let‟s examine the operation of the circuit in figure 6.24. A 4-bit data (10112) are inserted serially (shift in/loading) in the DATA IN beginning with the rightmost bit (LSB). Figure 6.25 shows what happen to the inserted data after each clock pulse. Figure 6.25 Basic SISO operation (shift in)
DATA IN
Initial condition, all FF output are cleared.
1 0 1 1 D
Q
0
D
FF A
Q
0
D
FF B
Q
0
D
FF C
0
Q
DATA OUT
FF D
CLK
st
DATA IN
1 0 1 1 D
Q
1
D
FF A
Q
0
D
FF B
0
Q
D
FF C
0
Q
DATA OUT
After the 1 clock pulse, the LSB at the input D of FF A will be transferred to the Q of FF A
FF D
CLK
nd
DATA IN
1 0 1 1 D
Q
1
D
FF A
Q
1
D
FF B
0
Q
D
FF C
Q
0
DATA OUT
FF D
CLK DATA IN
1 0 1 1 D
Q
0
D
FF A
Q
1
D
FF B
1
Q
D
FF C
Q
0
DATA OUT
FF D
After the 2 clock pulse, the next bit at the input D of FF A will be transferred to the Q of FF A and the LSB at that already at the input of FF B will be transferred to Q of FF B rd After the 3 clock pulse, the next bit at the input D of FF A will be transferred to the Q of FF A and the other bit are shifted to the next FF
CLK
th
DATA IN
1 0 1 1 D
Q
1
D
FF A
Q
0
D
FF B
1
Q
D
FF C
Q
1
DATA OUT
FF D
After the 4 clock pulse, all the data has been loaded into this SISO register. Data can be stored until another clock pulse received (or the power is off)
CLK
To get back the data stored, data are shifted out serially. This is explained in figure 6.26. Figure 6.26 Basic SISO operation (shift out)
DATA IN
D
Q
1
FF A
D
Q
0
FF B
D
Q
1
FF C
D
Q
1 1
DATA OUT
FF D
CLK
DATA IN
D
Q
FF A
CLK
0
D
Q
FF B
1
D
Q
FF C
0
D
Q
FF D
1 1 1
DATA OUT
To shift the data out, new data must be inserted to „push out‟ the existing data. In this case, data 0000 will be inserted. This data is chosen because it will also clear the SISO register. th st After the 5 clock pulse the 1 0 are transferred to Q of FF A and by that, all the bit in the other FF are shifted to the next FF.
101
DATA IN
D
Q
0
D
FF A
0
Q
FF B
D
Q
1
FF C
D
Q
th
0 1 1
DATA OUT
FF D
CLK
DATA IN
D
Q
0
D
FF A
0
Q
FF B
D
Q
0
FF C
D
Q
1 1 0 1 1
DATA OUT
FF D
nd
After the 6 clock pulse the 2 0 are transferred to Q of FF A and by that, all the bit in the other FF are shifted to the next FF. th After the 7 clock pulse all the data bit in the SISO register has been outputted serially.
0
CLK
DATA IN
D
Q
0
D
FF A
0
Q
FF B
D
Q
0
FF C
D
Q
0
th
After the 8 clock pulse the register has been clear (reset).
DATA OUT
FF D
CLK
An 8-bit SISO register can be represented by a logic symbol shown in figure 6.27. Data in
REMEMBER
Q7
SRG 8
CLK
SRG 8 stands for Shift Register with 8-bit capacity
Q7
5.5 SERIAL IN / PARALLEL OUT SHIFT REGISTER (SIPO) This register takes in serial data; shift it, and when done, output the data in parallel. Figure 6.27 Basic Data Movement of a SIPO
Data in
Data out
Figure 6.28 A 4-bit Shift Right SIPO
DATA IN
D
Q
D
Q
D
Q
D
Q
CLK QA
QB
QC
QD
DATA OUT
Let‟s examine the operation of the circuit in figure 6.29. A 4-bit data (10112) are inserted serially (shift in/loading) in the DATA IN beginning with the rightmost bit (LSB). Figure 6.25 shows what happen to the inserted data after each clock pulse.
102
Figure 6.29 Basic SIPO operation
DATA IN
Initial condition, all FF output are cleared.
1 0 1 1 D
Q
D
FF A
Q
D
FF B
Q
D
FF C
Q
FF D
CLK 0
0
0
0
DATA OUT
st
DATA IN
1 0 1 1 D
Q
1
FF A
D
Q
0
FF B
D
Q
0
FF C
D
Q
0
After the 1 clock pulse, the LSB at the input D of FF A will be transferred to the Q of FF A
FF D
CLK 1
0
0
0
DATA OUT
nd
DATA IN
1 0 1 1 D
Q
1
FF A
D
Q
1
FF B
D
Q
0
FF C
D
Q
0
FF D
CLK 1
1
0
After the 2 clock pulse, the next bit at the input D of FF A will be transferred to the Q of FF A and the LSB at that already at the input of FF B will be transferred to Q of FF B
0
DATA OUT
rd
DATA IN
1 0 1 1 D
Q
0
FF A
D
Q
1
FF B
D
Q
1
FF C
D
Q
0
FF D
After the 3 clock pulse, the next bit at the input D of FF A will be transferred to the Q of FF A and the other bit are shifted to the next FF
CLK 0
1
1
0
DATA OUT
th
DATA IN
1 0 1 1 D
Q
1
FF A
D
Q
0
FF B
D
Q
1
FF C
D
Q
1
FF D
CLK 1
0
1
1
After the 4 clock pulse, all the data has been loaded into this SIPO register. Data can be stored until another clock pulse received (or the power is off) and can be retrieved simultaneously (in parallel).
DATA OUT
An 8-bit SIPO register can be represented by a logic symbol shown in figure 6.30. Figure 6.30 Logic symbol for an 8-bit SIPO
Data in
SRG 8
CLK
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
103
The 74LS164: 8-bit Serial in / Parallel out Shift Register This IC has two data input, A and B. Data is entered serially through either A or B with the other function as enable/disable control or tied to Vcc if unused. It also has asynchronous active low master reset (MR). Figure 4.20 The 74LS164: 8-bit Serial in / Parallel out Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom).
(14) Vcc
1
14
Vcc
B
2
13
Q7
A
Q0
3
12
Q6
B
Q1
4
11
Q5
Q2
5
10
Q4
Q3
6
9
MR
Q5
GND
7
8
CP
Q6
(12)
Q7
(13)
74LS164
CP
MR
(1)
Q0
(4)
Q1
(2)
Q2
(8)
Q3 Q4
(9)
Examining from the internal circuitry: (i) If the leftmost st bit is entered 1 , which of the output is the MSB th after the 8 clock pulse? (ii) How to use this IC as SISO?
(3)
A
(5) (6) (10) (11)
GND (7)
A B
D
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
CLR
CP MR Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
5.6 PARALLEL IN / SERIAL OUT SHIFT REGISTER (PISO) Parallel in enables data to be entered simultaneously rather than one bit at a time directly into its respective stage (FF). Data are outputted bit by bit (serially). Figure 4.21 Basic Data Movement of 4-bit PISO (left) and logic symbol (right)
Data in Data in D0 D1 D2 D3 SHIFT / LOAD
Data out
SRG 4 Data out
CLK
A PISO has a control input (SHIFT/LOAD) to set the operation mode of this circuit. When this input is LOW (0), this register is in LOAD mode, meaning that all the DATA IN will enter their respective FF at the next triggering edge; and when it is HIGH (1), this register is in SHIFT mode, meaning that all the bits is shifted to the next FF at every triggering 104
edge. Figure 4.22 4-bit Parallel in/ Serial out internal circuitry.
DATA IN D0
SHIFT/LOAD
D1
1
2
D
Q
Q0
D2
3
4
D
Q
Q1
D3
5
6
D
Q
Q2
7
D
Q
Q3
CLK
Referring to figure 4.22, when the control input (SHIFT/LOAD) is:
LOW (0): AND gate 1, 3, 5 and 7 will be enabled allowing DATA IN bit to enter their respective FF at the next triggering edge while AND 2, 4 and 6 are disabled, stopping all the shifting.
HIGH (1): AND gate 2, 4 and 6 will be enabled allowing data to be shifted to the next FF at the next triggering edge while AND 1, 3, 5 and 7 are disabled.
The 74LS165: 8-bit Parallel In/ Serial Out Shift Register The 74LS165 uses SHIFT/LOAD input to determine its operation. If its LOW (0), it will load value D0 to D7 into the register and if it is HIGH (1), the register will shift its content (while parallel input is disabled). This IC also allows serial data input through DS (only when SHIFT/LOAD input is HIGH (1)). Clocking is accomplished through a 2-input OR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is HIGH (if not, it will assume the level change as clock).
105
Figure 4.23 The 74LS165: 8-bit PISO Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom).
SHIFT / LOAD
DS Vcc
SHIFT / LOAD
1
16
CLK
2
15
D4
3
14
D3
D5
4
13
D2
D6
5
12
D1
D7
6
11
D0
Q7
7
10
DS
GND
8
9
Q7
Examining from the internal circuitry: (i) How to use this IC as a SISO?
(8)
CLK
(9)
CLK INH
74LS165
(1) (10)
CLK INH
(3) D0 (4)
Q7
D1 (5) (6) (10) (11) (12)
Q7
D2
(9) (7)
D3 D4 D5 D6
(13) D 7
D0
D1
D2
D3
D4
D5
D6
D7
SHIFT/ LOAD
DS
D
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
D
CLR
Q
CLR
D
Q
CLR
D
Q
CLR
D
Q
Q7
CLR
CLK CLK INH
5.7 PARALLEL IN / PARALLEL OUT SHIFT REGISTER (PIPO) A parallel in/ parallel out shift register takes all the DATA IN bit simultaneously and after triggering edge, the data are available for retrieval at the output line. Figure 4.24 Basic Data Movement of 4-bit PIPO (left) and logic symbol (right) and internal circuitry (bottom)
Data in D0 D1 D 2 D 3
Data in
SRG 4 CLK Q0 Q1 Q2 Q3 Data out
Data out DATA IN D0
D1
D
Q
D2
D
Q
D3
D
Q
D
Q
CLK Q0
Q1
Q2
Q3
DATA OUT
106
The 74HC195: 4-bit Parallel Shift Register This shift register features parallel inputs, parallel outputs, JK inputs, SHIFT/LOAD control input, and a asynchronous CLEAR. This shift register can operate in two modes: PARALLEL LOAD; SHIFT from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and setting the SHIFT/LOAD control input to LOW (0). The data is loaded into the respective FF and available at the outputs after the positive transition of the clock input (triggering edge). During parallel loading, serial data flow is disabled. Serial shifting occurs synchronously when the SHIFT/LOAD control input is HIGH (1). Serial data for this mode is entered at the J-K inputs. Figure 4.23 The 74LS195: 4-bit Parallel Shift Register pin diagram (left), logic symbol (right) and internal circuitry (bottom).
SHIFT / LOAD
CLR
Vc c
J
(9) (10)
1
16
J
2
15
Q0
K
3
14
Q1
D0
4
13
Q2
D1
5
12
Q3
(4)
D2
6
11
Q3
(5)
D3
7
10
GND
8
9
74HC195
K CLK
CLR
CLK
(8)
Q1
(9)
Q2 (1)
(6)
SHIFT / LOAD
Q0
(7)
Q3 D0
Q3
Examining from the internal circuitry: (i) How to use the J K input for serial DATA IN
(15) (14) (13) (12) (11)
D1 D2 D3
SHIFT/ LOAD
J
K
D0
D1
D2
D3
CLR CLK
Q3
Q0
Q1
Q2
Q3
107
TUTORIAL 1.
2.
3.
3.
What is the difference between a LATCH and a FLIP-FLOP? (a) Latch is a level sensitive device while flip-flop is an edge sensitive device.
(b) Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
(c) Latches take less gates (also less power) to implement than flip-flops.
(d) all above
A bistable multivibrator is (a) an electronic circuit
(b) has two stable states
(c) capable of serving as one bit of memory
(d) all of above
Which of the following circuit realized a D flip-flop? (a)
(b)
(c)
(d)
For a gated D latch, the Q output always equals the D input (a) before the enable pulse
(b) during the enable pulse
(c) immediately after the enable pulse
(d) answers (b) and (c) 108
4.
A JK flip-flop is presently in the SET state and must remain SET on the next clock pulse. What is the input J and K? (a) J must be 1 and K must be 1.
(b) J must be 0 and K must be 0.
(c) J must be 1 and K must be 0
(d) Answer (b) and (c)
5.
When will the second flip-flop update its output Z?
6.
7.
8.
(a) When the input Y is changed.
(b) When the clock value changes from high to low.
(c) When the clock value changes from low to high.
(d) Never.
Asynchronous counter are known as (a) ripple counters
(b) multiple clock counters
(c) decade counters
(d) modulus counter
For a finite state machine with 30 states, the number of storage elements (flip-flops) needed to implement the sequential machine circuit is (a) 30
(b) 15
(c) 5
(d) 4
In a clocked sequential circuit, the finite state machine can make a transition from one state to another state: (a) only once per clock cycle
(b) only when it is in the initial state
(c) at any time
(d) depends on the combinational logic
109
9.
Which of the following shows the connection for mod-6 counter using a decade counter? (a)
(b)
(c)
(d)
10. The waveforms in Figure Q6 are applied to the inputs A & B of a flip-flop. Based on the waveform of output Q, determine the type of flip-flop. (a) SC flip-flop with PGT
(b) JK flip-flop with PGT
(c) SC flip-flop with NGT
(d) JK flip-flop with NGT
11. Which of the following is NOT a characteristic of the latches?
110
(a) Temporarily stored the data.
(b) The operations are synchronous.
(c) The outputs respond to the present inputs.
(d) The latches are bistable devices.
12.
For a positive edge-triggered JK flip-flop with preset and clear inputs in figure above, determine the Q output at clock pulse 6, 7 & 8. (a) 000
(b) 010
(c) 001
(d) 100
13. A feature that distinguishes the JK flip-flop from the SC flip-flop is the (a) toggle condition
(b) clear input
(c) preset input
(d) type of clock
14. A JK flip-flop with J = 1 and K = 1 has a 5 kHz clock input. The output Q is (a) constantly low
(b) a 5 kHz square wave
(c) a 10 kHz square wave
(d) a 2.5 kHz square wave
15. Asynchronous counters are also known as ripple counter. How many JK flip-flops are needed to build MOD 32 counters? 111
(a) 4
(b) 6
(c) 5
(d) 7
16.
Indicate the type of the counter in Figure Q13. What would be the values of Q 2, Q1 and Q0 when PL is low if P2, P1 and P0 are 0, 1 and 1 respectively? (a) Ripple counter, 110
(b) Presettable synchronous counter, 110
(c) Ripple counter, 011
(d) Presettable synchronous counter, 011
17. Which of the following is NOT the characteristic of Moore state machine? (a) Output signals can have asynchronous changes
(b) Moore output is a function only of the current flip-flop.
(c) Output signals are all synchronous.
(d) Next states of Moore machine depend solely on the present states.
18. A 10-bit ripple counter has a 256 kHz clock signal applied. Determine the frequency at the MSB output and the MOD number of this counter.
112
(a) 250 Hz, 1024
(b)
250 Hz, 10
(c) 100 Hz, 1024
(d)
100 Hz, 10
19. The invalid state for a SC latch occurs when (a) S=1, C=0
(b)
S=1, C=1
(c) S=0, C=1
(d)
S=0, C=0
20. Like the latch, flip-flop belongs to a logic circuit known as (a) monostable multivibrator
(b)
bistable multivibrator
(c) astable multivibrator
(d)
one-shots
21. The purpose of having the clock input to a flip-flop is to (a) clear the state
(b)
always cause the output to change states
(c) set the flip-flop
(d)
cause the output to assume a state dependent on the controlling (SC,JK,D) inputs
(a) state changes can only occur at the clock pulse edge
(b)
the state the flip-flop goes to depends on the D input
(c) the output follows the input at each clock pulse
(d)
all of the above
22. For an edge triggered D flip-flop,
23. A JK flip-flop is in “toggle” mode when (a) J=1, K=0
(b) J=0, K=0
(c) J=1, K=1 (d) J=0, K=1 24. An asynchronous counter differs from a synchronous counter in (a) the method of clocking
(b) the type of flip-flop used
113
(c) the number of states sequence
(d) the modulus value
25. A 3 bit binary counter has a maximum modulus of (a) 3
(b) 6
(c) 8
(d) 16
26. A BCD counter is also known as (a) decade counter
(b) full modulus counter
(c) a truncated modulus counter
(d) both (a) and (c)
27. Complete the following table of flip-flop excitation values required to produce the indicated flip-flop state changes, where X indicates the present state and Y is the desired next state of the flip-flop. Present state X 0 0 1 1
Next State Y 0 1 0 1
J-K Flip flop J
K
SC Flip flop S
C
D Flip flop D
28. Given the JK flip flop as shown in the Figure 28 below. Complete the timing diagram of Figure 28 by determining the output waveform of Q.
Figure 28
29. The circuit of Figure 29contains a D latch, a positive edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. Complete the timing diagram of Figure 29 by drawing the waveforms of the signals y1, y2 and y3.
114
Figure 29 30
(a) Draw the state transition diagram for a three bit counter that has the following counting sequence: 0,1,2,4,6,7,3,5,0,1… repeats. (b) What is the MOD number of the counter? (c) If the counter is initially at 1012, what count will it hold after 3673 pulses?
31. A clock generator system's input frequency is 36 kHz. The system is required to generate two frequencies 9 kHz and 3 kHz at its outputs. Propose an arrangement for frequency division by using counters. 32. Design a state machine based on state diagram given in Figure 32 below by using Moore machine. Assume state 0,3,4,6 as don‟t care. Implement the circuit by using JK flip-flop. 001
111
010
101
Figure 32 33. Given the circuit diagram of Figure 33, complete the timing diagram of Figure 33 for Q A, QB and QC.
115
Figure 33 34. Analyse the circuit diagram of Figure 34(a) and complete the timing diagram of Figure 34(b). Do not show the propagation delays. Draw the truth table of this circuit.
(a)
(b)
Input Before After A B Q Q Q Q
35. Design and realise a 3-bit counter that counts in the following sequence: …, 111, 010, 001, 110, 100, 000, 111, 010, 001, …
116
Use JK flip-flops in this design.
36. Complete the timing diagram for this circuit. The initial states of D flip-flops and input waveforms are shown in Figure 36.
Figure 36 37. Table 37 is a state table for a circuit operation. Assume you make use of J-K flip flop in the design. X is the external input and Z is the output of the circuit. Draw the logic diagram for the sequential circuit Present state ABC 000 010 100 110 111
Next State
Output Z
X=0 000 000 010 100 110
X=0 0 0 1 0 1
X=1 010 100 110 111 000
X=1 1 1 0 0 1
38. Explain one (1) advantage and one (1) disadvantages of a synchronous counter compared with an asynchronous counter using suitable example or figure.
117
39. Figure below shows the block diagram of a digital clock. Show the connection for counter A, B and C using IC 74LS293.
40. Design an asynchronous counter that will count in a sequence of 6, 5, 4, 3, 2, 1 and repeat. Use only J-K flip-flop that has two active low control inputs PRE and CLR. Explain the operation of your design briefly. 41. Figure below show the logic symbol of 74LS293, 4-bit binary counter. Show how it can be used to generate a 10KHz clock from the 60KHz clock source. Label completely.
Clock 60KHz
(10) (11)
(12) (13)
CP0
Q4
CP1
Q2 Q1
MR1 MR2
&
Q0
(8) (4) (5) (9)
42. Eight sensors each feed eight bits of information to a circuit which processes the information. It is decided that instead of using 64 signal lines, the data will be multiplexed onto eight data lines with three address lines used to indicate the sensor using the data lines. In fact, the sensors will be continually cycled through in order. (i)
A three-bit counter is required to cycle through the values for the address lines. Design it using JK flip-flop. You may assume the availability of a clock signal.
(ii)
An 8:1 multiplexer has eight data inputs, three control inputs and an output. The value of the control inputs determines the data input which is selected as the output. Design an 8:1 multiplexer.
(iii)
Show how these components could be used to build the required system.
118
43. (a)
A 4-bit shift register constructed from edge-triggered D-type flip flops is shown in Figure Q6(a). If, on successive rising edges of the clock signal CLK, the input takes on the values 1, 0, 1, 0, 1, 1, 1, 0, what are the contents of the shift register after each edge of the clock? You may assume that the register contains all zeroes initially. (3 marks)
(b)
The shift register in Q6(a) is require to detect „1011‟ bit pattern from the serial data feed into the input pin. Design and illustrate how a combinational logic circuit can be added to achieve this. This combinational logic circuit will produce an output HIGH (1) when the pattern is detected. (7 marks)
(c)
Figure Q6(c) shows a state transition diagram for an infinite state machine with control input, Y. Design the circuit using JK flip-flop. (15 marks)
44. The circuit of Figure 3(a) contains a D latch, a positive edge-triggered D flip-flop, and a negative edge-triggered D flip-flop. Complete the timing diagram of Figure 3(b) by drawing the waveforms of the signals y1, y2 and y3.
119
45. Given the circuit diagram below, complete the timing diagram for QA, QB and QC. Assume that QA, QB and QC are at high level initially.
46. Design a circuit that will generate TWO (2) frequencies, 12 kHz and 3 kHz at its outputs when a clock signal applied to the circuit is operating at 48 kHz. Use JK flip-flops in your design.
120
47. Determine and draw the state transition diagram for the Moore machine below.
‘1’
‘0’ JA
QA
FF A
‘1’
KA
QA
JB
QB
FF B KB
QB
JC
QC
FF C KC
QC
CLK
121
SUBJECT:
EXPERIMENT 17:
PRELAB TASK
ELECTRICAL ENGINEERING LABORATORY BEE 2291 DIGITAL ELECTRONICS Full Modulus MOD-16 Asynchronous Counter
1. Show (in drawings) how a four JK flip-flop can operate as a MOD-16 counter. 2. Re-draw this circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 1.
LAB TASK
1. Construct circuit 1 on the protoboard. 2. Connect all the outputs to LED and verify that the counter is functioning correctly. 3. Write a brief comparison about the advantages and disadvantages between an asynchronous counter and a synchronous counter. 4. Modify this circuit to implement a MOD-10 counter 5. Write a brief discussion about the difference between a full modulus counter and a truncated counter.
EXPERIMENT 18: PRELAB TASK
Building a 3-bit Moore machine 1. Figure 1 shows the state diagram of a 3-bit Moore machine. Build the next state table for this counter. 2. Build the excitation table. 3. Using k-map, get expression for the circuit.
000
101
011
010
111
simplified
4. Draw the circuit using 3 J-K flip-flops. 5. Re-draw this circuit complete with IC and pin numbers (refer datasheet for the IC pin assignment). Name this circuit as circuit 1. LAB TASK
001
100
110
1. Build circuit 1 on the protoboard. 2. Make sure every IC is connected to +5V and ground properly. 3. Verify that the counter is functioning correctly. 4. What are the difference between state machines and counter?
122
CHAPTER 7
DIGITAL SYSTEM INTERFACING OUTLINE •
DIGITAL-TO-ANALOG (DAC) CONVERSION
•
DAC CIRCUITARY
•
DAC PERFORMANCE
•
DAC CONVERSION ERROR
•
RECONSTRUCTION FILTER
•
ANALOG-TO-DIGITAL (ADC) CONVERSION
•
SAMPLE AND HOLD
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In chapter 1, we have discussed about the overcoming the limitation of digital system by using ADC (analog-to-digital converter) and DAC (digital-to-analog converter). This chapter will discuss the detail about interfacing a digital system with analog world. 7.1 DIGITAL-TO-ANALOG CONVERSION (DAC) We will start by discussing about DAC first. This is because DAC is „simpler‟ than ADC process and ADC circuit also contains DAC circuit. Remember that a digital signal comprises of binary bits, while analog signal can either be voltage or current. Depending on the value (or combination) of the digital input, the corresponding predetermine analog signal will be outputted. Binary-Weighted-Input DAC One method of DAC is by using resistor with different value for each bit. The LSB has the largest value resister (lowest current) while the MSB has the smallest value resistor (largest current) because each binary bit has different weight. The typical circuit is shown in figure 7.1. If there is voltage at the input (input HIGH), there will be current across the resistor and this current value varies between each input because of the different resistor value. Because there is practically no current at the inverting input of the opamp (virtual ground), all the input current are summed together and the drop across Rf is equal to the output voltage. Figure 7.1 Typical BinaryWeightedInput DAC Circuit
D0 D1 D2 D3
8R
Rf
I0 4R
I1 2R
+
V0=IfRf
I2 R
I3
The disadvantage of this type of DAC is the input level must be the same and the amount of resistor needed in a higher bit input DAC. If there is 8-bit input, the resistor must be in the range of R to 255R, making this type of ADC very difficult to mass-produce. Lets us examine circuit in figure 7.2. We are going to feed binary input 00002 (010) to 11112 (710) and calculate the corresponding output.
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Figure 7.2 Example value of a BinaryWeightedInput DAC Circuit
D0 D1 D2 D3
200 kΩ
10 kΩ
I0 100 kΩ
+
I1 50 kΩ
V0=IfRf
I2 25 kΩ
I3
For a +5 input (typical value for digital circuit) the current at each inputs are: 5V I0 0.025mA 200kΩ 5V I1 0.05mA 100kΩ 5V I2 0.1mA 50kΩ 5V I3 0.2mA 25kΩ Therefore, Vout(D0) 10kΩ 0.025mA 0.25V
Vout(D1) 10kΩ 0.05mA 0.5V
Vout(D2) 10kΩ 0.1mA 1V
Vout(D3) 10kΩ 0.2mA 2V
Figure 7.3 shows the output voltage for each of the input combination. V0 3.75 3.50 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25
1101 1110 1111
OUTPUT V0 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 -1.75 -2.00 -2.25 -2.50 -2.75 -3.00 -3.25 -3.50 -3.75
1001 1010 1011 1100
D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0101 0110 0111 1000
INPUT D2 D1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
0001 0010 0011 0100
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0000
Figure 7.3 BinaryWeightedInput DAC Circuit Output
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Input (binary)
Notice that in the graph in figure 7.3, the analog output is not pure analog signal (it look more like a step). In fact, a DAC output cannot produce a pure analog signal (which varies continuously with time). DAC Resolution Resolution determines the accuracy of a DAC and it can be expressed as the step size or the number of step.
The different between each step in the graph in figure 7.3 is the step size. It is defined as the smallest change that can occur in the analog output corresponding to the input. So, for DAC in figure 7.3, the step size is 0.25 V. The smaller the step size, the „more analog‟ the output will be (because of the step is smaller). So, the smaller the step size, the better DAC it is. REMEMBER Don‟t get confuse with „resolution‟ in digital imaging. The resolution in image is often referred to the amount of pixel in a specific size image. Thus, the higher resolution is, the better the picture quality.
Resolution (step size) is calculate with the formula below
resolution (step size) K
A fs 2n 1
where Afs = analog full-scale output n = the number of bits
From the formula, it can be seen that to decrease resolution, the full-scale analog output must be kept small and the number of bits is high. But achieving high resolution is not easy and maybe costly. Not easy because the Afs is depended on the application the DAC are used in and costly when the bits is higher (more gates). Although higher resolution is better, it may not always necessary to have it. Let‟s take a DC motor speed controller as an example; a small increase in current may not be enough to vary the motor speed. Thus, using a small resolution DAC will be a waste. Resolution may also be expressed in percentage using the formula below.
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% resolution (step size)
Step size 100% A fs
Resolution can also be referred to the number of discrete steps in the output, which is dependent on the number of bits for the input. For example a 4-bit DAC has 15 steps (each step is one part of fifteen. This can also be expressed in percentage as 6.67% or the number of bits converted.
Input Weight Each of the bits in the binary input has different amount of contribution to the output (weight). Taking DAC in figure 7.3 for example, the weight for D3 is -2V, D2 is -1V, D1 is -0.5V and D0 is -0.25V. The MSB (D3) has the most weight while LSB (D0) has the least. The weight of the LSB is also the DAC resolution
7.2 DAC CIRCUITARY We are going to take a look at several DAC circuit. The first one is the „Binary-weighted-input DAC‟ which we already seen in figure 7.1. This DAC consist of a resistor network to give every input a different weight and then been connected to a summing op-amp. One of the problems for this type of DAC is that Vout is dependent on the digital input voltage. In the previous example, the weights of each bit are calculated by assuming the input is 5V, which is the ideal case. To overcome this, additional circuits are needed to provide a precise input voltage. Binary-Weighted-Input DAC Circuit With Reference Supply Figure 7.4 shows an improved version of Binary-weighted-input DAC. It has a „reference supply‟ to keep the input voltage of the DAC to 5V. Each digital input control an electronic controlled switch (can also be relay) to connect or disconnect the DAC input to the reference supply. If the digital input is HIGH (1), the switch will closed and the DAC input for that bit will be pulled to 5V (reference supply)
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Figure 7.3 BinaryWeightedInput DAC Circuit With Reference Supply
Reference Supply 8R
D0
I0
Rf
4R
D1
+
I1
V0=IfRf
2R
D2
I2
R
D3
I3
The R/2R Ladder DAC Another problem with Binary-Weighted-Input DAC is that the value or R (resistor) can be very large. Let say we have an 8-bit DAC. The resistor value will be between R and 128R and the tolerance must be low to give an accurate result. This problem can be overcome by using R/2R Ladder DAC. It only uses two resistor value, R and 2R. In this circuit, the MSB is D3. Figure 7.3 The R/2R Ladder DAC
D0
D1
D2
D3 Rf = 2R
R1 2R
R2 2R
R3 2R
R4 R
R5 2R
R6 R
R7 2R
+
R8 R
Vout
Now let see this DAC in action. We will do an analysis for several input condition. Case 1: D3=1,D2=0,D1=0,D0=0 Figure 7.4 The R/2R Ladder DAC with input D=0001
0
0
0
5V Rf = 2R
R1 2R
R2 2R
R3 2R
R4 R
R5 2R
R5 R
R7 2R
R7 R
+
Vout
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the equivalent circuit will be: Figure 7.5 The R/2R Ladder DAC with input D=0001 (equivalent circuit)
5V Rf = 2R R7 2R
+
REQ 2R
Vout
therefore: 5V Vout IR f 2R 5V 2R
Case 2: D3=0,D2=1,D1=0,D0=0 Figure 7.6 The R/2R Ladder DAC with input D=0010
0
0
5V
0 Rf = 2R
R1 2R
R2 2R
R3 2R
R4 R
R5 2R
R5 R
R7 2R
+
R7 R
Vout
the equivalent circuit will be: Figure 7.7 The R/2R Ladder DAC with input D=0010 (equivalent circuit)
5V Rf = 2R R5 2R
R8 R
REQ 2R
R7 2R
+
Rf = 2R
VTH 2.5V Vout
RTH R
R8 R R7 2R
+
Vout
therefore: 2.5V Vout IR f 2R 2.5V 2R
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Case 3: D3=0,D2=0,D1=1,D0=0 Figure 7.8 The R/2R Ladder DAC with input D=0100
0
5V
0
0 Rf = 2R
R1 2R
R2 2R
R3 2R
R4 R
R5 2R
R5 R
R7 2R
+
R7 R
Vout
the equivalent circuit will be: Figure 7.9 The R/2R Ladder DAC with input D=0100 (equivalent circuit)
5V Rf = 2R R3 2R
REQ 2R
R8 R
R6 R R5 2R
Rf = 2R
VTH 1.25V
+
R7 2R
Vout
RTH R
R8 R R7 2R
+
Vout
therefore: 1.25V Vout IR f 2R 1.25V 2R
Case 4: D3=0,D2=0,D1=0,D0=1 Figure 7.10 The R/2R Ladder DAC with input D=1000
5V
0
0
0 Rf = 2R
R1 2R
R2 2R
R3 2R
R4 R
R5 2R
R5 R
R7 2R
R7 R
+
Vout
the equivalent circuit will be:
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Figure 7.11 The R/2R Ladder DAC with input D=1000 (equivalent circuit)
5V Rf = 2R R1 2R
R2 2R
R6 R
R4 R R3 2R
R8 R R5 2R
R7 2R
+
Rf = 2R
VTH 0.625V Vout
R8 R RTH R
R7 2R
+
Vout
therefore: 0.625V Vout IR f 2R 0.625V 2R
7.3 DAC PERFORMANCE Performance of DAC are determine by the following characteristic: Resolution: (see previous subtopics) Accuracy: the comparison of the actual DAC output with the expected output. Linearity: a linear error is a deviation from the ideal straight-line output of a DAC. Monotonicity: a DAC is monotonic if it does not take any reverse steps when it is sequenced over its entire range of input bits. Settling time: normally defined as the time a DAC takes to settle within ± ½ LSB of its final value when input code changes.
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7.4 DAC CONVERSION ERROR Several type of errors can arise in a DAC are shown below. Figure 7.12 DAC with nonmonotonicity error
Analog Output Ideal
15 14 13 12 11 10 2 9 8 7 6 5 4
Nonmonotonicity output
3 2 1 0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Binary Input
Analog Output 15 14 13 12 11 10 2 9 8 7 6 5 4
Ideal
Non-linearity output
3 2 1 0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Figure 7.13 DAC with non-linearity error
Binary Input
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Figure 7.14 DAC with non-linearity error
Analog Output High gain
15 14 13 12 11 10 2 9 8 7 6 5 4
Ideal
Low gain
3 2 1 0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Binary Input
Analog Output 15 14 13 12 11 10 2 9 8 7 6 5 4
Ideal Offset
3 2 1 0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Figure 7.15 DAC with offset error
Binary Input
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7.5 RECONSTRUCTION FILTER To get a more „analog‟ output, the staircase like DAC output are usually feed into a reconstruction filter (a.k.a. post filter) to smoothen the output. This is done by removing the higher frequency content of the signal by using a low-pass filter. Figure 7,16 below shows the signal at the input of this filter at the resulting output. Figure 7.16 Reconstruction filter input (left) and output (right).
Analog Input
Analog Output
t
t
7.6 ANALOG -TO- DIGITAL CONVERSION (ADC) Now let‟s take a look an analog-to-digital converter (ADC). As we know, ADC takes an analog input signal and converts it into a digital signal (bit). It also has a DAC as its main component. Figure 7.17 Basic 8-bit Digital Ramp ADC block diagram
Analog Input VA
Clock
Comparator + -
VA’
Counter
DAC
Reset
Start D7………………………………….D0 Binary (digital output)
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This is how the ADC in figure 7.17 works. (i)
(ii)
(iii)
(iv)
A pulse (Start) is given to signal the start of the conversion process. When the start signal is HIGH (1), the AND gate is disabled and no clock signal are feed into the counter. This HIGH (1) start pulse also reset the counter to 0000 00002. When the start pulse goes to LOW (0), the AND gate are enabled thus allowing clock signal to go into the counter; as long as the output of the comparator is HIGH (1). Output of the comparator will be HIGH when VA > VA‟. Counter will start to count (one count), and the outputs are feed into a DAC which generate the analog value (VA‟) of the current counter binary output. The comparator then compares VA‟ with VA. If VA > VA‟, the AND gate will still be enabled, thus step (ii) and (iii) are repeated. When VA VA‟, output f the comparator will become LOW (0), thus disabling the AND gate. As a result, the counter will stop counting (because there is no clock), and the current counter binary output is the digital value of the analog input.
Because of the conversion will not always stop at VA = VA‟ (can also stop when VA < VA‟, we can say that the binary digital output is an approximation of the analog input. Because the counter in this ADC need to count until VA VA‟ before the digital output can be obtain, this type of ADC is slow, especially if the number of output bit increased and the time to finish vary depending on the analog input.
Flash ADC Flash ADC, as the name implies, is a faster DAC than successiveapproximation ADC. In flash ADC, multiple comparators are used, thus conversion are done simultaneously. When the input the input voltage exceeds the reference voltage of the comparator, output HIGH (1) will be generated. Each comparator reference voltage is different because of the voltage-divider resistor network. For an N-bit ADC, the comparator needed is 2N-1 (less 1 because we don‟t need conversion for 0V input. The high number of comparator for a high number of bits outputs is the main disadvantage of this ADC. Outputs of these comparators are then connected to a priority encoder (see chapter 4) to generate the binary digital value. Figure 7.18 below shows a 3-bit flash ADC.
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Figure 7.18 Basic 3-bit Flash ADC.
+VREF Analog Input
Comparator + -
+ -
+ -
7 6 5
+ -
4 3
Priority Encoder
1
D0
2
D1
4
D2
Digital Output
2 + -
1 0
+ -
+ -
7.7 SAMPLE AND HOLD Before ADC conversion can be done, the analog value must hold still until the conversion is done, which is impossible because analog signal is a signal that varies over time. Therefore, to get a „still‟ signal, the analog signal is „sampled‟ and then „hold‟ until the conversion complete. Sampling is a process of taking a sufficient number of discrete values at points on the waveform. These discrete values are used to define the waveform shape. Figure 7.19 below shows an original analog signal that are being sampled by sampling pulse A and sampling pulse B (figure 7.20). Figure 7.21 shows the resulting sampled signal.
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Figure 7.19 Original Analog Signal
Figure 7.20 Sampling Pulse
Figure 7.21 Sampled Signal
Analog Input
Analog Input
Sampling Pulse (A)
Sampling Pulse (B)
Sampled Signal Sampled Output
As we can see from figure 7.21, a lower frequency of sampling pulse resulting in a less accurate discrete representation of the original signal. The proper frequency for sampling must be determined using Nyquist theorem. Nyquist Theorem: f sample f a (max) where fa(max) is the highest analog frequency.
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CHAPTER 8
INTEGRATED LOGIC CIRCUIT FAMILY OUTLINE •
INTEGRATED CIRCUIT (IC) BASIC
•
IC CHARACTERISTIC AND PARAMETER
•
MOSFETs
•
TRANSISTOR-TRANSISTOR LOGIC (TTL)
•
PROGRAMMABLE LOGIC DEVICE (PLD)
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In this chapter, we will discuss the details of integrated circuit (or IC). There are two type of IC, the fixed function (which function has already been set by the manufacturer) and the programmable one. We will focus on the fixed function IC and take a brief look at the programmable IC at the end of this chapter. 8.1 INTEGRATED CIRCUIT (IC) BASIC The term integrated circuit (IC) is a small chip made of silicon that contains the entire electronic circuit. This small chip are put inside a „packaging‟ and connected to the package pin for I/O connection. Figure 8.1 Cutaway view of an IC
Packaging The most common IC packaging is the Dual-inline-package (DIP) such as in figure 8.1. This packaging is for through hole-mounted circuit board or PCB. For more complex IC (more pins), Pin Grid Array (PDA) packaging are used. The disadvantage of this type of packaging is the space it used, and not suitable for multi layer circuit board. Figure 8.2 PGA Packaging
Surface mount technology (SMT) overcome this limitation by offering smaller size package and the pin can directly be soldered on the surface. Thus, allowing multi layer circuit board.
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Figure 8.3 SOIC (small outline IC), a type of SMT Figures below show the various type of SMT package and a short explanation. Figure 8.3 PLCC Package IC (above) PLCC socket (below)
A Plastic Leaded Chip Carrier (PLCC) is a four-sided “J”-leaded plastic integrated circuit package with pin spacing of 0.05" (1.27 mm). Lead counts range from 20 to 84. PLCC PLCC sockets may in turn be surface mounted, or use thru-hole technology. The motivation for a surface-mount PLCC socket would be when working with devices that cannot withstand the heat involved during the reflow process, or to allow for component replacement without reworking.
Figure 8.4 LCC Package IC
A leadless chip carrier (LCC) is a type of packaging for integrated circuits which has no "leads", but instead rounded pins through the edges of the ceramic package.
Figure 8.5 SSOP Package IC
Shrink small-outline package (SSOP). A microchip package for surface-mount technology with "gull wing" leads protruding from the two long sides and a lead spacing of 0.025 inches.
Figure 8.6 TSSOP Package IC
A TSSOP (Thin-Shrink Small Outline Package) is a four-sided, rectangular, thin body size surface mount component. A Type I TSSOP has leads protruding from the width portion of the package. A Type II TSSOP has the leads protruding from the length portion of the package. A TSSOP's lead count can range from 8 to 56.
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Figure 8.7 P4-LGA775 Package IC (above) and socket (below)
The land grid array (LGA) is a physical interface for microprocessors of the Intel Pentium 4 and AMD Opteron families. Unlike the pin grid array (PGA) interface found on most AMD and Intel processors, there are no pins on the chip; in place of the pins are pads of bare gold-plated copper that touch pins on the motherboard. LGA processor sockets include Socket F (also called Socket 1207) from AMD and the Prescott core Pentium 4 and Xeon chip systems with the new model number system from Intel.
IC Classification IC can be classified into several groups. The most common classification are by type and transistor count.
By type: o Integrated circuits can be classified into analog, digital and mixed signal (both analog and digital on the same chip). o Digital integrated circuits can contain anything from a few thousand to millions of logic gates, flip-flops, multiplexers, and other circuits in a few square millimeters. The small size of these circuits allows high speed, low power dissipation, and reduced manufacturing cost compared with board-level integration. These digital ICs, typically microprocessors, DSPs, and micro controllers work using binary mathematics to process "one" and "zero" signals. o Analog ICs, such as sensors, power management circuits, and operational amplifiers, work by processing continuous signals. They perform functions like amplification, active filtering, demodulation, mixing, etc. Analog ICs ease the burden on circuit designers by having expertly designed analog circuits available instead of designing a difficult analog circuit from scratch. o ICs can also combine analog and digital circuits on a single chip to create functions such as A/D converters and D/A converters. Such circuits offer smaller size and lower cost, but must carefully account for signal interference
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By transistor count: o The first integrated circuits contained only a few transistors. Called "Small-Scale Integration" (SSI), they used circuits containing transistors numbering in the tens. SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missile and Apollo program needed lightweight digital computers for their inertially-guided flight computers; the Apollo guidance computer led and motivated the integrated-circuit technology, while the Minuteman missile forced it into massproduction. These programs purchased almost all of the available integrated circuits from 1960 through 1963, and almost alone provided the demand that funded the production improvements to get the production costs from $1000/circuit (in 1960 dollars) to merely $25/circuit (in 1963 dollars). They began to appear in consumer products at the turn of the decade, a typical application being FM inter-carrier sound processing in television receivers. o The next step in the development of integrated circuits, taken in the late 1960s, introduced devices which contained hundreds of transistors on each chip, called "Medium-Scale Integration" (MSI). They were attractive economically because while they cost little more to produce than SSI devices, they allowed more complex systems to be produced using smaller circuit boards, less assembly work (because of fewer separate components), and a number of other advantages. o Further development, driven by the same economic factors, led to "Large-Scale Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip. Integrated circuits such as 1Kbit RAM, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had fewer than 4000 transistors. True LSI circuits, approaching 10000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors. o The final step in the development process, starting in the 1980s and continuing on, was "Very Large-Scale Integration" (VLSI), with hundreds of thousands of transistors, and beyond (well past several million in the latest stages). For the first time it became possible to fabricate a CPU on a single integrated circuit, to create a microprocessor. In 1986 the first one megabit RAM chips were introduced, which contained more than one million transistors. Microprocessor chips produced in 1994 contained more than three million transistors. This step was largely made possible by the codification of "design rules" for the CMOS technology used in VLSI chips, which made production of working devices much more of a systematic endeavor.
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o To reflect further growth of the complexity, the term ULSI that stands for "Ultra-Large Scale Integration" was proposed for chips of complexity more than 1 million of transistors. However, there is no qualitative leap between VLSI and ULSI, hence normally in technical texts the "VLSI" term covers ULSI as well, and "ULSI" is reserved only for cases when it is necessary to emphasize the chip complexity, e.g. in marketing. The most extreme integration technique is wafer-scale integration (WSI), which uses whole uncut wafers containing entire computers (processors as well as memory). Attempts to take this step commercially in the 1980s (e.g. by Gene Amdahl) failed, mostly because of defectfree manufacturability problems, and it does not now seem to be a high priority for the industry. The WSI technique failed commercially, but advances in semiconductor manufacturing allowed for another attack on IC complexity, known as System-on-Chip (SOC) design. In this approach, components traditionally manufactured as separate chips to be wired together on a printed circuit board are designed to occupy a single chip that contains memory, microprocessor(s), peripheral interfaces, Input/Output logic control, data converters, and other components, together composing the whole electronic system.
Technology IC can be made by using either MOSFET (metal-oxide-semiconductorfield-effect-transistor) or bipolar junction transistor. IC using MOSFET is CMOS (complimentary MOS) while IC using bipolar transistor is TTL (transistor-transistor-logic). Combination of both technologies is BiCMOS.
8.2 IC CHARACTERISTIC AND PARAMETER DC Supply Voltage The nominal DC supply voltage for a TTL device is 5V while CMOS device has several different supply voltages (5V, 3.3V, 2.5V and 1.2V) depending on the categories. This supply voltage are distributed internally to all element within the IC.
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Logic Level There are four logic level in IC specifications: VIL(max) : Low-level Input Voltage. The maximum input value (in volt) that the IC will interpret as LOW (0). Value higher than this will not be accepted as LOW (0) VIH(min) : High-level Input Voltage The minimum input value (in volt) that the IC will interpret as HIGH (1). Value lower than this will not be accepted as HIGH (1) VOL(max): Low-level Output Voltage The maximum voltage level at the IC output when in LOW (0) state under defined load condition. VOH(min): High-level Output Voltage The minimum voltage level at the IC output when in HIGH (1) state under defined load condition. Figure 8.8 Typical parameter for a 5V CMOS IC
5V
5V HIGH (1)
4.4V
VIH
VOH(min)
Undefined
1.5V
VIL(max) LOW (0)
VIL
0.33V
0V
0V
3.3V
3.3V HIGH (1)
VIH
2V
LOW (0)
VOL
HIGH (1)
VOH
2.4V
VOL(max)
VOH(min)
VIH(min) Undefined
Undefined VIL(max)
0.8V LOW (0) 0V
VOH
VIH(min)
3.3V Undefined
Figure 8.9 Typical parameter for a 3.3V CMOS IC
HIGH (1)
VIL
0.4V 0V
LOW (0)
VOL
VOL(max)
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Figure 8.10 Typical parameter for a 5V TTL IC
5V
5V
HIGH (1)
HIGH (1)
VIH
VOH
2.4V 2V
Undefined
Undefined 0.8V
VOH(min)
VIH(min)
VIL(max) LOW (0)
0V
VIL
0.4V 0V
LOW (0)
VOL
VOL(max)
Noise Immunity Noise is unwanted signal that practically exist in all electrical devices and can prevent circuit from operating properly. Noise can be generated internally or be pick-up externally. An IC must be able tolerate certain amount of noise. Referring to figure 8.10, an input voltage for HIGH (1) logic level may fluctuate between 2V and 5V, and still be interpreted as HIGH (1). But, once its drop below 2V (the VIH(min)), it will goes into the undefined range, and the output is unpredictable.
Noise Margin Circuit noise immunity are called noise margin, and measured in volt. There are two parameter for noise immunity:
High-level noise margin (VNH) = VOH(min)-VIH(min)
Low-level noise margin (VNL) = VIL(min)-VOL(min)
Power Dissipation Logic gate will drawn current from the DC supply voltage. There are two type of current:
ICCH: current drawn when the gate output is HIGH (1)
ICCL: current drawn when the gate output is LOW (0)
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Therefore, the power dissipation for a gate with HIGH (1) output is:
PD VCC I CCH When the gate is pulsed, with 50% duty cycle, the output will be 50% in HIGH (1) states and 50% in LOW (0) states. Therefore, the average supply current is:
I CC
I CCH I CCL 2
and the average power dissipation is: PD(ave) VCC I CC
Propagation Delay When signal passed through a gate, time delay will occurs. There are two types of time delay, tPHL and tPLH. (refer to chapter 5 in subtopic Flipflop characteristic).
Speed Power Product As the name implies, it is the product of power and time. This parameter are used when both speed and power are critical aspect in selecting types of IC for a design. The lower the speed power product value is better. Loading and Fan-Out When the output of a logic gates is connected to the input of one or more gates, a load will be created. The limit of how many gates can be connected is called the fan-out. CMOS Loading: CMOS are constructed from MOSFET that used a predominantly capacitive load to the driving gate (figure 8.11). The more load gate are connected to the driving gate, the total capacitance will increase (because s effectively appear as parallel) thus reducing the maximum frequency the gate can operate (fmax)
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Figure 8.11 Capacitive loading of CMOS gate
+ 5V LOW
HIGH
IDISCHARGE
ICHARGE
Charging
Discharging
TTL Loading: A TTL driving gate source current to load gate input in HIGH (1) state and sinks current from the load gate in LOW (0) state.
Figure 8.12 Current sourcing and sinking of TTL gate
+ 5V
+ 5V 1 1
HIGH IIH
Current Sourcing
0
LOW IIL
Current Sinking
As more load added, the total source current will increase, and the internal voltage drop of the driving gate will also increase. This will decrease the output voltage. If the output voltage drop below the VOH(min), the noise margin are reduce, thus compromising the circuit operation. Increasing load will also increase the power dissipation in the driving gate. The maximum number of load is called a unit load. As more load added, the total sinking current will increase, and the internal voltage drop of the driving gate will also increase. This will increase the VOL and if it exceeds the VOL(max), the noise margin are reduce, thus compromising the circuit operation.
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8.3 MOSFETs The metal-oxide-semiconductor field-effect transistor (MOSFET), is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOSFET, pMOSFET, NMOS FET, PMOS FET, nMOS FET, pMOS FET). A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back into the same direction as the channel. Sometimes a broken line is used for enhancement mode and a solid one for depletion mode, but the awkwardness of drawing broken lines means this distinction is often ignored. Another line is drawn parallel to the channel for the gate. The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in. If the bulk is connected to the source (as is generally the case with discrete devices) it is angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS. Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols:
Figure 8.13 NMOS and PMOS symbol
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n-Channel MOSFET transistors
With no voltage between the gate terminal and the substrate, there are two junctions between the two n regions and the p region. This acts like two oppositely connected diodes, and no current can flow between the source and the drain. Application of a positive voltage between the gate terminal and the substrate creates an electric field that drives Holes out of the region under the gate, creating a channel of n-type material that connects the source and drain terminals. Current is due to electron movement Tap analogy Sub-threshold, linear, and saturation regions of operation Standard notation that you will encounter includes supply voltage VDD, gate-to-source voltage VGS, drain-to-source voltage VDS, and threshold voltage VT
Figure 8.14 NMOS structure and operation
p-Channel MOSFET transistors The p and n regions are reversed from the n-Channel device.
Application of a voltage on the gate terminal that is negative relative to the substrate creates a p channel beneath The gate and charge flow is due to hole movement.
Figure 8.15 PMOS structure
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The general model for implementation of gates hinges on the use of passive versus active pull-up Figure 8.16 Pull-up and Pull-down network general model
The boxes labeled T and T‟ contain switches connected in such a way that they establish a connection between the top and bottom terminals when the input signals take on certain values and cause an open circuit if the input signals take on any other values.
The two networks in the active pullup circuit must be be designed so that they are never both conducting or are both open at the same time (recall the definition of complementary MOS).
Figure 8.17 Active and passive Pullup network general model
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nMOS and CMOS logic families Figure 8.18 NMOS logic family
Figure 8.19 CMOS logic family
Properties of nMOS and CMOS gates
No current flows through the gate unless the input signal is changing High input impedance High fanout Sandwich structure of MOS transistor creates capacitor between the gate and substrate High input capacitance that slows transition time (switching speed) and limits fan-out nMOS dissipates power in low output state The faster a CMOS gate switches the more power it dissipates, so there is a tradeoff between CMOS gate only dissipates power when it is changing state
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8.4 TRANSISTOR-TRANSISTOR-LOGIC (TTL) The fundamental switching action of a TTL gate is based on a multipleemitter input transistor. This replaces the multiple input diodes of the earlier DTL, with improved speed and a reduction in chip area. The active operation of this input transistor removes stored charge from the output stage transistors more rapidly than a comparable DTL gate, making TTL much faster in switching. A small amount of current must be drawn from a TTL input to ensure proper logic levels. The total current draw must be within the capacities of the preceding stage, which limits the number of nodes that can be connected. All standardized common TTL circuits operate with a 5 volt power supply. A TTL signal is defined as "low" or L when between 0V and 0.8V with respect to the ground terminal, and "high" or H when between 2V and 5V. Standardization of TTL devices was so successful that it is routine for a complex circuit board to contain chips made by many manufacturers, based on availability and cost rather than interoperability restrictions. Like most integrated circuits of the period 1960-1990, TTL devices are usually packaged in through-hole, dual in-line packages with between 14 and 24 lead wires, made usually of epoxy plastic but also commonly ceramic. Other packages included the flat-pack, used for military and aerospace applications, and beam-lead chips without packages for assembly into larger arrays. As surface-mounted devices became more common through the 1990's, most popular TTL devices were made available in these packages. Figure 8.20 show a standard TTL inverter circuit. In this figure,
Q1: input coupling transistor D1: input clamp diode Q2: phase splitter Q3 and Q4: totem pole arrangement
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Figure 8.20 Standard TTL inverter circuit
+5V R1
R2
R3
4kΩ
1.6kΩ
130Ω
Q4 INPUT
D2
Q2
Q1
OUTPUT
D1
Q3 R4 1kΩ
The two figures below shows the operation of this TTL inverter. Figure 8.21 Case 1: INPUT=LOW
Input is LOW; voltage at the base of Q1 is 0.7V causing Q1 to be in ON state, thus, the collector of Q1 is 0V.
+5V
R3 0.7V IC=0
LOW (0V)
ON
OFF
D2 HIGH
0V
D1
OFF
Base of Q2 is 0V, thus it‟s in OFF state. This cause the voltage at the base of Q4 and Q3 are 5V and 0V respectively. Thus, Q4 is ON while Q3 is OFF. As a result, OUTPUT is HIGH.
Figure 8.22 Case 2: INPUT=HIGH
Input is HIGH; Q1 is reversed biased, thus, the base of Q2 is 1.4V and Q2 is in ON state.
+5V R3 2.1V IC=0 1.4V
HIGH D1
≈0.7V
ON
OFF D2 LOW
0.7V
ON
This cause the voltage at the base of Q4 about/less than 0.7V, not enough to turn it ON while Q3 is ON because the voltage of its base is 0.7V. As a result, OUTPUT is LOW.
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Figure 8.23 TTL NAND gate
+5V
R1
R2
R3
Q4
A
Q1
Q2
B
OUT Q3 R4
8.5 PROGRAMMABLE LOGIC DEVICES A programmable logic device or PLD is an electronic component used to build digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit it must be programmed. Using ROM as Programmable Device Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary combinatorial logic functions of a number of inputs. Consider a ROM with m inputs (the address lines) and n outputs (the data lines). When used as a memory, the ROM contains 2m words of n bits each. Now imagine that the inputs are driven not by an m-bit address, but by m independent logic signals. Theoretically, there are 2m possible Boolean functions of these m signals, but the structure of the ROM allows just n of these functions to be produced at the output pins. The ROM therefore becomes equivalent to n separate logic circuits, each of which generates a chosen function of the m inputs. The advantage of using a ROM in this way is that any conceivable function of the m inputs can be made to appear at any of the n outputs, making this the most general-purpose combinatorial logic device available. Also, PROMs (programmable ROMs), EPROMs (ultravioleterasable PROMs) and EEPROMs (electrically erasable PROMs) are available that can be programmed using a standard PROM programmer without requiring specialized hardware or software. However, there are several disadvantages:
they are usually much slower than dedicated logic circuits, they cannot necessarily provide safe "covers" for asynchronous logic transitions, 154
they consume more power, and because only a small fraction of their capacity is used in any one application, they often make an inefficient use of space.
Stand alone they cannot be used for sequential logic, because they contain no flip-flops. An external TTL register was often used for sequential designs such as state machines. Common EPROMs, for example the 2716, are still sometimes used in this way by hobby circuit designers, who often have some lying around. This use is sometimes called a 'poor man's PAL'. Early Programmable Logic In 1970, Texas Instruments developed a mask-programmable IC based on the IBM read-only associative memory or ROAM. This device, the TMS2000, was programmed by altering the metal layer during the production of the IC. The TMS2000 had up to 17 inputs and 18 outputs with 8 JK flip flop for memory. TI coined the term Programmable Logic Array for this device. In 1973 National Semiconductor introduced a mask-programmable PLA device (DM7575) with 14 inputs and 8 outputs with no memory registers. This was more popular than the TI part but cost of making the metal mask limited its use. The device is significant because it was the basis for the field programmable logic array produced by Signetics in 1975, the 82S100. (Intersil actually beat Signetics to market but poor yield doomed their part.) In 1971, General Electric Company (GE) was developing a programmable logic device based on the new PROM technology. This experimental device improved on IBM's ROAM by allowing multilevel logic. Intel had just introduced the floating-gate UV erasable PROM so the researcher at GE incorporated that technology. The GE device was the first erasable PLD ever developed, predating the Altera EPLD by over a decade. GE obtained several early patents on programmable logic devices. In 1974 GE entered into an agreement with Monolithic Memories to develop a mask- programmable logic device incorporating the GE innovations. The device was named the 'Programmable Associative Logic Array' or PALA. The MMI 5760 was completed in 1976 and could implement multilevel or sequential circuits of over 100 gates. The device was supported by a GE design environment where Boolean equations would be converted to mask patterns for configuring the device. The part was never brought to market.
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PAL: Programmable Array Logic MMI introduced a breakthrough device in 1978, the Programmable Array Logic or PAL. The architecture was simpler than that of Signetics FPLA because it omitted the programmable OR array. This made the parts faster, smaller and cheaper. They were available in 20 pin 300 mil DIP packages while the FPLAs came in 28 pin 600 mil packages. The PAL Handbook demystified the design process. The PALASM design software (PAL Assembler) converted the engineers' Boolean equations into the fuse pattern required to program the part. The PAL devices were soon second-sourced by National Semiconductor, Texas Instruments and AMD. After MMI succeeded with the 20-pin PAL parts, AMD introduced the 24pin 22V10 PAL with additional features. After buying out MMI (1987), AMD spun off a consolidated operation as Vantis, and that business was acquired by Lattice Semiconductor in 1999.
GAL: Generic Array Logic An innovation of the PAL was the generic array logic device, or GAL, invented by Lattice Semiconductor in 1985. This device has the same logical properties as the PAL but can be erased and reprogrammed. The GAL is very useful in the prototyping stage of a design, when any bugs in the logic can be corrected by reprogramming. GALs are programmed and reprogrammed using a PAL programmer, or by using the in-circuit programming technique on supporting chips. A similar device called a PEEL (programmable electrically erasable logic) was introduced by the International CMOS Technology (ICT) corporation in 1999.
CPLD: Complex Programmable Logic Device PALs and GALs are available only in small sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLDs or CPLDs can be used. These contain the equivalent of several PALs linked by programmable interconnections, all in one integrated circuit. CPLDs can replace thousands, or even hundreds of thousands, of logic gates. Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins. A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal
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computer. The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function. Each manufacturer has a proprietary name for this programming system. For example, Lattice Semiconductor calls it "in-system programming". However, these proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG)
FPGA: Field Programmable Logic Array While PALs were busy developing into GALs and CPLDs (all discussed above), a separate stream of development was happening. This type of device is based on gate-array technology and is called the fieldprogrammable gate array (FPGA). Early examples of FPGAs are the 82s100 array, and 82S105 sequencer, by Signetics, introduced in the late 1970s. The 82S100 was an array of AND terms. The 82S105 also had Flip Flop functions. FPGAs use a grid of logic gates, similar to that of an ordinary gate array, but the programming is done by the customer, not by the manufacturer. The term "field-programmable" may be obscure to some, but "field" is just an engineering term for the world outside the factory, where customers live. FPGAs are usually programmed after being soldered down to the circuit board, in a manner similar to that of larger CPLDs. In most larger FPGAs the configuration is volatile, and must be re-loaded into the device whenever power is applied or different functionality is required. Configuration is typically stored in a configuration PROM or EEPROM. EEPROM versions may be in-system programmable (typically via JTAG). FPGAs and CPLDs are often equally good choices for a particular task. Sometimes the decision is more an economic one than a technical one, or may depend on the engineer's personal preference or experience.
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Program in PLD A PLD is a combination of a logic device and a memory device. The memory is used to store the pattern that was given to the chip during programming. Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. These include: Silicon antifuses SRAM EPROM or EEPROM cells Flash memory Silicon antifuses are the storage elements used in the PAL, the first type of PLD. These are connections that are made by applying a voltage across a modified area of silicon inside the chip. They are called antifuses because they work in the opposite way to normal fuses, which begin life as connections until they are broken by an electric current. SRAM, or static RAM, is a volatile type of memory, meaning that its contents are lost each time the power is switched off. SRAM-based PLDs therefore have to be programmed every time the circuit is switched on. This is usually done automatically by another part of the circuit. An EPROYM cell is a MOS (metal-oxide-semiconductor) transistor that can be switched on by trapping an electric charge permanently on its gate electrode. This is done by a PAL programmer. The charge remains for many years and can only be removed by exposing the chip to strong ultraviolet light in a device called an EPROM eraser. Flash memory is non-volatile, retaining its contents even when the power is switched off. It can be erased and reprogrammed as required. This makes it useful for PLD memory. As of 2005, most CPLDs are electrically programmable and erasable, and non-volatile. This is because they are too small to justify the inconvenience of programming internal SRAM cells every time they start up, and EPROM cells are more expensive due to their ceramic package with a quartz window.
PLD Programming Language Many PAL programming devices accept input in a standard file format, commonly referred to as 'JEDEC files'. To assist the creation of such files, special computer programs have been created, called logic compilers. They are analogous to software compilers. The languages used as source code for logic compilers are called hardware description languages, or HDLs.
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PALASM and ABEL are frequently used for low-complexity devices, while Verilog and VHDL are popular higher-level description languages for more complex devices. The more limited ABEL is often used for historical reasons, but for new designs VHDL is more popular, even for low-complexity designs.
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