Mazidi Solution Sol0_4

Online Instruc Instruc tor’ s Manual Manual to accompany

THE 8051 MICROCONTROLLER: A SYSTEMS APPROACH Muhammad Ali Mazidi Janice Gillispie Mazidi Rolin McKinlay

With contributions from Ardeshir Eslami and Sepehr Naimi

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Copyright 2013 Pearson Education, Inc., publishing as Prentice Hall, 1 Lake Street, Upper Saddle River, New Jersey, 07458. 07458. All rights reserved. Manufactured in the United States of America. This publication is protected by Copyright, and permission should be obtained from the pu blisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. To obtain permission(s) to use material from this work, please submit a written request to Pearson Education, Inc., Permissions Department, 1 Lake Street, Upper Saddle River, New Jersey 07458.

All rights reserved. Instructors of classes using Mazidi, Mazidi, and McKinlay, The 8051 Microcontroller: A Systems Approach, may be reproduced material from the instructor’s manual for classroom use. Otherwise, no part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher.

10 9 8 7 6 5 4 3 2 1

ISBN13: 978-0-13-508443-4 978-0-13-508443-4 ISBN10: 0-13-508443-1

CHAPTER 0: INTRODUCTION TO COMPUTING Sectio n 0.1: Numbering and Coding Systems 1. (a) 1210 = 11002 (b) 12310 = 0111 10112 (c) 6310 = 0011 11112 (d) 12810 = 1000 00002 (e) 100010 = 0011 1110 10002 2. (a) 1001002 = 3610 (b) 10000012 = 6510 (c) 111012 = 2910 (d) 10102 = 1010 (e) 001000102 = 3410 3. (a) 1001002 = 2416 (b) 10000012 = 4116 (c) 111012 = 1D16 (d) 10102 = 0A16 (e) 001000102 = 2216 4. (a) 2B916 = 0011 1011 10012, 69710 (b) F4416 = 1111 0100 01002, 390810 (c) 91216 = 1001 0001 00102, 232210 (d) 2B16 = 0010 10112, 4310 (e) FFFF16 = 1111 1111 1111 11112, 6553510 5. (a) 1210 = 0C16 (b) 12310 = 7B16 (c) 6310 = 3F16 (d) 12810 = 8016 (e) 100010 = 3E816 6. (a) 1001010 = 0011 0110 (b) 111001 = 0000 0111 (c) 10000010 = 0111 1110 (d) 111110001 = 0000 1111 7. (a) 2C+3F = 6B (b) F34+5D6 = 150A (c) 20000+12FF = 212FF (d) FFFF+2222 = 12221

Instructor’s Manual for “The 8051 Microcontroller: A System Approach”

1

8.

(a) 24F-129 = 12616 (b) FE9-5CC = A1D16 (c) 2FFFF-FFFFF = 3000016 (d) 9FF25-4DD99 = 5218C16

9.

(a) Hex: 30, 31, 32 , 33, 34, 35, 36, 37, 38, 39 (b) Binary: 11 0000, 11 0001, 11 0010, 11 0011, 11 0100, 11 0101, 11 0110, 11 0111, 11 1000, 11 1001. ASCII (hex) Binary 30 011 31 011 32 011 33 011 34 011 35 011 36 011 37 011 38 011 39 011

0 1 2 3 4 5 6 7 8 9 10.

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

000000 22 55 2E 53 2E 41 2E 20 69 73 20 61 20 63 6F 75 000010 6E 74 72 79 22 0D 0A 22 69 6E 20 4E 6F 72 74 68 000020 20 41 6D 65 72 69 63 61 22 0D 0A

Section 0.2: Digital Primer 11.

A

1

B

2

3

4 6

C

5

12. A 0 0 0 0 1 1 1 1

2

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 1 1 1 1 1 1 1

"U.S.A. is a cou ntry".."in North America"..

13.

A

1

B

2

3

.

4 6

C

5

14. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 0 0 0 0 0 0 1

15.

A

1

B

2

3

4 6

C

5

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 0 1 1 0 1 0 0 1

16. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 1 1 1 1 1 1 1 0


3

17. A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Y 1 0 0 0 0 0 0 0

18. LSB

19. LSB

20. CLK No Yes Yes

D X 0 1

Q NC 0 1

Sectio n 0.3: Semiconduc tor Memory 21.

4

(a) 4 (b) 4 (c) 4 20 (d) 1 048 576, 2 (e) 1024K 30 (f) 1 073 741 824, 2 (g) 1 048 576 K (h) 1024M (i) 8388608, 8192K

22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37.

38.

1 million pages The storage of the chip is measured in Megabits while the Computer memory is measured in Megabytes. True, the more address lines the more memory locations. True, the memory location size is fixed. True, the more data lines the more memory locations True access time True electrically erasable True DRAM SRAM DRAM and SRAM (c) (c) (a) 32Kx8, 256K (f) 8Kx1, 8K (b) 8Kx8, 64K (g) 4Kx8, 32K (c) 4Kx8, 32K (h) 2Kx8, 16K (d) 8Kx8, 64K (i) 256Kx4, 1M (e) 4Mx1, 4M (j) 64Kx8, 512K (a) 128K 14 8 (f) 256K 8 4 (b) 256K 15 8 (g) 8M 20 8 (c) 512K 16 8 (h) 16M 11 4 (d) 2M 18 8 (i) 512K 16 8 (e) 512K 16 8

Sectio n 0.4: Bus Designi ng and Add ress Decodin g 39. 40. 41.

42.

43. 44.

(a) 589824 bytes (b) 576 kbytes 32 2 – 1 = 4294967295 (a) FFh, 255 (b) FFFFh, 65535 (c) FFFF FFFFh, 4 294 967 295 (d) FFFF FFFF FFFF FFFFh, 18 446 744 073 709 551 615 (a) 64K (b) 16M (c) 4096 Mega, 4G (d) 256 Tera, 262144 Giga, 268435456 Mega Data bus is bidirectional, address is unidirectional. 4000h - 7FFFh


5

45. A0

A11

A12

1 3

A13

46. 47.

1

2

~CS

2

8000h - 8FFFh, B000h - BFFFh, E000 - EFFFh A0

8kx8

A12

U?

A13 A14 A15 Vcc

1 2 3 6 4 5

A B

Y0N Y1N Y2N

C G1 G2AN

Y3N Y4N Y5N

G2BN

Y6N Y7N

15 14

~CS

13 12 11 10 9 7

74138

48. 49.

Each controls 8K bytes block 6000h - 7FFFh, C000h - DFFFh, E000h - FFFFh A0

32kx8

A14

U?

A15 A16 A17 Vcc

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N

15 14 13

~CS

12 11 10 9 7

74138

50. 51. 52. 53. 54.

6

Each controls 32K bytes block 4000h - 7FFFh, 8000h - BFFFh, C000h – FFFFh Tri-state buffer Latch The linear select Most often each port (or even memory) can be accessed by a single unique address. However, in address decoding, multiple addresses are assigned to a single port if some address lines are not used in the decoding circuitry. In this case, all the aliases refer to the same device just like a person with several names (aliases).

55. 56. 57.

the linear select Memory-mapped I/O uses the memory address space as I/O ports. True

58.

IOR

59. 60.

IOW

The diagram follows.

61. The diagram follows.


7

62. The following circuit shows an output circuit for Figure 0-30. 74LS373

D0

D

Q0

Q

System Data Bus

To LEDs

A0 D7

Q7

A15

63.

OC

G

System address bus

WR

Here is the drawing: 74LS244

D0

Switches

A0

8

D4

To system Data Bus

D7

Q7

G1

System Address Bus

A15

Q0

RD

G2

Section 0.6: CPU and Harvard Architecture 64. PC ( Program Counter ) 65. ALU 66. Address, control and data


9

CHAPTER 1: THE 8051 MICROCONTROLLERS Sectio n 1.1: Microc ontro llers and Embedded Processors 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

False: A general-purpose microprocessor does not have on-chip ROM. True: A microcontroller has on-chip ROM. True: A microcontroller has on-chip I/O ports. True: A microcontroller has a fixed amount of RAM on the chip. CPU, RAM, ROM, I/O, Timer, Serial COM port RAM and ROM Keyboard, mouse, printer Computing power and compatibility with millions and millions of PCs 8051 - Intel, 6811 – Freescale (Motorola), Z8 – Zilog, PIC 16x – Microchip Technology 8051 Power consumption The ROM area is where the executable code is stored Very, in case there is a shortage by one supplier Suppliers other than the manufacturer of the chip Only A is true, 8 bit software will run on a 16 bit system

Secti on 1.1: Overview of the 8051 Family 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27.

28. 29. 30.

10

4096 bytes 128 bytes 2 timers 256 bytes 8031 32 pins 1 serial port UV-EPROM EEPROM NV-RAM Flash (a) 4K ROM, 128 Bytes of RAM (b) 16K ROM, 256 Bytes RAM (c) 32K ROM, 256 Bytes RAM The OTP version of the 8051 The 8031 does not have on-chip ROM. DS89C420/430 are the best for home development, because you can program it serially using IBM PC.

CHAPTER 2: 8051 ASSEMBLY LANGUAGE PROGRAMMING

Secti on 2.1: Inside the 8051 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

8 8 8 DPTR or PC (program counter) Necessary 28H, A (a), (d), (f), and (g) (a), (c), (d), (f), and (g) 44H, A 1EH, A

Sectio n 2.2: Introd uctio n to Assembly Programming and Section 2.3: Assembling and Running an 8051 Program 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.

Low, high Assembly language Assembler program True List file False True No They are not real code (real code produces op code). Pseudo-instructions only give instruction to the assembler and does not generate opcodes. True

Secti on 2.4: The Progr am Counter and ROM Space in the 8051 21. 22. 23.

0000H It executes whatever is at location 0000h which could be garbage in this case. (a) 2 bytes (b) 2 bytes (c) 1 byte (d) 2 bytes (e) 1 byte (f) 1byte (g) 1 byte


11

24. 0000 0000 0002 0004 0006 0007 0008 000A 000C

7D25 7F34 7400 2D 2F 2412 80FE

25.

(a) (b) (c) (d) (e) (f) (g)

26. 27. 28.

0000h, FFFFh 32K 1K

ORG 0h MOV R5, #25h MOV R7, #34h MOV A, #0 ADD A, R5 ADD A, R7 ADD A, #12h HERE: SJ MP HERE END

3FFFh (16K) 1FFFh (8K) 7FFFh (32K) 1FFFh (8K) 0FFFh (4K) 0FFFh (4K) FFFFh (64K)

Secti on 2.5: 8051 Data Types and Directives 29. 0200 0200 0204 0205 0209 020B 020F

45617274 68 3938372D 3635 47414245 48203938

1 2

ORG 200H MYDATA_1:

DB " Ear t h"

3

MYDATA_2:

DB " 987- 65"

4

MYDATA_3:

DB " GABEH 98"

5 6

END

1 2

ORG 340H DAT_1: DB 22, 56H, 10011001B, 32, 0F6H, 11111011B

3

END

30. 0340 0340 0344

16569920 F6FB

All in hex where contents of each location are: 340=( 22) , 341=( 56) , 342=( 99) , 343=( 20) , 344=( F6) , 345=( FB)

12

Secti on 2.6: 8051 Flag Bits and th e PSW Register 31. 32. 33. 34. 35. 36. 37.

8 D7, D6 D2, D0 when there is a carry from D7 when there is a carry from D3 to D4 CY = 1 (a) CY = 1 (b) CY = 0 (c) CY = 0

38. ORG 0H MOV R0, #5 MOV A, #0 HERE: ADD A, #55h DJ NZ R0, HERE END

Secti on 2.7: 8051 Regis ter Banks and Stack 39. 40. 41. 42. 43. 44. 45.

46.

47. 48.

D3, D4 08 Bank 1 8 Bits Bank 0 Bank 0:00h-07h, Bank 1: 08h-0Fh, Bank 2: 10h-17h, Bank 3: 18h-1Fh (a) RAM Location 04 (b) RAM Location 00 (c) RAM Location 07 (d) RAM Location 05 (a) RAM Location 14h (b) RAM Location 10h (c) RAM Location 17h (d) RAM Location 15h SETB PSW.4 I NSTRUCTI ON ORG MOV MOV MOV

0 R0, #66H R3, #7FH R7, #5DH

SP af t er execut i on of t he i ns t r uc t i on 07H 07H 07H 08H

Cont ent s of t he St ack ? ? 66H 7FH


13

PUSH PUSH PUSH CLR MOV MOV POP POP POP

49.

NO,

0 3 7 A R3, A R7, A 3 7 0

09H 0AH 0AH 0AH 0AH 0AH 09H 08H 07H

5DH 5DH 5DH 5DH 5DH 5DH 7FH 66H 7FH

SP af t er execut i on of t he i ns t r uc t i on 07H 70H 70H 70H 70H 71H 72H 73H 73H 73H 73H 72H 71H 70H

Cont ent s of t he St ack ? ? ? ? ? 66H 7FH 5DH 5DH 5DH 5DH 7FH 66H ?

pop 7 pop 3 pop 0

50. I NSTRUCTI ON ORG MOV MOV MOV MOV PUSH PUSH PUSH CLR MOV MOV POP POP POP

0 SP, #70H R5, #66H R2, #7FH R7, #5DH 5 2 7 A R2, A R7, A 7 2 5

SECTION 2.8: RISC ARCHITECTURE

51. 52. 53. 54. 55.

14

RISC stands for "Reduced Instruction Set Computer". CISC stands for "Complex (or Complete) Instruction Set Computer". CISC RISC RISC CISC

CHAPTER 3: JUMP, LOOP, AND CALL INSTRUCTIONS

Sectio n 3.1: Loop and Jump Instru ction s 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.

256 the instruction following the jump PC short jump, 2 long jump, 3 less ROM space is consumed True False c, LJMP is not a short jump. 2, because it can only go –128 to 127 bytes in the program True MOV R6, #10 BACK: MOV R5, #100 HERE: DJ NZ R5, HERE DJ NZ R6, BACK

13. MOV R6, #10 BACK: MOV R5, #100 AGAI N: MOV R4, #100 HERE: DJ NZ R4, HERE DJ NZ R5, AGAI N DJ NZ R6, BACK

14. 15. 16.

20,000 128 127

Sectio n 3.2: Call Instruct ions 17. 18. 19. 20. 21. 22.

3 2 2K 64K 2 bytes 2 bytes


15

23.

24. 25.

26.

They need to be equal (in order for the stack to remain unchanged) so that when the RET instruction is executed it goes back to place where it originated; otherwise, it returns to a wrong place. When POP is executed, the contents of the stack are copied to the destination register and SP is decremented by one. SP Stack content 09 (00) 08 (0E) SP Stack content 0B (67) 0A (99) 09 (02) 08 (0B)

Secti on 3.3: Time Delay Generation f or Vario us 8051 Chips 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40.

16

10 MHz 0.667 s 1 s 0.480 s True, both instructions take 2 machine cycles to execute. 813.75 s 750 s ((4 x 250) x (200 x 100)) x 1.085 s = 21.7 seconds (250 x 150) x 5 x 0.75 s = 140625 s Duration of each machine cycle: 1/(11.0592MHz) = 90.422 ns Number of machine cycles: (1 + 1 + 1 + 4) x 150 x 90.422ns = 94.944 s 1 / 16MHz = 62.5 ns (1+1+1+4) x 200 x 62.5 ns = 87.5s (1+1+4) x 250 x 200 x 100 x 90.422 ns = 2.713 seconds (7 x 250) x 150 x 62.5 ns = 16.406 ms Although the period of each machine cycle is twelve times shorter in DS89C420/30, the fact that the execution of many instructions take more number of machine cycles than in AT89C51, does not allow the performance to become twelve times faster in DS89C420/30. As an example, if you divide the answer of Problem 35 by the answer of Problem 39, we can figure out that in this particular case, DS89C420/30 is almost 8.6 times faster than AT89C51, not 12 times faster.

CHAPTER 4: I/O PORT PROGRAMMING Secti on 4.1: 8051 I/O Programm ing 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

40 Pins 40, 20 are assigned to Vcc and Gnd, respectively. 32 8 Pins, 39-32, are designated for P0. 8 Pins, 01-08, are designated for P1. 8 Pins, 21-28, are designated for P2. 8 Pins, 10-17, are designated for P3. output P0 P1 ORG 0000h MOV A, #0FFH MOV P1, A MOV A, P1 MOV P0, A MOV P2, A MOV P3, A HERE: SJ MP HERE END

12. ORG 0000h MOV A, #0FFH MOV P2, A MOV A, P2 MOV P0, A MOV P1, A HERE: SJ MP HERE END

13. 14.

10 and 11 0000h; This means that the starting of the code must begin at location 0000h. In other words it belongs to code ROM.


17

15.

(a)

(b) ORG 0000h

ORG 0000h

AGAI N:

MOV A, #55h MOV A, #55h MOV P1, A MOV P2, A ACALL DELAY MOV A, #0AAh MOV P1, A MOV P2, A ACALL DELAY SJ MP AGAI N

AGAI N: MOV P1, A MOV P2, A ACALL DELAY CPL A SJ MP AGAI N END

END

Sectio n 4.2: I/O Bit Manipulation Progr amming 16. All ports of the 8051 are bit addressable. 17. The advantage of the bit addressing is that it allows each bit to be modified without affecting the other bits. 18. P1.x 19. No, CPL P1 is not a valid instruction because CPL works with register A and individual bits. 20. ORG 0000h AGAI N: SETB P1. 2 SETB P1. 5 ACALL DELAY CLR P1. 2 CLR P1. 5 ACALL DELAY SJ MP AGAI N END

18

21. ORG 0000h AGAI N: SETB P1. 3 SETB P1. 7 SETB P2. 5 ACALL DELAY CLR P1. 3 CLR P1. 7 CLR P2. 5 ACALL DELAY SJ MP AGAI N END

22. ORG 0000h SETB P1. 3 AGAI N: J NB P1. 3, AGAI N MOV A, #55h MOV P2, A HERE: SJ MP HERE END

23. ORG 0000h SETB P1. 3 AGAI N: J B P1. 3, AGAI N HERE: MOV A, #55h MOV P0, A ACALL DELAY MOV A, #0AAh MOV P0, A ACALL DELAY SJ MP HERE END


19

24. ORG 0000h SETB AGAI N: J B MOV MOV SJ MP HERE: MOV MOV SJ MP END

P2. 0 P2. 0, HERE A, #66H P1, A AGAI N A, #99H P1, A AGAI N

25. ORG 0000h SETB P1. 5 AGAI N: J NB P1. 5, AGAI N CLR P1. 3 SETB P1. 3 CLR P1. 3 HERE: SJ MP HERE END

26. ORG 0000h SETB P1. 3 AGAI N: J B

P1. 3, HERE

CLR P1. 4 SJ MP AGAI N HERE: SETB P1. 4 SJ MP AGAI N END

27.

20

The fifth bit of port 1.

28. ORG

0000H

SETB P1. 7 SETB P1. 6 AGAI N: J B P1. 7, HERE CLR P1. 0 SJ MP NEXT HERE: SETB P1. 0 NEXT: J B P1. 6, COPY CLR P1. 7 SJ MP AGAI N COPY: SETB P1. 7 SJ MP AGAI N END


21

Mazidi Solution Sol0_4

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