Online Instructor’s Manual to accompany
HCS12 Microcontroller and Embedded Systems: Using Assembly and C with CodeWarrior 1st Edition
Muhammad Ali Mazidi Danny Causey
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___________________________________________________________________________________________ Copyright © 2009 Pearson Education, Inc., publishing as Prentice Hall, Upper Saddle River, New Jersey and Columbus, Ohio. All rights reserved. Manufactured in the United States of America. This publication is protected by Copyright, and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. To obtain permission(s) to use material from this work, please submit a written request to Pearson Education, Inc., Permissions Department, One Lake Street, Upper Saddle River, New Jersey. Many of the designations by manufacturers and seller to distinguish their products are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed in initial caps or all caps.
10 9 8 7 6 5 4 3 2 1
ISBN-13: 978-0-13-504837-5 ISBN-10: 0-13-504837-0
CHAPTER 0: INTRODUCTION TO COMPUTING SECTION 0.1: NUMBERING AND CODING SYSTEMS 1. (a) 12 10 = 1100 2 (b) 123 10 = 0111 1011 2 (c) 63 10 = 0011 1111 2 (d) 128 10 = 1000 0000 2 (e) 1000 10 = 0011 1110 1000 2 2. (a) 100100 2 = 36 10 (b) 1000001 2 = 65 10 (c) 11101 2 = 29 10 (d) 1010 2 = 10 10 (e) 00100010 2 = 34 10 3. (a) 100100 2 = 24 16 (b) 1000001 2 = 41 16 (c) 11101 2 = 1D 16 (d) 1010 2 = 0A 16 (e) 00100010 2 = 22 16 4. (a) 2B9 16 = 0010 1011 1001 2 , 697 10 (b) F44 16 = 1111 0100 0100 2 , 3908 10 (c) 912 16 = 1001 0001 0010 2 , 2322 10 (d) 2B 16 = 0010 1011 2 , 43 10 (e) FFFF 16 = 1111 1111 1111 1111 2 , 65535 10 5. (a) 12 10 = 0C 16 (b) 123 10 = 7B 16 (c) 63 10 = 3F 16 (d) 128 10 = 80 16 (e) 1000 10 = 3E8 16 6. (a) 1001010 = 0011 0110 (b) 111001 = 0000 0111 (c) 10000010 = 0111 1110 (d) 111110001 = 0000 1111 7. (a) 2C+3F = 6B (b) F34+5D6 = 150A (c) 20000+12FF = 212FF (d) FFFF+2222 = 12221 8.
(a) 24F-129 = 126 16
(b) FE9-5CC = A1D 16 (c) 2FFFF-FFFFF = 30000 16 (d) 9FF25-4DD99 = 5218C 16 9.
(a) Hex: 30, 31, 32 , 33, 34, 35, 36, 37, 38, 39 (b) Binary: 11 0000, 11 0001, 11 0010, 11 0011, 11 0100, 11 0101, 11 0110, 11 0111, 11 1000, 11 1001. ASCII (hex) Binary 30 011 0000 31 011 0001 32 011 0010 33 011 0011 34 011 0100 35 011 0101 36 011 0110 37 011 0111 38 011 1000 39 011 1001
0 1 2 3 4 5 6 7 8 9 10. cou
000000 22 55 2E 53 2E 41 2E 20 69 73 20 61 20 63 6F 75
"U.S.A. is a
000010 6E 74 72 79 22 0D 0A 22 69 6E 20 4E 6F 72 74 68
ntry".."in
000020 20 41 6D 65 72 69 63 61 22 0D 0A
America"..
North SECTION 0.2: DIGITAL PRIMER 11.
A
1
B
2
3
4 6 C
5
12. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Y 0 1 1 1 1 1 1 1
13.
A
1
B
2
3
.
4 6 C
5
14. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Y 0 0 0 0 0 0 0 1
15. A
1
B
2
3
4 6 C
5
16. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Y 1 1 1 1 1 1 1 0
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Y 0 1 1 0 1 0 0 1
17. A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Y 1 0 0 0 0 0 0 0
D X 0 1
Q NC 0 1
18. LSB
19. LSB
20. CLK No Yes Yes
SECTION 0.3: SEMICONDUCTOR MEMORY 21.
(a) 4 (b) 4 (c) 4 (d) 1 048 576, 220 (e) 1024K (f) 1 073 741 824, 230 (g) 1 048 576 K (h) 1024M (i) 8388608, 8192K
22. 23. 24. 25.
26.
27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42.
43.
44. 45.
Disk storage capacity / size of a page = (2*230) / (25*80) = 1 million pages (a) 9FFFFh – 10000h = 8FFFFh = 589 824 bytes (b) 576 kbytes 232 – 1 = 4 294 967 295 (a) FFh, 255 (b) FFFFh, 65535 (c) FFFF FFFFh, 4 294 967 295 (d) FFFF FFFF FFFF FFFFh, 18 446 744 073 709 551 615 (a) 216 = 64K (b) 224 = 16M (c) 232 = 4096 Mega, 4G (d) 248 = 256 Tera, 262144 Giga, 268435456 Mega Data bus is bidirectional, address bus is unidirectional (exit CPU). The storage of the chip is measured in Megabits while the Computer memory is measured in Megabytes. True, the more address lines the more memory locations. True, the memory location size is fixed. True, the more data lines the more memory locations True access time True electrically erasable True DRAM SRAM DRAM and SRAM (c) (c) (a) 32Kx8, 256K (f) 8Kx1, 8K (b) 8Kx8, 64K (g) 4Kx8, 32K (c) 4Kx8, 32K (h) 2Kx8, 16K (d) 8Kx8, 64K (i) 256Kx4, 1M (e) 4Mx1, 4M (j) 64Kx8, 512K (a) 128K 14 8 (f) 256K 8 4 (b) 256K 15 8 (g) 8M 20 8 (c) 512K 16 8 (h) 16M 11 4 (d) 2M 18 8 (i) 512K 16 8 (e) 512K 16 8 4000h - 7FFFh A0
A11
A12
1 3
A13
1
2
2
~CS
46. 47.
8000h - 8FFFh, B000h - BFFFh, E000 - EFFFh A0
A12
8kx8 U?
A13 A14 A15 Vcc
1 2 3 6 4 5
A B C G1 G2AN G2BN
Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N
15 14 13 12 11 10 9 7
~CS
74138
48. 49.
Each controls 8K bytes block 6000h - 7FFFh, C000h - DFFFh, E000h - FFFFh A0
A14
32kx8 U?
A15 A16 A17 Vcc
1 2 3 6 4 5
A B C G1 G2AN G2BN
Y0N Y1N Y2N Y3N Y4N Y5N Y6N Y7N
15 14 13 12 11 10 9 7
~CS
74138
50.
Each controls 32K bytes block 4000h - 7FFFh, 8000h - BFFFh, C000h - FFFFh
SECTION 0.4: CPU AND HARVARD ARCHITECTURE
51. 52. 53.
PC ( Program Counter ) ALU is responsible for all arithmetic and logic calculations in the CPU. Address, control and data
SECTION 0.5: RISC ARCHITECTURE 54. 55.
RISC stands for "Reduced Instruction Set Computer". CISC stands for "Complex (or Complete) Instruction Set Computer". CISC
56. 57. 58.
RISC RISC CISC
CHAPTER 1: THE HCS12 MICROCONTROLLERS: HISTORY AND FEATURES SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
False. True. True. True. CPU, RAM, ROM, EEPROM, I/O, Timer, Serial COM port, ADC. RAM and ROM. Keyboard, mouse, printer. Computing power and compatibility with millions and millions of PCs. PIC 16x – Microchip Technology, 8051 - Intel, AVR – Atmel, Z8 – Zilog, 68HC11 – Freescale Semiconductor (Motorola). 8051. Power consumption. The ROM area is where the executable code is stored. Very, in case there is a shortage by one supplier. Suppliers other than the manufacturer of the chip. B is absolutely wrong, 16 bit software can not run on a 8 bit system due to special instructions and registers. But A can be true (in the case of software compatibility).
SECTION 1.2: OVERVIEW OF THE CPU12 AND CPU08 16. 17. 18. 19. 20. 21. 22. 23. 24.
512 Kbytes 64 Kbytes 8 Kbytes 4K K1bytes 2 Flash Flash (a) 14 Kbytes OTP (see the letter 'C')
(b) 12 Kbytes
(c) 2 Kbytes
CHAPTER 2: HCS12 ARCHITECTURE & ASSEMBLY LANGUAGE PROGRAMMING SECTION 2.1: INSIDE THE HCS12 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
16 8 8 FFH necessary The result is 28H, stored in Accumulator A. In (a) and (d) the operand exceeds allowed range. The syntax of (g) is wrong, since ADDA can have only one operand ( ADDA mybyte , or , ADDA #$50 ). (a), (c) and (d) exceed the allowed range. The result is 44H in accumulator A. The result is FFH in accumulator A. FFH False. There is only one register A and one register B.
SECTION 2.2: THE HCS12 MEMORY MAP 13. 14. 15. 16. 17. 18. 19. 20.
21. 22. 23. 24. 25. 26.
64KBytes True False. Registers are part of Register space. True False False. There are also Register Space and unused space. (a) 14 KBytes (b) 1 KBytes Data RAM is used to store temporary data, and when power goes off its information is lost. But, we use EEPROM to store nonvolatile data that must remain intact even when the power is turned off. Yes, some chips have no EEPROM, page 66. No, the HCS12 needs RAM for volatile data. Flash. 32 KBytes. 0000H Registers 000-3FFF, RAM 0800-3FFF, EEPROM 7000-7FFF, Code ROM C000-FFFF
SECTION 2.3: HCS12 ADDRESSING MODES 27. 28.
800H LDAA #$30 STAA $805 LDAA #$97 STAA $806
29.
30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42.
LDAA #$55 STAA $300 STAA $301 STAA $302 STAA $303 STAA $304 STAA $305 STAA $306 STAA $307 STAA $308 LDAA #5F STAA PORTB (b) LDAA $30 is Extended mode addressing. (a) Direct, (b) Immediate, (c) Extended, (d) Immediate, (e) Inherent, (f) Inherent (a) 3 Byte, (b) 2 Byte, (c) 3 Byte, (d) 2 Byte, (e) 1 Byte, (f) 1 Byte 0000H Direct Addressing Immediate Addressing Direct Addressing Extended Addressing Invalid 800H – 8FFH Registers X and Y True
SECTION 2.4: CONDITION CODE REGISTER 43. 44. 45. 46. 47. 48. 49.
50.
8 bit C = bit 0, H = bit 5 V = bit 1 , N = bit 3 The C flag = 1 when there is a carry out from the D7 bit after an 8-bit arithmetic operation. The H flag = 1 when there is a carry from the D3 to D4 bit after an 8-bit arithmetic operation. FFH + 1 = 100H, but since register A is only 8-bit the Z and C flags are both = 1. (a) 118H, so C = 1 (b) FFH, so C = 0 (c) 104H, so C = 1 LDAA #$55 ADDA #$55 ADDA #$55 STAA $1200
SECTION 2.5: HCS12 DATA FORMAT AND DIRECTIVES 51.
MYDAT_1 = 37H MYDAT_2 = 62H MYDAT_3 = 47H MYDAT_4 = 50H MYDAT_5 = C8H MYDAT_6 = 41H MYDAT_7 = AAH MYDAT_8 = FFH MYDAT_9 = 90H MYDAT_10 = 7EH MYDAT_11 = 0AH MYDAT_12 = 0FH
52.
DAT_1 = 16H DAT_2 = 56H DAT_3 = 99H DAT_4 = 20H DAT_5 = F6H DAT_6 = 7BH
53.
R0 EQU $300 R1 EQU $301 R2 EQU $302 R3 EQU $303 R4 EQU $304 R5 EQU $305 (a) LDAA #$11 STAA R0 STAA R1 STAA R2 STAA R3 STAA R4 STAA R5 (b) CLRA ADDA R0 ADDA R1 ADDA R2 ADDA R3 ADDA R4 ADDA R5
SECTION 2.6: INTRODUCTION TO HCS12 ASSEMBLY PROGRAMMING AND SECTION 2.7: ASSEMBLING AND LINKING A HCS12 PROGRAM 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67.
low - high Assembly. Assembler True. List file, with extension “ .lst “. False. False. END is optional for HCS12, but is good practice to make the code readable. No. Because they only tell the assembler what to do and do not generate any op-codes. True. False. True. The file with “ .s19 “ extension is downloaded. Three file extensions include: “ .asm “, “ .lst “, and “ .s19 “.
SECTION 2.8: STACK AND DATA TRANSFER INSTRUCTIONS 68. 69. 70. 71. 72.
The stack pointer points to the last used location. decremented, 2 incremented, 2 False, RAM is used for stack. True
