L'()C (ATE LA* +E,'+T *y: *renen Th"y"p"r"n
452600 TEJ3M0: Computer Technology Louise Arbour econ!"ry chool Mr# Lo$e Mon!"y M"y %2& 20%4
Table Of Contents
Title ,"ge ------------------------------------------------ % T"ble o. Contents -------------------------------------------# 2 ,urpose ----############ ----------------------------------------## 3 Aim ---------------------------------------------------## 3 )ntro!uction ----------------------------------------------## 3 M"teri"ls ------------------------------------------------# 3 ,roce!ure ---------------------------------------------- 4 / 5 'bser"tions --------------------------------------------# 6 / 1 iscussion Conclusion ----------------------------------------#
Purpose:
To investigate the each individual operations of Logic Gates.
Aim for each of the following labs: 6. To investigate the operation of an “AND” gate. 7. To investigate the operation of an “OR” gate. . To investigate the operation of a logic inverter !“NOT” gate". #. To investigate the operation of a “NAND” gate. $%. To investigate the operation of a “NOR” gate. $$. To investigate the operation of an “&'clusive OR” gate.
Introduction: The o()ective for conducting these e'peri*ents+ is to see ho, the operation of Logic Gates ,or-. urther*ore+ in order to see ho, these different logic gates ,or-+ the/ ,ill (e used in separate circuits and have their o,n truth ta(les+ so that it is easier to tell ho, the/ differ fro* each other+ and ho, the/ ,ould ,or-.
Materials: $ 0 17% oh* Resistor $ 0 L&D $ 0 71% Logic Gate !AND Gate" $ 0 7123 Logic Gate !OR Gate" $ 0 71%1 Logic Gate !4nverter" $ 5 71%% Logic Gate !Nand Gate" $ 5 71%3 Logic Gate !NOR Gate" $ 5 716 Logic Gate !&'clusive OR Gate" 7 ,ires $ atter/ $ 80 9% (read(oarding soc-et :ire stripper tool Needle Nose plier ;aper and ,riting utensil ;o,er uppl/
Procedure: 1. Gather all the rese the needle nose plier to pl/ off an/ un,anted coating of the )u*per ,ire on (oth ends !,hen doing this+ -eep in *ind that /ou need (oth ends of the ,ire+ to reach the (otto* of the (read(oard in order for the ,ire to *a-e connections (et,een pins in the (read(oarding soc-et". 4. ollo, the diagra*s and procedures on each la( sheet fro* La(s 60$$ in order to asse*(le the circuits. 5. ?erif/ if the resistor (eing used+ is a 17% oh* resistor+ (/ follo,ing this order@ % 0 lac• $ 5 ro,n • 3 5 Red • 2 5 Orange • 1 5 ello, • 9 5 Green • 6 5 lue • 7 5 ?iolet • 5 Gre/ • # 5 :hite •
!According to the a(ove list+ a 17% oh* resistor+ *ust have the follo,ing colours@ ello,+ ?iolet+ and ro,n in that precise order. Bust re*e*(er that the third colourCs value+ is the a*ount of eroes the resistor ,ill have+ ,hich in this case ,ould (e one ero." . Ea-e sure the positive end !the longer end" of the L&D (eing used+ is in the slot directl/ under the right end of the resistor in the (read(oarding circuit. !. =hec- if pin 7 of each logic gate for each la(+ is grounded. asicall/+ have a )u*per ,ire connected to the slot directl/ under pin 7 of the gate (eing used+ to the negative slot verticall/ (elo, it ,hich ,ould (asicall/ (e at the (otto* portion of the (read(oarding soc-et. ". No, chec- if pin $1 of each logic gate for each la(+ is connected to the input. asicall/+ have a )u*per ,ire connected to the slot directl/ a(ove pin $1 of the gate (eing used+ to the positive slot verticall/ a(ove it ,hich ,ould (asicall/ (e at the top portion of the (read(oarding soc-et. #. :hen the asse*(ling of the circuit created on the (read(oard is co*plete+ the ne't step is too connect the (read(oard soc-et to the po,er suppl/ via )u*per ,ires. !=onnect a
)u*per ,ire to an/ positive slot on the po,er suppl/ to a positive slot on the (read(oard circuit+ and do the sa*e thing ,ith another )u*per ,ire+ e'cept this ti*e+ connect the* to the negative slots". 1$. ,itch the inputs A and ,hich ,ould (e located verticall/ under ,ithin the first 2 pins of each Logic Gate+ to lo, and high !% %+ % $+ $ %+ $ $"+ to see ho, it effects the output results. 11. Record our O(servations and create a Truth Ta(le to record ho, the different inputs effect the outputs. 12. Repeat steps 3 5 $$+ ,ith the other Logic gates !integrated chips"+ and change each circuit according to the each individual la(.
%bser&ations:
Truth Ta(les $F On F igh % F Off F Lo, La( 6 Gate@
La( H I Na*e La( 6 !AND Gate"
4nput A %
4nput %
Output !L&D" %
%
$
%
$
%
%
$
$
$
La( 7 Gate@
La( H I Na*e
4nput A
4nput
Output !L&D"
La( 7 !OR Gate"
%
%
%
%
$
$
$
%
$
$
$
$
La( Gate@
La( H I Na*e
4nput A
4nput
Output !L&D"
La( 4nverters !NOT Gate"
$
0
%
%
0
$
La( # Gate@
La( H I Na*e
4nput A
4nput
Output !L&D"
La( # !NAND Gate"
%
%
$
%
$
$
$
%
$
$
$
%
La( $% Gate@
La( H I Na*e
4nput A
4nput
Output !L&D"
La( $% !NOR Gate"
%
%
$
%
$
%
$
%
%
$
$
%
La( $$ Gate@
La( H I Na*e
4nput A
4nput
Output !L&D"
La( $$ !&'clusive OR Gate" !JOR"
%
%
%
%
$
$
$
%
$
$
$
%
'iscussion and (onclusion:
ased off the “truth ta(les” sho,n in the o(servations+ each truth ta(le sho,s ho, uni
