Lab Report 2 Digital Logic Gates
Austin Storm and Syed Athar EEE 221402, Spring 2016 Lawrence Technological University
February 08, 2016 1
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Introduction
Lab 2, Digital Logic Gates, investigates the behavior of six IC gates. It verifies the truth tables of each logic gate and observes their input/output waveforms on the oscilloscope. Digital circuitry is the key to makeup the cornerstone of modern computational hardware. By representing binary digits (i.e. {0,1}) with voltage levels, digital circuits are able to process binary numbers electronically. Logic gates have one or more inputs with one output. They respond to various input combinations. A truth table shows this relationship between circuit’s input combinations and its output.
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Methods
2.1 Materials
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Quad 2input NAND gate (74LS00) Quad 2input NOR gate (74LS02) Quad 2input AND gate (74LS08) Quad 2input POS OR gate (74LS32) Hex Inverter (74LS04) Quad 2input XOR gate (74LS86) Digital Electronics Trainer board Dual channel oscilloscope
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Green Diffused LED (LEDGDT13/4) Yellow Diffused LED (LEDYDT13/4)
2.2 Procedure The procedure in this lab was divided into four parts.
2.2.1 Part I In this section of the lab, each of the six logic gates truth tables were verified. First each of the logic gates were connected to the power and the ground one at a time. Then a connection was made from the logic switches on the trainer board to the inputs of the logic chips. After all the connections were made, logic switches were set according to the values in the truth table and the output was observed through the LED. Below are the truth tables obtained for each logic gate. LTU
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AND Gate A
B
Output
0
0
0
0
1
0
1
0
0
1
1
1
OR Gate
A
B
Output
0
0
0
0
1
1
1
0
1
1
1
1
NOR Gate A
B
Output
0
0
1
0
1
0
1
0
0
1
1
0
NAND Gate
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A
B
Output
0
0
1
0
1
1
1
0
1
1
1
0
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XOR Gate
A
B
Output
0
0
0
0
1
1
1
0
1
1
1
0
NOT Gate A
Output
0
1
1
0
2.2.2 Part II In this part, input/output waveform relationships were observed on an oscilloscope for each of the logic gates from the chips tested in part I. Instead of using the switches on the trainer board as the inputs, two outputs of the 7493 counter chip were used. Below are the timing diagrams of each of the logic chips. NOR Gate
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AND Gate
OR Gate
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Not Gate
XOR Gate
2.2.3 Part III Part IV was done to demonstrate how NAND gates can be used to represent any other logic gate. By using 2input NAND gates only, a 2input AND gate, 2input OR gate, 2input NOR gate, 2input XOR gate and an inverter circuit was created. The circuit diagrams are shown below:
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2.2.4 Part IV In this section, the propagation delay of an inverter IC was calculated. Six inverters were connected in a series. The clock source of the trainer board was connected to the pin of the first inverter. The oscilloscope was set to dual trace mode and the input clock signal was displayed on channel one. The output of the sixth inverter was displayed on channel two. The propagation delay due to six inverters can be seen in the picture below. Six Inverters in series:
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Results
In Part I, after the circuits were completed for each logic chip separately, truth tables were obtained by setting the switches on the trainer board as input and observing the LED for the output. The truth tables did infact matched the original truth tables. In Part II, the timing diagrams for each logic chip was obtained using the oscilloscope. The timing diagram of the output of each logic gate matches with the corresponding desired output. In Part III, it was found that by using 2input NAND gates only, any other logic gate can be constructed. A 2input AND gate, 2input OR gate, 2input NOR gate, 2input XOR gate and an inverter were created. It was found that each of the gates verifies the values of their truth table outputs. Part IV of the lab was performed to see the propagation delay diagram when six inverters are connected in a series. The oscilloscope was tuned to see the delay and it was infact visible. The measured delay was 25.0 nanoseconds.
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Discussion
In Part I, it was found that when the inputs were fed into the logic gates through switches the output that was observed through a LED came out to be exactly the same as the desired output and the truth tables were infact proven true. In Part II, by using the oscilloscope to display the output of each logic gate, it was proven that the timing diagram of each logic gate’s output matches the outputs that were obtained in part I. The inputs of were not probed by mistake as it is shown in the picture in part II. The NAND gate and the NOR gate are said to be universal gates because combinations of these gates can be used to accomplish any of the basic operations of other gates. The fact that NAND gates are universal is incredibly useful in electronics. Part III demonstrated how 2input NAND gates were manipulated in a certain way to perform the basic operations of other gates. Part IV demonstrated the propagation delay of six inverters connected in series. When the oscilloscope was tuned to right configurations the delay became quite visible and the delay was measured to be 25.0 nanoseconds. Since the inverters were connected in series, wiring was a lot simpler than the other parts of the lab. Further experimentation can be done to explore more principles such as finding boolean expression from a logic circuit and building a logic circuit from boolean expressions. LTU
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References
[1] Lawrence Technological University. EEE 2214 Lab Manual. [2] http://www.futurlec.com/74LS/74LS93.shtml [3] http://www.futurlec.com/74/IC7402.shtml [4] http://www.futurlec.com/74/IC7400.shtml [5] http://www.futurlec.com/74/IC7486.shtml [6] http://www.futurlec.com/74/IC7408.shtml [7] http://www.futurlec.com/74LS/74LS04.shtml
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Appendices
6.1 Collected Data No further data was collected aside from what was included within the results portion of the lab report. "I have neither given nor received unauthorized aid in completing this work, nor have I presented someone else's work as my own."
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