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Topt = arg min{ P (T ) log σ f (T ) + [1 − P (T )] log σ b (T ) − P (T ) log P(T ) − [1 − P(T )]log[1 − P(T )]
} where
σ f (T ) and σ b (T ) are foreground and background standard
deviations 2
3
EntropyKapur
EntropySahoo
Topt = arg
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H f (T ) = −
T
G p( g ) p( g ) p( g ) p( g ) and H b (T ) = − log log P(T ) P(T ) g =0 P (T ) g =T +1 P (T )
Topt = T[1] [ PT[1] + PT[ k ] =
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T (k )
k = 1,2,3,
p ( g ),
w = P[T(3) ] − P[T(1) ]
g −0
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4
5
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Cb (T ) = − log Topt = arg min
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2
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+
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σ 2 is the variance of the whole image
6 7
Cluster-Otsu Cluster-Yanni
Topt = arg max
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Topt = ( g max − g min )
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package general is constant YES :std_logic := constant NO :std_logic := constant HI :std_logic := constant LO :std_logic := constant ONE :std_logic := constant ZERO :std_logic := function boolean2stdlogic(b: function log2(v: in natural)
'1'; '0'; '1'; '0'; '1'; '0'; in boolean) return std_logic; return natural;
end package general; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
><
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package body general is function boolean2stdlogic(b: in boolean) return std_logic is variable s: std_logic; begin if b then s := '1'; else s := '0'; end if; return s; end function boolean2stdlogic; function log2(v: in natural) return natural is variable n: natural; variable logn: natural; begin n := 1; for i in 0 to 128 loop logn := i; exit when (n>=v); n := n * 2; end loop; return logn; end function log2; end package body general;
"/ library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use WORK.general.all; package memCnt is component memCnt generic( FREQ :natural:= 70_000; -- operating frequency in KHz DATA_WIDTH :natural:= 16; -- logic & MEM data width NROWS :natural:= 4096; -- number of rows in MEM array NCOLS :natural:= 256; -- number of columns in MEM array CL_ADDR_WIDTH :natural:= 22; -- logic-side address width MC_ADDR_WIDTH :natural:= 12; -- MEM-side address width MAX_NOP:natural:= 10000;-- number of NOPs before entering self-refresh IN_PHASE:boolean:= TRUE-- MEM and controller work on same or opposite clock edge ); port( -- logic side clk :in lock :in rst :in cl_rd :in cl_wr :in prog :out done :out rdDone :out cl_addr :in cl_Din :in cl_Dout :out -- MEM side mc_cke :out ce_n :out mc_ras :out mc_cas :out mc_we :out
std_logic; -- master clock std_logic; -- true if clock is stable std_logic; -- reset std_logic; -- initiate read operation std_logic; -- initiate write operation std_logic; -- read/write/self-refresh op has begun std_logic; -- read or write operation is done std_logic; -- read operation is done and data is available unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic to MEM unsigned(DATA_WIDTH-1 downto 0); -- data from logic to MEM unsigned(DATA_WIDTH-1 downto 0); -- data from MEM to logic std_logic; std_logic; std_logic; std_logic; std_logic;
------
>>
clock-enable to MEM chip-select to MEM MEM row address strobe MEM column address strobe MEM write enable
mc_ba :out unsigned(1 downto 0); -- MEM bank address mc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0); -- MEM row/column address sDIn :in unsigned(DATA_WIDTH-1 downto 0); -- data from MEM sDOut :out unsigned(DATA_WIDTH-1 downto 0); -- data to MEM sDOutEn:out std_logic; -- true if data is output to MEM on sDOut udqm :out std_logic; -- enable upper-byte of MEM databus if true ldqm :out std_logic -- enable lower-byte of MEM databus if true ); end component; end package memCnt; library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use WORK.general.all; entity memCnt is generic( FREQ :natural:= 70_000; -- operating frequency in KHz IN_PHASE: boolean:= TRUE; MAX_NOP: natural := 10000; DATA_WIDTH: natural := 16; -- logic & MEM data width NROWS: natural := 4096; -- number of rows in MEM array NCOLS: natural := 256; -- number of columns in MEM array CL_ADDR_WIDTH:natural := 22; -- logic-side address width MC_ADDR_WIDTH:natural := 12 -- MEM-side address width ); port( -- logic side clk :in std_logic; -- master clock lock :in std_logic; -- true if clock is stable rst :in std_logic; -- reset cl_rd :in std_logic; -- initiate read operation cl_wr :in std_logic; -- initiate write operation prog:out std_logic; -- read/write/self-refresh op has begun done :out std_logic; -- read or write operation is done rdDone :out std_logic; -- read operation is done and data is available cl_addr :in unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic to MEM cl_Din :in unsigned(DATA_WIDTH-1 downto 0); -- data from logic to MEM cl_Dout :out unsigned(DATA_WIDTH-1 downto 0); -- data from MEM to logic -- MEM side mc_cke :out std_logic; -- clock-enable to MEM ce_n :out std_logic; -- chip-select to MEM mc_ras :out std_logic; -- MEM row address strobe mc_cas :out std_logic; -- MEM column address strobe mc_we :out std_logic; -- MEM write enable mc_ba :out unsigned(1 downto 0); -- MEM bank address mc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0); -- MEM row/column address sDIn :in unsigned(DATA_WIDTH-1 downto 0); -- data from MEM sDOut :out unsigned(DATA_WIDTH-1 downto 0); -- data to MEM sDOutEn:out std_logic; -- true if data is output to MEM on sDOut udqm :out std_logic; -- enable upper-byte of MEM databus if true ldqm :out std_logic -- enable lower-byte of MEM databus if true ); end memCnt; architecture arch of memCnt is constant OUTPUT:std_logic constant INPUT :std_logic constant NOP :std_logic constant READ :std_logic constant WRITE :std_logic
:= := := := :=
'1'; '0'; '0'; '1'; '1';
-- direction of dataflow w.r.t. this controller -- no operation -- read operation -- write operation
-- MEM timing parameters constant Tinit :natural := 200; -- min initialization interval (us) constant Tref :natural := 64_000_000;-- maximum refresh interval (ns) constant Trfc :natural := 66; -- duration of refresh operation (ns) constant Trp :natural:= 20; -- min precharge command duration (ns) constant Twr :natural := 15; -- write recovery time (ns) constant Txsr :natural := 75; -- exit self-refresh time (ns) constant Tras :natural := 45;--min interval between active-precharge commands(ns)
>9
constant Trcd
:natural := 20;-- min interval between active and R/W commands (ns)
-- MEM timing parameters converted into clock cycles (based on FREQ) ----------------------------------------------------------------------constant NORM :natural := 1_000_000; -- normalize ns * KHz constant INIT_CYCLES_N :natural := 1+((Tinit*FREQ)/1000); -- MEM power-on initialization interval constant RAS_CYCLES_N: natural := 1+((Tras*FREQ)/NORM); -- active-to-precharge interval constant RCD_CYCLES_N: natural := 1+((Trcd*FREQ)/NORM); -- active-to-R/W interval constant REF_CYCLES_N: natural := 1+(((Tref/NROWS)*FREQ)/NORM); -- interval between row refreshes constant RFC_CYCLES_N: natural := 1+((Trfc*FREQ)/NORM); -- refresh operation interval constant RP_CYCLES_N: natural := 1+((Trp*FREQ)/NORM); -- precharge operation interval constant WR_CYCLES_N: natural := 1+((Twr*FREQ)/NORM); -- write recovery time constant XSR_CYCLES_N: natural := 1+((Txsr*FREQ)/NORM); -- exit self-refresh time constant MODE_CYCLES_N:natural := 2; -- mode register setup time constant CAS_CYCLES_N: natural := 3; -- CAS latency constant RFSH_OPS_N: natural := 8; -- number of refresh operations needed to init MEM -- timer registers that count down times for various MEM operations ----------------------------------------------------------------------signal timer_r, timer_x: unsigned(log2(INIT_CYCLES_N+1)-1 downto 0); -- current MEM op time signal rasTimer_r, rasTimer_x:unsigned(log2(RAS_CYCLES_N+1)-1 downto 0); -- active-to-precharge time signal wrTimer_r, wrTimer_x: unsigned(log2(WR_CYCLES_N+1)-1 downto 0); -- write-to-precharge time signal refTimer_r, refTimer_x:unsigned(log2(REF_CYCLES_N+1)-1 downto 0); -- time between row refreshes signal rfshCntr_r, rfshCntr_x:unsigned(log2(NROWS+1)-1 downto 0); -- counts refreshes that are neede signal nopCntr_r, nopCntr_x: unsigned(log2(MAX_NOP+1)-1 downto 0); -- counts consecutive NOP operations signal doSelfRfsh: std_logic; -- active when the NOP counter hits zero and self-refresh can start -- MEM timing parameters converted into unsigned clock cycles for clarity ---------------------------------------------------------------------------constant INIT_CYCLES :unsigned := TO_UNSIGNED(INIT_CYCLES_N, timer_r'length); constant RAS_CYCLES :unsigned := TO_UNSIGNED(RAS_CYCLES_N, rasTimer_r'length); constant RCD_CYCLES :unsigned := TO_UNSIGNED(RCD_CYCLES_N, timer_r'length); constant REF_CYCLES :unsigned := TO_UNSIGNED(REF_CYCLES_N, refTimer_r'length); constant RFC_CYCLES :unsigned := TO_UNSIGNED(RFC_CYCLES_N, timer_r'length); constant RP_CYCLES :unsigned := TO_UNSIGNED(RP_CYCLES_N, timer_r'length); constant WR_CYCLES :unsigned := TO_UNSIGNED(WR_CYCLES_N, wrTimer_r'length); constant XSR_CYCLES :unsigned := TO_UNSIGNED(XSR_CYCLES_N, timer_r'length); constant MODE_CYCLES :unsigned := TO_UNSIGNED(MODE_CYCLES_N, timer_r'length); constant CAS_CYCLES :unsigned := TO_UNSIGNED(CAS_CYCLES_N, timer_r'length); constant RFSH_OPS :unsigned := TO_UNSIGNED(RFSH_OPS_N, rfshCntr_r'length); constant MAX_NOP_CNT :unsigned := TO_UNSIGNED(MAX_NOP, nopCntr_r'length); -- states of the MEM controller state machine -----------------------------------------------type cntlState is ( INITWAIT, -- initialization INITPCHG, -- initialization - initial precharge of MEM banks INITSETMODE, -- initialization - set MEM mode INITRFSH, -- initialization - do initial refreshes RW -- read/write/refresh the MEM ACTIVATE, -- open a row of the MEM for reading/writing REFRESHROW, -- refresh a row of the MEM
>=
SELFREFRESH
-- keep MEM in self-refresh mode with CKE low
); signal state_r, state_x: cntlState;
-- state register and next state
-- commands that are sent to the MEM to make it perform certain operations -- commands use these MEM input pins (ce_n,mc_ras,mc_cas,mc_we,udqm,ldqm) ----------------------------------------------------------------------------subtype sdramCmd is unsigned(5 downto 0); constant NOP_CMD :sdramCmd := "011100"; constant ACTIVE_CMD :sdramCmd := "001100"; constant READ_CMD :sdramCmd := "010100"; constant WRITE_CMD :sdramCmd := "010000"; constant PCHG_CMD :sdramCmd := "001011"; constant MODE_CMD :sdramCmd := "000011"; constant RFSH_CMD :sdramCmd := "000111"; -- MEM mode register subtype sdramMode is unsigned(11 downto 0); constant MODE: sdramMode := "00" & "0" & "00" & "011" & "0" & "000"; -- the logic address is decomposed into these sets of MEM address components constant ROW_LEN :natural := log2(NROWS);-- number of row address bits constant COL_LEN :natural := log2(NCOLS);-- number of column address bits signal bank signal row signal col
:unsigned(mc_ba'range); :unsigned(ROW_LEN - 1 downto 0); :unsigned(mc_addr'range);
-- bank address bits -- row address within bank -- column address within row
-- registers that store the currently active bank and row of the MEM signal activeBank_r, activeBank_x :unsigned(bank'range); signal activeRow_r, activeRow_x :unsigned(row'range); signal activeFlag_r, activeFlag_x:std_logic;-- indicates that some row is active signal doActivate:std_logic;-- indicates when a new row needs to be activated -- there constant constant constant constant constant
is a command bit embedded within the MEM column address CMDBIT_POS :natural := 10; -- position of command bit AUTO_PCHG_ON:std_logic := '1';-- CMDBIT value to auto-precharge the bank AUTO_PCHG_OFF :std_logic := '0';-- CMDBIT value to disable auto-precharge ALL_BANKS :std_logic := '1';-- CMDBIT value to select all banks ACTIVE_BANK:std_logic := '0';-- CMDBIT value to select only active bank
-- status signals that indicate when signal wrInProgress :std_logic; signal rdInProgress :std_logic; signal activateInProgress:std_logic;
certain operations are in progress -- write operation in progress -- read operation in progress -- row activation is in progress
-- these registers track the progress of read and write operations -- registered outputs to logic signal prog_r,prog_x :std_logic; -- true when MEM read or write operation is started signal cl_Dout_r,cl_Dout_x:unsigned(cl_Dout'range); -- holds data read from MEM and sent to the logic signal cl_DoutOppPhase_r, cl_DoutOppPhase_x :unsigned(cl_Dout'range); -- holds data read from MEM on opposite clock edge -- registered outputs to MEM signal mc_cke_r,mc_cke_x:std_logic; -- clock enable signal cmd_r,cmd_x :sdramCmd; -- MEM command bits signal mc_ba_r,mc_ba_x :unsigned(mc_ba'range); -- MEM bank address bits signal mc_addr_r,mc_addr_x:unsigned(mc_addr'range); -- MEM row/column address signal mc_data_r,mc_data_x:unsigned(sDOut'range); -- MEM out databus signal mc_dataDir_r,mc_dataDir_x:std_logic;-- MEM databus direction control bit begin ------------------------------------------------------------ attach some internal signals to the I/O ports ------------------------------------------------------------ attach registered MEM control signals to MEM input pins (ce_n,mc_ras,mc_cas,mc_we,udqm,ldqm) <= cmd_r;-- MEM operation control bits
9
mc_cke <= mc_cke_r; -- MEM clock enable mc_ba <= mc_ba_r; -- MEM bank address mc_addr <= mc_addr_r; -- MEM address sDOut <= mc_data_r; -- MEM output data bus sDOutEn<= YES when mc_dataDir_r=OUTPUT else NO;-- output databus enable -- attach some port signals cl_Dout <= cl_Dout_r; prog <= prog_r;
-- data back to logic -- true if requested operation has begun
------------------------------------------------------------ compute the next state and outputs ----------------------------------------------------------combinatorial: process(cl_rd, cl_wr, cl_addr, cl_Din, cl_Dout_r, sDIn, state_r, prog_x, activeFlag_r, activeBank_r, activeRow_r, cl_DoutOppPhase_r, nopCntr_r,lock, rfshCntr_r, timer_r, rasTimer_r, wrTimer_r, refTimer_r, cmd_r,mc_cke_r) begin ------------------------------------------------------------ setup default values for signals ----------------------------------------------------------prog_x <= NO; -- no operations have begun mc_cke_x <= YES; -- enable MEM clock cmd_x <= NOP_CMD; -- set MEM command to no-operation mc_dataDir_x <= INPUT; -- accept data from the MEM mc_data_x <= cl_Din(mc_data_x'range);-- output data from logic to MEM -- reload these registers and flags with their existing values state_x <= state_r; activeFlag_x <= activeFlag_r activeBank_x <= activeBank_r; activeRow_x <= activeRow_r; rfshCntr_x <= rfshCntr_r; ------------------------------------------------------------ setup default value for the MEM address ------------------------------------------------------------ extract bank field from logic address bank <= cl_addr(bank'length+ROW_LEN+COL_LEN-1 downto ROW_LEN +COL_LEN); mc_ba_x <= bank; -- set MEM bank address bits -- extract row, column fields from logic address row <= cl_addr(ROW_LEN + COL_LEN - 1 downto COL_LEN); -- extend column until it is as large as the(MEM address bus - 1) col <= (others=>'0'); -- set it to all zeroes col(COL_LEN-1 downto 0) <= cl_addr(COL_LEN-1 downto 0); -- by default, set MEM address to the column address with interspersed -- command bit set to disable auto-precharge mc_addr_x <= col(col'high-1 downto CMDBIT_POS) & AUTO_PCHG_OFF & col(CMDBIT_POS-1 downto 0); ------------------------------------------------------------ manage row activation ------------------------------------------------------------ request a row activation operation if the row and bank of the current -- address do not match the currently active row and bank, or if no row -- andbank is currently active if (row /= activeRow_r)or(bank /= activeBank_r)or(activeFlag_r = NO) then doActivate <= YES; else doActivate <= NO; end if; ------------------------------------------------------------ manage self-refresh ------------------------------------------------------------ enter self-refresh if neither a read or write is requested for --MAX_NOP_CNT consecutive cycles. if (cl_rd = YES) or (cl_wr = YES) then
97
-- any read or write resets NOP counter and exits self-refresh state nopCntr_x <= (others=>'0'); doSelfRfsh <= NO; elsif nopCntr_r /= MAX_NOP_CNT then -- increment NOP counter whenever there is no read or write operation nopCntr_x <= nopCntr_r + 1; doSelfRfsh <= NO; else -- start self-refresh when counter hits maximum NOP count --and leave counter unchanged nopCntr_x <= nopCntr_r; doSelfRfsh <= YES; end if; ------------------------------------------------------------ update the timers ------------------------------------------------------------ row activation timer if rasTimer_r /= 0 then -- decrement a non-zero timer and set the flag -- to indicate the row activation is still inprogress rasTimer_x <= rasTimer_r - 1; activateInProgress <= YES; else -- on timeout, keep the timer at zero and reset the flag -- to indicate the row activation operation is done rasTimer_x <= rasTimer_r; activateInProgress <= NO; end if; -- write operation timer if wrTimer_r /= 0 then -- decrement a non-zero timer and set the flag -- to indicate the write operation is still inprogress wrTimer_x <= wrTimer_r - 1; wrInPRogress <= YES; else -- on timeout, keep the timer at zero and reset the flag that -- indicates a write operation is in progress wrTimer_x <= wrTimer_r; wrInPRogress <= NO; end if; -- refresh timer if refTimer_r /= 0 then refTimer_x <= refTimer_r - 1; else -- on timeout, reload the timer with the interval between row refreshes -- and increment the counter for the no. of row refreshes that are needed refTimer_x <= REF_CYCLES; rfshCntr_x <= rfshCntr_r + 1; end if; -- main timer for sequencing MEM operations if timer_r /= 0 then -- decrement the timer and do nothing else since the previous operation --has not completed yet. timer_x <= timer_r - 1; else -- the previous operation has completed once the timer hits zero timer_x <= timer_r; -- by default, leave the timer at zero ------------------------------------------------------------ compute the next state and outputs ----------------------------------------------------------case state_r is ------------------------------------------------------------ let clock stabilize and then wait for the MEM to initialize -----------------------------------------------------------
9
when INITWAIT => if lock = YES then timer_x <= INIT_CYCLES; state_x <= INITPCHG; else mc_cke_x <= NO; end if; ------------------------------------------------------------ precharge all MEM banks after power-on initialization ----------------------------------------------------------when INITPCHG => cmd_x <= PCHG_CMD; mc_addr_x(CMDBIT_POS) <= ALL_BANKS; timer_x <= RP_CYCLES; rfshCntr_x <= RFSH_OPS - 1; state_x <= INITRFSH; ------------------------------------------------------------ refresh the MEM a number of times after initial precharge ----------------------------------------------------------when INITRFSH => cmd_x <= RFSH_CMD; timer_x <= RFC_CYCLES; rfshCntr_x <= rfshCntr_r - 1; if rfshCntr_r = 0 then state_x <= INITSETMODE; end if; ------------------------------------------------------------ set the mode register of the MEM ----------------------------------------------------------when INITSETMODE => cmd_x <= MODE_CMD; mc_addr_x <= MODE; timer_x <= MODE_CYCLES; state_x <= RW; -------------------------------------------------------------------- process read/write/refresh ops after initialization is done ------------------------------------------------------------------when RW => ---------------------------------------------------------- highest priority operation: row refresh -- do a refresh op if the refresh counter is non-zero --------------------------------------------------------if rfshCntr_r /= 0 then if (activateInProgress=NO) and (wrInProgress=NO) and (rdInProgress=NO) then cmd_x <= PCHG_CMD; mc_addr_x(CMDBIT_POS)<= ALL_BANKS; timer_x <= RP_CYCLES; activeFlag_x<= NO; state_x <= REFRESHROW; end if; elsif cl_rd = YES then if doActivate = YES then if (activateInProgress=NO) and (wrInProgress=NO) and (rdInProgress=NO) then cmd_x <= PCHG_CMD; Addr_x(CMDBIT_POS) <= ALL_BANKS; timer_x <= RP_CYCLES; activeFlag_x <= NO; state_x <= ACTIVATE; end if; elsif (rdInProgress=NO) then cmd_x <= READ_CMD; prog_x <= YES; end if; ---------------------------------------------------------- do a logic-initiated write operation
98
--------------------------------------------------------elsif cl_wr = YES then if doActivate = YES then if (activateInProgress=NO) and wrInProgress=NO)and (rdInProgress=NO) then cmd_x <= PCHG_CMD; timer_x <= RP_CYCLES; activeFlag_x<= NO; state_x <= ACTIVATE; mc_addr_x(CMDBIT_POS) <= ALL_BANKS; end if; elsif rdInProgress = NO then cmd_x <= WRITE_CMD; mc_dataDir_x <= OUTPUT; wrTimer_x <= WR_CYCLES; prog_x <= YES; end if; ---------------------------------------------------------- do a logic-initiated self-refresh operation --------------------------------------------------------elsif doSelfRfsh = YES then if (activateInProgress=NO) and (wrInProgress=NO) and (rdInProgress=NO) then cmd_x <= PCHG_CMD; timer_x <= RP_CYCLES; activeFlag_x <= NO; state_x <= SELFREFRESH; mc_addr_x(CMDBIT_POS) <= ALL_BANKS; end if; --------------------------------------------------------- no operation ------------------------------------------------------else state_x <= RW; end if; ------------------------------------------------------------ activate a row of the MEM ----------------------------------------------------------when ACTIVATE => cmd_x <= ACTIVE_CMD; mc_addr_x <= (others=>'0'); mc_addr_x(row'range) <= row; activeBank_x <= bank; activeRow_x <= row; activeFlag_x <= YES; rasTimer_x <= RAS_CYCLES; timer_x <= RCD_CYCLES; state_x <= RW; ------------------------------------------------------------ refresh a row of the MEM ----------------------------------------------------------when REFRESHROW => cmd_x <= RFSH_CMD; timer_x <= RFC_CYCLES; rfshCntr_x <= rfshCntr_r - 1; state_x <= RW; ------------------------------------------------------------ place the MEM into self-refresh and keep it there until --further notice ----------------------------------------------------------when SELFREFRESH => if (doSelfRfsh = YES) or (lock = NO) then cmd_x <= RFSH_CMD; mc_cke_x<= NO; else mc_cke_x <= YES; rfshCntr_x <= (others=>'0'); activeFlag_x<= NO;
9!
timer_x state_x
<= XSR_CYCLES; <= RW;
end if; ------------------------------------------------------------ unknown state ----------------------------------------------------------when others => state_x <= INITWAIT; end case; end if; end process combinatorial; ------------------------------------------------------------ update registers on the appropriate clock edge ----------------------------------------------------------update: process(rst,clk) begin if rst = YES then state_r <= INITWAIT; activeBank_r <= (others=>'0'); activeRow_r <= (others=>'0'); activeFlag_r <= NO; rfshCntr_r <= (others=>'0'); timer_r <= (others=>'0'); refTimer_r <= REF_CYCLES; rasTimer_r <= (others=>'0'); wrTimer_r <= (others=>'0'); nopCntr_r <= (others=>'0'); prog_r <= NO; mc_cke_r <= NO; cmd_r <= NOP_CMD; mc_ba_r <= (others=>'0'); mc_addr_r <= (others=>'0'); mc_data_r <= (others=>'0'); mc_dataDir_r <= INPUT; cl_Dout_r <= (others=>'0'); elsif clk'event and clk='1' then state_r <= state_x; activeBank_r <= activeBank_x; activeRow_r <= activeRow_x; activeFlag_r <= activeFlag_x; rfshCntr_r <= rfshCntr_x; timer_r <= timer_x; refTimer_r <= refTimer_x; rasTimer_r <= rasTimer_x; wrTimer_r <= wrTimer_x; nopCntr_r <= nopCntr_x; prog_r <= prog_x; mc_cke_r <= mc_cke_x; cmd_r <= cmd_x; mc_ba_r <= mc_ba_x; mc_addr_r <= mc_addr_x; mc_data_r <= mc_data_x; mc_dataDir_r <= mc_dataDir_x; cl_Dout_r <= cl_Dout_x; end if; if rst = YES then cl_DoutOppPhase_r<= (others=>'0'); elsif clk'event and clk='0' then cl_DoutOppPhase_r<= cl_DoutOppPhase_x; end if; end process update; end arch;
93
"/$
/
library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.general.all; use WORK.memCnt.all; package memCnt is component memCntMod generic( FREQ :natural:= 70_000; -- operating frequency in KHz DATA_WIDTH :natural:= 16; -- logic & MEM data width NROWS :natural:= 4096; -- number of rows in MEM array NCOLS :natural:= 256; -- number of columns in MEM array CL_ADDR_WIDTH :natural:= 22; -- logic-side address width MC_ADDR_WIDTH :natural:= 12; -- MEM-side address width MAX_NOP: natural:= 10000 -- number of NOPs before entering self-refresh ); port( -- logic side clk :in std_logic; -- master clock bufclk :out std_logic; -- buffered master clock clk1x :out std_logic; -- logic clock sync'ed to master clock clk2x :out std_logic; -- double-speed logic clock lock :out std_logic; -- logic clock is locked to master clock=1 rst :in std_logic; -- reset cl_rd :in std_logic; -- initiate read operation cl_wr :in std_logic; -- initiate write operation prog:out std_logic; -- read/write/self-refresh op begun done :out std_logic; -- read or write operation is done rdDone :out std_logic; -- read done and data is available cl_addr :in unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic cl_Din :in unsigned(DATA_WIDTH-1 downto 0); -- data from logic cl_Dout :out unsigned(DATA_WIDTH-1 downto 0); -- data to logic -- MEM side sclkfb :in std_logic; -- clock from MEM after PCB delays sclk :out std_logic; -- MEM clock sync'ed to master clock cke :out std_logic; -- clock-enable to MEM mc_cs :out std_logic; -- chip-select to MEM mc_ras :out std_logic; -- MEM row address strobe mc_cas :out std_logic; -- MEM column address strobe mc_we :out std_logic; -- MEM write enable mc_ba :out unsigned(1 downto 0); -- MEM bank address bits mc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0);-- MEM row/column address mc_data :inout unsigned(DATA_WIDTH-1 downto 0); -- MEM in/out databus udqm :out std_logic; -- high databits I/O mask ldqm :out std_logic -- low databits I/O mask ); end component; end package memCnt; library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.general.all; use WORK.memCnt.all; entity memCntMod is generic( FREQ DATA_WIDTH NROWS NCOLS CL_ADDR_WIDTH MC_ADDR_WIDTH
:natural:= :natural:= :natural:= :natural:= :natural:= :natural:=
70_000; 16; 4096; 256; 22; 12;
9<
-------
operating frequency in KHz logic & MEM data width number of rows in MEM array number of columns in MEM array logic-side address width MEM-side address width
MAX_NOP: natural:= 10000 -- number of NOPs before entering self-refresh ); port( -- logic side clk :in std_logic; -- master clock bufclk :out std_logic; -- buffered master clock clk1x :out std_logic; -- logic clock sync'ed to master clock clk2x :out std_logic; -- double-speed logic clock lock :out std_logic; -- logic clock is locked to master clock=1 rst :in std_logic; -- reset cl_rd :in std_logic; -- initiate read operation cl_wr :in std_logic; -- initiate write operation prog:out std_logic; -- read/write/self-refresh op begun done :out std_logic; -- read or write operation is done rdDone :out std_logic; -- read done and data is available cl_addr :in unsigned(CL_ADDR_WIDTH-1 downto 0); -- address from logic cl_Din :in unsigned(DATA_WIDTH-1 downto 0); -- data from logic cl_Dout :out unsigned(DATA_WIDTH-1 downto 0); -- data to logic -- MEM side sclkfb :in std_logic; -- clock from MEM after PCB delays sclk :out std_logic; -- MEM clock sync'ed to master clock cke :out std_logic; -- clock-enable to MEM mc_cs :out std_logic; -- chip-select to MEM mc_ras :out std_logic; -- MEM row address strobe mc_cas :out std_logic; -- MEM column address strobe mc_we :out std_logic; -- MEM write enable mc_ba :out unsigned(1 downto 0); -- MEM bank address bits mc_addr :out unsigned(MC_ADDR_WIDTH-1 downto 0);-- MEM row/column address mc_data :inout unsigned(DATA_WIDTH-1 downto 0); -- MEM in/out databus udqm :out std_logic; -- high databits I/O mask ldqm :out std_logic -- low databits I/O mask ); end memCntMod; architecture arch of memCntMod is -- the MEM controller and external MEM chip will clock on the same edge -- if the frequency is greater than the minimum DLL lock frequency constant MIN_LOCK_FREQ: natural := 25_000; constant IN_PHASE: boolean := (FREQ >= MIN_LOCK_FREQ); -- signals for internal logic clock DLL signal int_clkin, int_clk1x, int_clk1x_b, int_clk2x, int_clk2x_b, int_lock: std_logic; -- signals for external logic clock DLL signal ext_clkin, sclkfb_b, ext_clk1x, ext_lock: std_logic; signal clk_i : std_logic; -- clock for MEM controller logic signal lock_i: std_logic; -- bus for holding output data from MEM signal sDOut: unsigned(mc_data'range); signal sDOutEn: std_logic; begin ------------------------------------------------------------ setup the DLLs for clock generation ----------------------------------------------------------clkin: IBUFG port map (I=>clk, O=>int_clkin); ext_clkin <= int_clkin when IN_PHASE else not int_clkin; gen_dlls: if IN_PHASE generate -- generate an internal clock sync'ed to the master clock dllint: CLKDLL port map( CLKIN=>int_clkin, CLKFB=>int_clk1x_b, CLK0=>int_clk1x, RST=>ZERO, CLK90=>open, CLK180=>open, CLK270=>open,
9>
int_clk1x_buf int_clk2x_buf sclkfb_buf dllext
: : : :
CLK2X=>int_clk2x, CLKDV=>open, LOCKED=>int_lock ); BUFG port map(I=>int_clk1x, O=>int_clk1x_b); BUFG port map(I=>int_clk2x, O=>int_clk2x_b); IBUFG port map(I=>sclkfb, O=>sclkfb_b); CLKDLL port map( CLKIN=>ext_clkin, CLKFB=>sclkfb_b, CLK0 =>ext_clk1x, RST =>ZERO, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open, CLKDV=>open, LOCKED=>ext_lock);
end generate; bufclk clk_i clk1x clk2x sclk
<= <= <= <= <=
int_clkin; int_clk1x_b int_clk1x_b int_clk2x_b ext_clk1x
when when when when
IN_PHASE IN_PHASE IN_PHASE IN_PHASE
else else else else
int_clkin; int_clkin; int_clkin; ext_clkin;
-- indicate the lock status of the internal and external DLL lock_i <= int_lock and ext_lock when IN_PHASE else YES; lock <= lock_i; -- lock signal for the logic logic -- MEM memory controller module u1: memCnt generic map( FREQ => FREQ, IN_PHASE => IN_PHASE, PIPE_EN => PIPE_EN, MAX_NOP => MAX_NOP, NROWS => NROWS, NCOLS => NCOLS, DATA_WIDTH=> DATA_WIDTH, CL_ADDR_WIDTH => CL_ADDR_WIDTH, MC_ADDR_WIDTH => MC_ADDR_WIDTH ) port map( clk => clk_i, -- master clock from external clock source lock => lock_i, -- valid synchronized clocks indicator rst => rst, -- reset cl_rd => cl_rd, -- logic-side MEM read control from memory tester cl_wr => cl_wr, -- logic-side MEM write control from memory tester prog => prog, -- MEM memory read/write done indicator rdDone => rdDone, -- MEM memory read/write done indicator done => done, cl_addr => cl_addr, -- logic-side address from memory tester cl_Din => cl_Din, -- test data pattern from memory tester cl_Dout => cl_Dout, -- MEM data output to memory tester status => status, -- MEM controller state (for diagnostics) mc_cke => mc_cke -- MEM clock enable ce_n => mc_cs, -- MEM chip-select mc_ras => mc_ras, -- MEM RAS mc_cas => mc_cas, -- MEM CAS mc_we => mc_we, -- MEM write-enable mc_ba => mc_ba, -- MEM bank address mc_addr => mc_addr, -- MEM address sDIn => mc_data, -- input data from MEM sDOut => sDOut, -- output data to MEM sDOutEn => sDOutEn, -- enable drivers to send data to MEM udqm => udqm -- MEM UDQM ldqm => ldqm -- MEM LDQM ); mc_data <= sDOut when sDOutEn=YES else (others=>'Z'); end arch;
99
"/&
"
/
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use WORK.general.all; package mem is component ImBinar generic( DATA_WIDTH ADDR_WIDTH BEG_TEST END_TEST
:natural :natural :natural :natural
:= := := :=
16; 22; 16#00_0000#; 16#00_000F#
-----
memory data width memory address width beginning test range address ending test range address
); port( clk :in rst :in done :in cl_rd :out cl_wr :out addr :out dIn :in dOut :out doAgain:in progress:out
std_logic; -- master clock input std_logic; -- reset or pushbotton on the board std_logic; -- memory operation done indicator std_logic; -- memory read control signal std_logic; -- memory write control signal unsigned(ADDR_WIDTH-1 downto 0);-- address to memory unsigned(DATA_WIDTH-1 downto 0);-- data from memory unsigned(DATA_WIDTH-1 downto 0);-- data to memory std_logic; -- re-do memory test std_logic_vector(2 downto 0) -- memory test progress indicator
); end component; end package mem; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use WORK.general.all; entity ImBinar is generic( DATA_WIDTH :natural := 16; -- memory data width ADDR_WIDTH :natural := 22; -- memory address width BEG_TEST :natural := 16#00_0001#;-- beginning test range address END_TEST :natural := 16#00_0010#-- ending test range address ); port( clk :in std_logic; -- master clock input rst :in std_logic; -- reset or pushbotton on the board done :in std_logic; -- memory operation done indicator cl_rd :out std_logic; -- memory read control signal cl_wr :out std_logic; -- memory write control signal addr :out unsigned(ADDR_WIDTH-1 downto 0);-- address to memory dIn :in unsigned(DATA_WIDTH-1 downto 0);-- data from memory dOut :out unsigned(DATA_WIDTH-1 downto 0);-- data to memory doAgain:in std_logic; -- re-do memory test progress:out std_logic_vector(2 downto 0)-- memory test progress indicator ); end ImBinar; architecture Behavioral of ImBinar is type testState is ( INIT, -- initialization MEM_RD_1, -- Read data from mem TRESH_CAL, -- calculate the threshold MEM_RD_2, -- Read data from mem and compare MEM_WR, -- Write the binarized image in mem STOP ); signal state_r,state_x :testState;
-- state register and next state
9=
signal signal signal signal signal signal
addr_r,addr_x :unsigned(addr'range); -- address register data_x :unsigned(dOut'range);-- data register w1_r, w2_r :signed(8 downto 0); -- current weights registers w1_x,w2_x :signed(8 downto 0); -- next weights registers alpha_r,alpha_x :signed(8 downto 0) -- alpha register thresh :unsigned(8 downto 0);--threshold register
constant w1_init constant w2_init Constant alpha_init
:signed(8 downto 0):= "010000000"; -- weight1 Initial value :signed(8 downto 0):= "010000000"; -- weight2 Initial value :signed(8 downto 0):= "010000000"; -- alpha initial value
begin -- states of the state machine combinatorial: process(state_r,addr_r,dIn,done,doAgain,w1_r,w2_r, alpha_r) --Internal Variables variable d1,d2,ad1,ad2 :signed(8 downto 0); variable prod1, prod2 :signed (17 downto 0); variable prodt1, prodt2:signed(8 downto 0); variable s_dIn :signed(8 downto 0); variable dIn_8 :unsigned(7 downto 0); begin -- default operations (do nothing unless explicitly stated in -- the following case statement) cl_rd <= NO; -- no memory write cl_wr <= NO; -- no memory read addr_x <= addr_r; -- next address is the same as current address state_x<= state_r; -- no change in states -- compute the next state and operations case state_r is ------------------------------------------------------- initialize the registers -----------------------------------------------------when INIT => progress<= "000";-- indicate the current controller state addr_x <= TO_UNSIGNED(BEG_TEST,addr_x'length); -- load starting mem address state_x <= MEM_RD_1; -- next go to memory read state w1_x <= w1_init; --initialize w1 w2_x <= w2_init; --initialize w2 alpha_x <= alpha_init;-- initialize alpha thresh <= (others=>'0');-- reset threshold register ------------------------------------------------------- Read data from mem -----------------------------------------------------when MEM_RD_1 => progress<= "001"; -- indicate the current controller state if done = NO then cl_rd <= YES; else cl_rd <= NO; prod_alpha := alpha_r* "011111101"; alphat:= prod_alpha(16 downto 8); alpha_x<=alphat; dIn_8:=dIn(7 downto 0); s_dIn:= signed('0'& dIn_8); d1 := s_dIn - w1_r; d2 := s_dIn - w2_r; ad1 := abs(d1); ad2 := abs(d2); prod1 := alpha * d1; prod2 := alpha * d2; prodt1:= prod1 (16 downto 8); prodt2:= prod2 (16 downto 8); -- Comapare weights and update if ad1 <= ad2 then
=
w1_x <= w1_r+ prodt1; w2_x<= w2_r; -- Check if the weight value is -- between 0 and 255 if w1_x<0 then w1_x <="000000000"; elsif w1_x>255 then w1_x <="011111111"; end if; else w2_x <= w2_r+ prodt2; w1_x<= w1_r; -- Check if the weight value is -- between 0 and 255 if w2_x<0 then w2_x <="000000000"; elsif w2_x>255 then w2_x <="011111111"; end if; end if; if addr_r = TO_UNSIGNED(END_TEST,addr_r'length) then state_x <= TRESH_CAL; --go to the next state else addr_x <= addr_r + 1; -- increment address to check next -- memory location end if; end if; ------------------------------------------------------- calulate the threshold -----------------------------------------------------when TRESH_CAL => progress<= "010"; -- indicate the current controller state thresh<= (unsigned(w1_x+w2_x))/2;--calculate threshold state_x<= MEM_RD_2; addr_x <= TO_UNSIGNED(BEG_TEST,addr_x'length); -- load starting mem address ------------------------------------------------------- Read data from mem and compare -----------------------------------------------------when MEM_RD_2=> progress <= "011"; if done = NO then cl_rd <= YES; else cl_rd <= NO; -- Appling threshold value if dIn <= ("0000000"&thresh) then data_x <= X"0000"; else data_x <= X"00FF"; end if; state_x <= MEM_WR; end if; ------------------------------------------------------- Write the binarized image in mem -----------------------------------------------------when MEM_WR => progress<= "100"; -- indicate the current controller state if done = NO then cl_wr <= YES; else cl_wr<= NO; if addr_r/= TO_UNSIGNED(END_TEST,addr_r'length) then addr_x <= addr_r + 1; -- increment address to check next -- memory location state_x <= MEM_RD_2; -- go to the next state
=7
else state_x <= STOP; end if; end if; ------------------------------------------------------- STOP -----------------------------------------------------when others=> progress <= "101"; -- indicate the current controller state if (doAgain = YES) then addr_x <= TO_UNSIGNED(BEG_TEST,addr_x'length); -- load starting mem address state_x<= INIT; -- go to the INIT state and and re-do memory test end if; end case; end process; -- update the registers update: process(clk) begin if clk'event and clk = '1' then if rst = YES then -- go to starting state state_r <= INIT; else -- update address register, and state state_r <= state_x; addr_r <= addr_x; w1_r<=w1_x; w2_r<=w2_x; alpha_r<=alpha_x end if; end if; end process; -- connect internal registers to external busses(outputs) addr <= addr_r; dOut <= data_x; end Behavioral;
"/(
"
/
library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.general.all; use WORK.mem.all; use WORK.memCnt.all; entity ImBinarMod is generic( FREQ DATA_WIDTH BEG_ADDR END_ADDR BEG_TEST END_TEST ); port( pushb_n:in clk :in sclkfb :in mc_data :inout
:natural:= :natural:= :natural:= :natural:= :natural:= :natural:=
70_000; -- frequency of operation in KHz 16; -- MEM data width 16#00_0000#;-- beginning MEM address 16#3f_FFFF#;-- ending MEM address 16#00_0000#;-- beginning test range address 16#00_000F# -- ending test range address
std_logic; -- pushbutton input std_logic; -- main clock input from external clock source std_logic; -- feedback MEM clock with PCB delays unsigned(DATA_WIDTH-1 downto 0);-- data bus to/from MEM
=
ce_n :out std_logic; sclk :out std_logic; mc_cke :out std_logic; mc_cs :out std_logic; mc_ras :out std_logic; mc_cas :out std_logic; mc_we :out std_logic; mc_ba :out unsigned( 1 downto 0); mc_addr :out unsigned(11 downto 0); udqm :out std_logic; qml :out std_logic; seven_seg:out unsigned(6 downto 0); ); end ImBinarMod;
-------------
Flash RAM chip-enable clock to MEM MEM clock-enable MEM chip-select MEM RAS MEM CAS MEM write-enable MEM bank-address MEM address bus MEM UDQM MEM LDQM seven segment LED
architecture arch of ImBinarMod is constant ADDR_WIDTH: natural := log2(END_ADDR-BEG_ADDR+1); signal rst_i :std_logic; -- internal reset signal signal clk_i :std_logic; -- internal master clock signal signal clk_b :std_logic; -- buffered input (non-DLL) clock signal lock :std_logic; -- MEM clock DLL lock indicator signal begun :std_logic; -- MEM operation started indicator signal done :std_logic; -- MEM operation complete indicator signal rdDone :std_logic; -- MEM operation complete indicator signal cl_addr :unsigned(ADDR_WIDTH-1 downto 0); -- logic address bus signal cl_Din :unsigned(DATA_WIDTH-1 downto 0); -- logic-side data to MEM signal cl_Dout :unsigned(DATA_WIDTH-1 downto 0); -- logic-side data from MEM signal cl_rd :std_logic; -- logic-side read control signal signal cl_wr :std_logic; -- logic-side write control signal signal dataIn :unsigned(DATA_WIDTH-1 downto 0); -- input databus from MEM signal dataOut :unsigned(DATA_WIDTH-1 downto 0); -- output databus to MEM signal progress:std_logic_vector(2 downto 0); -- test progress indicator signal syncPushb: std_logic_vector(1 downto 0); attribute INIT: string; attribute INIT of rst_i: signal is "1"; begin ce_n <= '1';
-- disable Flash RAM
-- internal reset flag is set active by config. bitstream -- and then gets reset after clocks start. process(clk_b) begin if(clk_b'event and clk_b='1') then if lock = NO then rst_i <= YES; -- stay in reset until DLLs start up and lock else rst_i <= NO; -- release reset once DLLs lock end if; end if; end process; -- synchronize the pushbutton to the main clock process(clk_b) begin if(clk_b'event and clk_b='1') then syncPushb <= syncPushb(syncPushb'high-1 downto 0) & not pushb_n; end if; end process; -- generic ImBinar module slow_u0: ImBinar generic map( DATA_WIDTH => cl_Din'length, ADDR_WIDTH => cl_addr'length, BEG_TEST => BEG_TEST, END_TEST => END_TEST ) port map( clk => clk_i, rst => rst_i,
=8
-- master internal clock -- reset
doAgain => syncPushb(syncPushb'high), -- re-do the memory test done => done -- MEM controller operation complete dIn => cl_Dout, -- logic-side data from MEM goes to memory tester cl_rd => cl_rd, -- logic-side MEM read control from memory tester cl_wr => cl_wr, -- logic-side MEM write control from memory tester addr => cl_addr, -- logic-side address from memory tester dOut => cl_Din, -- logic-side data to MEM from memory tester progress=> progress -- current phase of memory test ); -- MEM memory controller module u1: memCntMod generic map( FREQ => FREQ, -- master clock frequency DATA_WIDTH => cl_Din'length, -- width of the logic and MEM databus NROWS => 4096, -- number of rows in the MEM NCOLS => 256, -- number of columns in each row CL_ADDR_WIDTH => cl_addr'length, -- logic-side address width MC_ADDR_WIDTH => mc_addr'length -- MEM-side address width ) port map( clk => clk, -- master clock from external clock source (unbuffered) bufclk => clk_b, -- buffered master clock output clk1x => clk_i, -- synchronized master clock clk2x => open, -- synchronized doubled master clock lock => lock, -- DLL lock indicator rst => rst_i, -- reset cl_rd => cl_rd, -- logic-side MEM read control from ImBinar cl_wr => cl_wr, -- logic-side MEM write control from memory tester prog => begun, -- indicates memory read/write has begun rdDone => rdDone, -- indicates MEM memory read operation is done done => done, -- indicates MEM memory read or write operation is done cl_addr => cl_addr, -- logic-side address from memory tester to MEM cl_Din => cl_Din, -- test data pattern from memory tester to MEM cl_Dout => cl_Dout -- MEM data output to memory tester sclkfb => sclkfb, -- clock feedback with added external PCB delays sclk => sclk, -- synchronized clock to external MEM mc_cke => mc_cke, -- MEM clock enable mc_cs => mc_cs, -- MEM chip-select mc_ras => mc_ras, -- MEM RAS mc_cas => mc_cas, -- MEM CAS mc_we => mc_we, -- MEM write-enable mc_ba => mc_ba, -- MEM bank address mc_addr => mc_addr, -- MEM address mc_data => mc_data, -- MEM databus udqm => udqm, -- MEM UDQM ldqm => ldqm -- MEM LDQM ); --
indicate the phase of the ImBinar on the seven segment seven_seg <= "1110111" when progress="000" "0010010" when progress="001" "1011101" when progress="010" "1011011" when progress="011" "0111010" when progress="100" "1101011" when progress="101" "1111111"; end arch;
=!
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-------
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