®
Design Idea DI-22 ®
TOPSwitch-GX 70 W, 19 V External Laptop Adapter Application
Device
Power Output
Input Voltage
Output Voltage
Topology
Laptop Adapter
TOP249Y
70 W
85-265 VAC
19 V
Flyback
Design Highlights
Operation
• High effi efficienc ciency: y: 84% at 85 VAC (wit (with h 50 50 ˚C exter external nal ambient temperature) • Low compon component ent count count and high high power power density, density, 7 W/in. W/in. 3 • Ver Very y compa compact ct desi design gn (4.1 (4.1 in. × 2.225 in. × 1.06 in.) • No surfa surface ce mount mount compon component entss requir required ed • Low zero zero load load power power consum consumptio ption, n, <370 <370 mW at 115 115 VAC • Appr Approxima oximately tely consta constant nt overloa overload d power power with with line voltag voltagee • Line underv undervolta oltage ge detectio detection n (UV) (UV) and overvo overvoltage ltage (OV) shutdown • Low EMI EMI - switching switching freque frequency ncy jitter jitter helps helps meet meet CISPR22 CISPR22B/ B/ EN55022B limits • Full Fully y protected protected for overlo overload, ad, short short circuit circuit and therma thermall faults faults
The design utilizes a TOP249Y in a flyback converter providing a 70 W output in a sealed enclosure at an external ambient of 50 ˚C. ˚C. Line UV and OV OV (100 V and 450 V, respectively) are implemented using a single 2 M ! resistor (R1). Undervoltage eliminates eliminates power-up/down glitches and overvoltage provides line transient and long duration power system surge protection. Resistor R10 programs the internal current limit to 75% of nominal at the the UV threshold. As a function of input voltage the current limit is further reduced by R9 to provide approximately constant overload power. The larger TOPSwitch-GX selection reduces conduction losses, raising efficiency (without circuit changes or increased overload power) and permits a higher inductance design for reduced primary RMS currents, further increasing efficiency.
C7 2.2 nF
C13 C12 C11 0.33 µF 0.022 µF 0.01 µF 400 V 400 V 400 V
D2 MBR20100
Y1 Safety
BR1 RS805 8 A 600 V
1
2
VR1 P6KE200 2
9
D1 UF4006
C6 0.1 µF X2
RT1 10 Ω 1.7 A F1 3.15 A
t°
R9 13 MΩ S
6 5
C2 820 µF 25 V
R8 4.7 Ω
R10 20.5 kΩ
85-265 VAC
F
C8 0.1 µF 50 V
R3 6.8 Ω C5 47 µF 16 V
R1 270 Ω
U2 PC817A R2 1 kΩ
C15 TOPSwitch-GX 1 µF L 50 V TOP249Y CONTROL CONTROL U1 C X
C14 0.1 µF 50 V
19 V, 3.6 A RTN
D4 1N4148
T1
D
L3 75 µH 2A
L1 200 µH
8
R11 2 MΩ 1/2 W C1 150 µF 400 V
C3 820 µF 25 V
11
3
L2 820 µH 2A
D3 MBR20100
C4 820 µF 25 V R4 31.6 kΩ 1%
R13 562 Ω C9 1% 4.7 nF 50 V
U3 TL431
R7 56 kΩ
C10 0.1 µF 50 V R6 4.75 kΩ 1% PI-2691-033001
Figure 1. TOPSwitch-GX 70 W Laptop Adapter Schematic.
DI-22 To reduce winding and diode dissipation the secondary is split into two windings and diode OR’ed into the output capacitors (C2, 3). Regulation is provided by a secondary side reference (U3), the output voltage sensed by R4, R13 and R6.
TRANSFORMER PARAMETERS Core Material
FPQ26/20-A 2 TDK PC40 gappped for A LG = 843 nH/T
Bobbin
TDK BPQ26/20-1112CP
Winding Details
Primary: 9T + 9T, 2 x 26 AWG Shield: 1T, 8 mm x 0.015 mm Cu foil Secondary 1: 3T, 3 x 26 AWG T.I.W. Secondary 2: 3T, 3 x 26 AWG T.I. W. Bias: 2T, 8 mm x 0.015 mm Cu foil (T.I.W. = Triple Insulated Wire)
Winding Order (Pin Numbers)
Primary (2-1), Shield (1-NC), tape, Secondary 1 (12-9), Secondary 2 (11-8), Bias (6-5), tape, Primary (3-2), tape
Inductance
Primary: 273 µH ± 10%, Leakge: 3 µH (maximum)
Primary Resonant Frequency
1.5 MHz (minimum)
Key Design Points • D1 and VR1 clamp leakage inductance spikes. A Zener clamp provides lower zero load consumption than an RCD clamp and higher efficiency below full load. • C11 reduces VR1 dissipation, raising efficiency. • Additional differential filtering is provided by C13 and L3. • C12 provides high frequency bypass, reducing high frequency EMI. • Use foil windings to reduce dissipation and reduce leakage inductance. • Sandwich secondary winding between two halves of primary to reduce leakage inductance. • High core temperature reduces saturation flux density. Keep flux density below 3000 gauss (0.3 T) to prevent saturation. • Use 100 V Schottky diodes for highest efficiency. • Good layout practices should be followed: - Locate C8, R3, C5, R9, R10 and R11 close to U1. - Power and signal source currents should be separated, joined using a Kelvin connection at the SOURCE pin. - Minimize the primary and secondary loop areas to reduce parasitic leakage and EMI. • Consult DAK-11 and EPR-11 for more information.
Table 1. Transformer Construction Information.
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The products and applications illustrated herein may be covered by one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com. The PI Logo, TOPSwitch , TinySwitch and EcoSmart are registered trademarks of Power Integrations, Inc. PI Expert is a trademark of Power Integrations, Inc. ©Copyright 2002, Power Integrations, Inc. WORLD HEADQUARTERS AMERICAS Power Integrations, Inc. San Jose, CA 95138 USA Customer Service: Phone: +1 408-414-9665 Fax: +1 408-414-9765 e-mail:
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