بسم هللا الرحمن الرحيم
Al-Quds University Faculty of Engineering “Electronics Engineering Department”
Electronics Lab “Experiment #1” “Diode Characteristics”
Supervisor: “Rajaa Nawahdah” Demonstrator: “Mahmoud dababseh”.
Prepared by: “Rafat Hanna Al-Hawash” [20913425] “Tareq Hanna Al-Atrash” [20910083]
24-10-2011
Table of Contents: 2.1
Introduction……………………………………..…… 1 2.1.1 Objectives……………………………………….. 1 2.1.2 Equipments List…………………………………. 1
2.2 2.3 2.4
Theoretical Background………………………….………. 1 Experimental Results & Discussion……………………… 2 Conclusion………………………………………………8
Figures Table: Figure No. 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14
Page No. 1 2 2 3 3 4 4 5 5 6 6 6 7 8
Tables Table: Table No. 2.1 2.2
Page No. 7 7
2.1
Introduction:
2.1.1 Objectives: a) Study the analysis of circuits with diodes, applying DC input. b) Analyze diode networks; series & parallel configuration.
2.1.2 Equipment List: a) Si & Ge diodes. b) Resistors. c) Digital Multi Meter (DMM) as volt-meter. d) Power Supply.
2.2
Theoretical Background:
The analysis of circuits with diode and DC input requires that the state of the diode first be determined. In general a diode is in the “on” state if the direction of the current established by the applied sources matches that of the arrow in the diode symbol, noticing that: VD>=0.7 V for the silicon. VD>=0.3V for germanium. The state of the diode is first determined by mentally replacing the diode with a resistive element: Firstly: ON state (diode forward biased)
Fig 2.1
The resulting voltage and current levels are the following:
Voltage drop applied across the diode, and its value is equal to VK as shown in the equation. 1
Secondly: OFF state (diode reverse biased)
Fig 2.2
The resulting voltage and current levels are the following: (
)
Open circuit assumed across diode, so ID is (0 A). In the parallel configuration, the diode about small voltage (VK) is on and the other (high voltage) is off, and Vo in parallel network equaled to the voltage of the diode on.
2.3 Experimental Results & Discussion: 2.3.1Part1: Threshold voltages VT
VT = .546 V
VT = .233V
2.3.2Part2: Series Configuration a) +
VD
+
Si E
ID
5V
R
2.2 KΩ
Vo -
R (meas.) = 2.17 KΩ
Fig 2.3
b)
c) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 ) (
)
(
)
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜 39 ∗1
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
1
%
2
(
)
% %
(
)
(
)
( (
) )
d) R1
VD
+
+
Si
2.2 KΩ E
ID
5V
R2
1 KΩ
Vo -
R1 (meas.) = 2.17 KΩ R2 (meas.) =976 Ω
Fig 2.4
e)
f) 1
(
)
∗13 ∗1
(
)
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
(
)
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 % 𝑇ℎ𝑒𝑜 1 39 1 37 ∗1 % 1 39
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
1
(
)
(
)
(
)
%
In the two previous circuits the diode is forward biased, so a voltage drop applied across it in the circuit solving, in each calculated and measured, there is some source of error, because of less of accuracy in measuring components values. ======================================================================= g) R1 2.2 KΩ E
VD -
+ +
Si
5V
R2
1 KΩ
Vo -
R1 (meas.) = 2.17 KΩ R2 (meas.) =976 Ω
Fig 2.5
h)
(
)
(o.c.) (o.c.)
In the previous circuit the diode is reversed, and that cause it to be reverse biased, so it becomes an open circuit. -E - VD = 0 VD = -E The circuit current is zero because of the open circuit across the diode. =======================================================================
3
i) V1 +
Si
Ge
Vo
5V
E
R
2.2 KΩ
R (meas.) = 2.17 KΩ
Fig 2.6
j)
(
)
33 779
( (
779 𝐸𝑟𝑟𝑜𝑟(𝐼𝐷 )
)
𝐸𝑟𝑟𝑜𝑟(𝐼𝐷 )
)
(
k) 𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 % 𝑇ℎ𝑒𝑜 19 1 9 ∗1 % 19
𝐸𝑟𝑟𝑜𝑟(𝐼𝐷 )
1
)
7
(
)
(
)
( (
) )
%
2.3.3Part3: Parallel Configuration a) +
VR +
R 2.2 KΩ 5V
E
Si
Ge
Vo -
R (meas.) = 2.17 KΩ
Fig 2.7
b) 33
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 ) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 % 𝑇ℎ𝑒𝑜 33 7 ∗1 % 33
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
c)
31 %
In this parallel diode configuration circuit, the output voltage is equal to the smaller threshold voltage VT of the two diodes; that because the current flows through the branch with smaller voltage drop, so the current will not flow in the Silicon diode (o.c.), and the output voltage will be equal to VT of the Ge diode. =======================================================================
4
d) + VR1 +
R1 =2.2 KΩ 5V
E
Si
R2 1 KΩ
Vo -
R1 (meas.) = 2.17 KΩ R2 (meas.) =976 Ω
Fig 2.8
e)
f)
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 ) (
)
(
)
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
∗1
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
% (
%
(
%
(
)
(
) )
)
In this circuit, the output voltage is equal to VT of the diode, since no current flows in R2, because the voltage drop across R2 is greater than voltage drop across the diode. ======================================================================= g) +
VR +
R =2.2 KΩ 5V
E
Si
Ge
Vo -
R1 (meas.) = 2.17 KΩ R2 (meas.) =976 Ω
Fig 2.9
h)
i)
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 ) (
)
(
)
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 ) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
∗1 %
5
% %
(
(
) (
(
)
) )
2.3.4Part4: Positive logic AND Gate a) 5V Si Vo
Si 2.2 KΩ
R
5V
R1 (meas.) = 2.17 KΩ
Fig 2.10
b)
c) 𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 % 𝑇ℎ𝑒𝑜 9 ∗1 %
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
3%
d) Applying voltage for each terminal of the gate: 5V Si 5V Vo
Si 2.2 KΩ
R
5V
Fig 2.11
e) f) 0V Si 0V Vo
Si 2.2 KΩ
R
5V
R1 (meas.) = 2.17 KΩ
Fig 2.12
g) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜
%
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
∗1
%
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
3
%
6
In Positive Logic AND Gate, we found Voltage out in all cases, show in the table: 5(v) ≡ 1
AND
A
B
0(v) ≡ 0
0
0
0
0
0
1
0
1
0
1
1
1
Table 2.1
In the positive logic AND Gate can the diode became the FB if the voltage on the anode is equal and the voltage on the cathode is equal but the voltage in the cathode is largest. In the OR Gate can the diode any one nut equality became FB if the diode voltage on the anode smallest then cathode. OR
A
B
0
0
0
1
0
1
1
1
0
1
1
1
Table 2.2
2.3.5Part4: Bridge Configuration a) Si1
Si2 - Vo
5V
+
R1=1 KΩ
R3=2.2 KΩ
VR
3
+
R2=2.2 KΩ
-
R1 (meas.) = .75 KΩ R2 (meas.) =2.17 KΩ R3 (meas.) =2.17 KΩ
Fig 2.13
b) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑅 ) 𝐸𝑟𝑟𝑜𝑟(𝑉𝑅 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜 39 ∗1
𝐸𝑟𝑟𝑜𝑟(𝑉𝑅 )
1 3%
7
i) % %
2.3.6Part4: Practical Exercise a) Si1 - Vo 5V
+
R1=1 KΩ
R3=2.2 KΩ
VR
3
+
R2=2.2 KΩ
-
R1 (meas.) = .75 KΩ R2 (meas.) =2.17 KΩ R3 (meas.) =2.17 KΩ
Fig 2.14 (
)∗
(
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
)∗ ( (
)∗ )∗
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
𝑇ℎ𝑒𝑜 𝐸𝑥𝑝 ∗1 𝑇ℎ𝑒𝑜 1 39 1 37 ∗1 1 39
𝐸𝑟𝑟𝑜𝑟(𝑉𝑜 )
1
%
b)
%
%
2.4 Conclusion: * In the series configuration (Forward Bias), diode effect the circuit with voltage drop, and its value is VT. VR = E - VT *when using several diodes connected on series in the same direction, voltage drop is the summation of VT for each diode. *In parallel configuration, when diode is on, no current flow in the network connected with it on parallel. *when two diodes connected on parallel (both forward biased), the diode with less firing potential (VT) is on, and the other is off. Otherwise the forward biased diode is on. *when configuring two parallel diodes, they could form logic gates such as AND & OR Gates.
8
