Hard Disk Controller (Hdc)

HARD DISK CONTROLLER (HDC) INTRODUCTION The hard disk controller (HDC) has experienced rapid integration as driven by cost reductions. Moving from a sixchip design! the current HDC solution is one chip. "uture  products #ill integrate the read #rite channel into the HDC further reducing the total number  of parts the hard disk drive (HDD) #ill re$uire re$uire to perform its function. function. The presented presented here #ill #ill look look at the the curre current nt scale scale of inte integr grati ation on and and the the testa testabi bili lity ty issu issues es creat created ed by this this integration. HDC Functional Block Descrition

The Hard Disk Controller today is made up of the follo#ing common blocks% Host &nterface! 'uffer Controller! Disk e$uencer! rror Correction Code (CC)!

ervo Control! Central *rocessing +nit (C*+)! 'uffer Memory! and C*+ memory. ee "igure , for a block diagram of a disk drive. 1

Host Inter!ace

The host interface-s primary function is to provide a standard protocol for the Disk  Drive to talk to a host system. The host system can be anything from a server or *C to a simple peripheral or consumer productsuch as a printer or digital camera. There exists a number of distinct protocols in the disk drive industry for performing this link. ome of the maor interfaces are /T/! C&! and erial interfaces. The main driver bet#een selecting #hich interface to use is cost to performance. The design trend for the host interface is to have multiple interface blocks. ach block supports a particular host protocol and has a standard back end interface to the rest of the HDC. This allo#s for maximum synergy among designs. Depending on the interface chosen and the performance desired! the si0e of the host interface can vary dramatically from a fe# thousand gates to over a hundred thousand gates. Currently! the host interface is the only block that is covered by any kind of published industry standardalbeit many different public standards. These standards define physical transfers! re$uired registers! and command sets.  Bu!!er Controller

The main function of the buffer controller is to provide arbitration and ra# signal control to the bank of buffer memory. This memory can be tatic 1andom /ccess Memory (+M)! Dynamic 1andom /ccess Memory (D1/M)! or mbedded memory. Typically the host interface! disk se$uencer! CC! and C*+ all need access to this buffer memory. The  buffer controller! under some priority scheme! #ill prevent these blocks from colliding #hile accessing the memory buffer. This block may also contain logic to help #ith the automation of moving data to and from the host. The si0e of this block can vary depending on the number  of memory configurations supported by a single controller. Disk Se"uencer

The main task of the disk se$uencer is to oversee and manage the transfer of data  bet#een the disk interface (referred to in this as the 213 pins) and the data buffer. The term!  213! is defined as nonreturn to 0ero. The 213 bus has become a normal name for the 4bit data interface bet#een the read5#rite channel and the HDC. "or a disk #rite operation! the disk se$uencer takes user data! appends additional fields such as CC bytes! and #rites out the ne#ly formatted data to the media interface through the 213 pins.

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Conversely for a disk read operation! the disk se$uencer reads formatted data from the  213 pins and converts it back into user data that is then sent to the host interface. The  process is complicated by the fact that disk media has servo #edges #ritten on it that cannot  be over #ritten by user data. (ervo #edges! typically 6747 per revolution! contain gain control information for the read#rite channel8 cylinder5track location information8 and head alignment patterns. The servo #edges are #ritten at the factory by special e$uipment called! 9ervo :riters.;) The user data sometimes must be split on either side of these servo #edges. The disk se$uencer handles the split data fields for both read and #rite operations. "urthermore! since the spinning disk cannot be throttled! the data rate from and to the disk must remain constant. The se$uencer is in charge of pulling data from registers! data buffers! and the CC  block at precise times in a disk #rite operation! and in charge of sending the 213 data to the correct blocks during a disk read operation. The disk se$uencer is often referred to as the disk  formatter. Ser#o Control

The servo control block has a lot of different definitions depending on the particular  implementation. ervo block refers to general logic used in aiding the spinning of the discs and in the positioning of the actuator on the disc. &t does not refer to the po#er devices necessary to drive the spindle motors. This block is uni$uely customi0ed to the particular  customer-s strategy for motion control d the Head Disk /ssembly (HD/). Therefore! it is difficult to standardi0e and thus lends itself to an /pplication pecific tandard *roduct (/*) strategy.  C$U (Central $rocessin% Unit(s))

The C*+ of the HDC can be implemented in multiple #ays. ingle ?bit microprocessors and Digital ignal *rocessors (D*) have been used! as #ell as combinations of these cores. These cores are used to control the overall system or may have a very specific task. The C*+ has the highest gate count of all the logic blocks except memory. &t is also the most complex from a simulation and integration standpoint.

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T&e C&allen%e o! Inte%ration

 &ntegration of more and more HDC functional blocks into a single chip is not #ithout issues. :hile integration can lead to cost savings! if not managed appropriately! it can lead to cost increases! or even failure of the proect. /s each module #as integrated over the years! the externally observable connections #ere no longer available for test. This forced the designer to find alternative methods for  testability #ithout adding significant cost to the final product. The testability issues have different obectives% development tests for the designer to prove function8 #afer tests #hich ensure the die #as successfully manufactured8 final assembly tests to verify the customer  receives a functional part8 and fnally a means for the customer to develop and debug application firm#are5soft#are on the embedded microprocessor. :e #ill no# look at the  process for developing the product in greater detail and each of the testability obectives.

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@nce the definition and design has been completed! the conversion to hard#are  begins. Most of us have seen HDA to netlist flo#s. Highlighting some important aspects of  the flo# sho#n in "igure ?! static timing analysis (T/) and formal verification have become a very important step in the development of the highly integrated HDC. T/ is a fast method of inspecting the intermodule and intramodule timings! clock ske#! and test mode timings created during synthesis.

CONCLUSION &ntegration has brought the price of the hard disk drive do#n for the consumer. This has sho#n ho# designers have dealt #ith the integration in terms of testability and design flo#. /s integration continues to bring more functionality into the HDC! designers #ill need to manage the testability issue. 2e# methods for tackling the three vie#points (designer!  production! and customer) are #aiting to be found.

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