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PROJECT REPORT
Sir Nouman
Afraz Liaqat
2009-EE-13
Bilal Ahmed
2009-EE-18
Fuad Asim
2009-EE-26
Design Requirements: 1. Rin >= 15k 2. Vout (p-p) max before clipping =20V symmetrical with R L = 100
ohm. 3. Output DC level <=50mV 4. Output DC current <=10mA 5. Av variable from ≈ 0 to 2000. 6. Bandwidth from 10Hz to 20kHz.
Design Description: We have used 4 gain stages of BJT multistage amplifiers with each having a gain of 10. All stages are Common Emitter unbypassed and identical. The DC quiescent point (V C) in each stage is set to 1.5V in order to achieve a max peak to peak output. The drop across emitter resistance is 5% of the total voltage and to compensate for the low negative feedback, the R th of each stage is kept higher than 10R E. For coupling different stages we have used RC coupling method. For designing, DC we have assumed I B = 0. For AC analysis β is taken to be 100.
st
1 Stage Design: VRE = 5 % of total voltage = 5/100 * 30 = 1.5V Av = 10 As we know, Av = RC / RE = 10 If we take R E = 560 Ω then RC comes out to be 5.6 k Ω As VRE = 1.5 V => VE = 1.5V - 15V = -13.5 V So, VB = VE + 0.7 = -12.8V Now we want Rin ≥ 15k ---------------- (a) We know that Rin = Rth || βRE Then Rth ≥ 24k to satisfy equation (a) Also, VB = R2 * 30 / (R 1 + R2) - 15 = -12.8 ------- (1) And Rth = R1 || R2 ----------------------------------- (2) Solving equations (1) & (2) and replacing the resistors with standard values we get, R1 = 300kΩ R2 = 27kΩ RC = 5.6kΩ RE = 560Ω As all our stages are identical, designing each separately is unnecessary.
Coupling Capacitor Designing: We require the lower cutoff f L ≤ 10 Hz. The output impedance of each stage is R C = 5.6k and Rin = Rth || βRE = 17k We design the first stage to have a lower cutoff at 5Hz.
Using the formula f C = 1/(2πRC) where R is the sum of resistance appearing and the two terminals of the capacitor. For 1st stage: C1 = 1/(2π*(17k + 5.6k) * 5) = 1.4 µF Using standard value of 10µF. nd
For 2
stage we design for 0.5Hz , since R will be same the capacitor
comes out to be C 2 = 22µF (standard). rd
Similarly, for 3 stage we design for 0.05 Hz and C 3 = 220µF.
Variable gain: Variable gain has been achieved in the circuit with a variable resistor in series with the RE of the last stage. The varistor varies from 0 Ω to 1MΩ, which in turn increases the R E of the last stage and reduces the gain. When the varistor is set to 0 Ω, the gain of the last stage is 10 which produces the maximum overall gain. When it is increased to maximum i-e 1MΩ the gain of the last stage is 0.0056, which produces the overall gain ≈ 0.
Output Stage: We have used a CLASS AB AMPLIFIER circuit available on the internet. It consists of a complementary npn and pnp DARLINGTON PAIR. 4 diodes have been used to keep them forward biased in order to rectify the problem of Crossover Distortion.
Gain before output stage = A V1 * AV2 * AV3 * AV4 * Rin /(RS + Rin1) * Rin2/(Rin2 + Rout1) * Rin3 /(Rin3 + Rout2) * Rin4/ (Rin4 + Rout3) = 4019.74
Analysis: st
Since all our stages are identical we will only analyse 1 stage. We have designed R 1 = 300k , R 2 = 27k , R C = 5.6k , RE = 560Ω
VB = R2 /(R1 + R2) * 30 – 15 = -12.52 V VE = VB – 0.7 = -13.22V IE = (VE -15)/ IE = 2.36mA IC = IE = 2.36mA VC = 15 – ICRC = 1.784V VCE = VC – VE = 1.784 + 13.22 = 15.004 V
As evident above, the analysis is very close to the designed values.
The WinSpice Code and output are attached along with this report.
