1. Why APB instead of AHB?
The APB is simpler than the AHB. APB is sometimes optimized for reduced interface complexity and minimal power consumption for supporting peripheral functio ns. 2. Difference between APB and AHB
AHB stands for Advanced High-performance Bus and APB sands for Advanced Peripheral Bus. AHB uses a full duplex parallel communication whereas the APB uses m assive memory-I/O accesses. When comparing the usage, the APB is simpler than the AHB. APB has no pipelining. The APB is mainly proposed for connecting to simple peripherals. The APB comes with a low power peripheral. AHB has a single edge clock protocol, several bus masters, split transactions, single-cycle bus master handover, burst transfers, large bus widths and non-tristate implementation. In AHB, the transaction consists of an address phase and a data phase. In case of AHB, there is only one Bus master at a time. But APB is only used for low bandwidth control accesses. Though the APB has an address phase and data phase as like that of the AHB, it comes with a list of low complexity signal. 3. What is the difference between SPLIT and RETRY responses in AHB? Ans: Both the Split and Retry responses are used by slaves which require a large number of cycles to
complete a transfer. These responses allow a data phase transfer to appear completed to avoid stalling the bus, but at the same time indicate that the transfer should be re-attempted when the master is next granted the bus. The difference between them is that a SPLIT response tells the Arbiter to give priority to all other masters until the SPLIT transfer can be completed (effectively ignoring all further requests from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the RETRY response only tells the Arbiter to give priority to higher priority masters. A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it allows the maximum efficiency to be made of the bus bandwidth. The master behaviors is identical to both SPLIT and RETRY responses, the master has to cancel the next access and re-attempt the current failed f ailed access. 4. What value should be used for HTRANS when an AHB master gets a RETRY response from a slave in the middle of burst?
Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it may also be necessary to adjust the HBURST information (usually just to indicate INCR).
5. What address should be on the bus during the IDLE cycle after a SPLIT or RETRY?
It does not matter what address is driven onto the bus during this cycle. The slave selected by the
driven address should not take any action and must respond with a zero wait state OKAY response. In many cases it will be simpler for the master to leave the address unaltered during this cycle, so that it remains at the address of the next transfer that the master wishes to perform and only in the following cycle does the master return the address to that of the transfer that must be repeated because of the SPLIT or RETRY response. In some designs it may be possible for the master to return the address to that required to repeat the previous transfer during the IDLE cycle and this behaviour is also perfectly acceptable.
6. Do all masters have to support SPLIT and RETRY?
Yes. All masters must support SPLIT and RETRY responses to ensure they are compatible with any bus slave. A master will handle both SPLIT and RETRY responses in an identical manner.
7. Can a SPLIT or RETRY response be given at any point during a burst?
Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any transfer during a burst. The slave is not restricted to only giving these responses to the first transfer.
8. Will a master always lose the bus after a SPLIT response?
Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same cycle that it gives the SPLIT response and therefore the master will always lose the bus.
9. Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response?
No. The specification requires that HSPLITx can only be asserted after the slave has given a SPLIT response.
10. Do all slaves have to support the SPLIT and RETRY responses?
No. A slave is only required to support the response types that it needs to use. For example, a simple on-chip memory block which can respond to all transfers in just a few wait states does not need to use either the SPLIT or RETRY responses.
11. Can a slave use both SPLIT and RETRY responses?
Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT response should be used by any slave that may be accessed by many different masters at the same time. The RETRY
response is intended to be used by peripherals that are only accessed by one bus master.
Difference between AHB and AXI Explain APB and AHB using state machine How to reduce the number of clock cycles taken for a transfer in APB/AHB protocol.. Eg: suppose a transfer takes 4 clock cycles, how can we make it in 3. Explain addr phase and data phase in AHB
AHB vs. AXI AHB is Advanced High-performance Bus and AXI is Advanced eXtensible Interface. Both the ABH and AXI are Bus masters, which are really different in many aspects. When the Advanced High-performance Bus i s a single channel Bus, the Advanced eXtensible Interface is a multi- channel Bus. The AHB is also a shared B us whereas the AXI is a read/write optimized bus. In AHB, each of the bus masters will connect to a single-channel shared bus. On the other hand, the bus master in AXI will connect to a Read data channel, Read address channel, Write data c hannel, Write address channel and Write response channel.
Another difference that is noticed is that the Bus latencies in AHB start lower than the AXI. The AHB starts at 16 Byte transactions where as the AXI starts at 64 Byte transactions. It can also be seen that the AHB Bus utilization is higher than AXI utilization. Moreover, The Advanced eXtensible Interface uses around 50 per cent more power, which means that AHB has an edge over it. Advanced eXtensible Interface is the third generation of Advanced Microprocessor Bus Architecture interface. Some of the features of AXI incude separate address/control and data phases, burst based transactions with start address issued, support for unaligned data transfers using byte strobes, easy addition of register stages to provide timing closure and issuing o f multiple outstanding addresses. The AXI, which suits high speed sub-micrometer interconnect, mainly targets high clock frequency system designs and high performance. Some of the features of Advanced High-performance Bus includes single edge clock protocol, several bus masters, split transactions, pipelined operations, burst transfers, non-tristate implementation and large bus-widths.
1 . Difference between AXI3 and AXI4 1. AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to 256 beats. 2. AXI3 supports write interleaving. AXI4 does NOT support write interleaving 3. AXI3 supports locked transfers, AXI4 does NOT support locked transfers 4. AXI4 supports QoS, AXI3 does NOT suppor QoS.
2. why there is no separate response channel for read burst ? I would guess it is because the VALID/READY handshake mechanism only allows for traffic flow in one direction, so for read transactions the traffic flow is slave to master for both data and response, sharing a VALID/READY handshake, whereas for write transactions the data is master to slave, but the response is slave to master, hence the response needing a separate channel to support the required VALID/READY controls.
What is AXI Lite? Name five special features of AXI? Why streaming support,it's advantages? Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transaction What is the AXI capability of data interleaving? Explain out-of-order transaction support on AXI? Explain multiple outstanding address pending? Any flow control mechanism in AXI? How to ensure data integrity on AXI? What is 'last' signal? What are bursts and transfers?
Maximum size of a transfer? Write response codes? What is strobing in AXI?
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ? Answer : All of the AXI channels pass information in only 1 direction (only the xREADY signal goes against the channel direction), so for a slave to give a response back to the master for a write transaction, would need a separate channel. I guess this channel could have been defined to include a BRESP for each write data item, but this would increase the bandwidth requirement for this channel, and as in most applications you will just repeat the complete transaction for a non-OKAY response, few applications would make use of the additional detail of which transfer in a write burst caused a failure. You do give a RRESP response for each read data item because the higher bandwidth channel is already there, 2) How to terminate A read/write burst ? Specification says we can not stop bursts intermittantly. Answer : Simple answer, you cannot. As soon as the AXI master indicates that it will perform X number of transfers in a transaction, it must complete X transfers. There is no "Early Burst Termination" concept like there was in AHB. For write transactions the master could complete the burst, but driving the WSTRB bits all to logic '0' (dummy accesses) so that no data is actually being transferred to the slave, but for read transactions there is no equivalent, and so "real" read accesses will be completed.
In AHB Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses. All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.
3) Can A master can give WLAST in middle of a burst transfer ? Answer : No. WLAST can only be asserted while WVALID is high when the f inal WDATA of a burst is being transferred. Indicating WLAST (and WVALID) too early in a burst would be a protocol violation. Also, many slave designs will not use the WLAST input, and will simply count data items coming in, so this would not be a safe (or legal) method of terminating a burst.
4) in the same way if slave assersts RLAST before the completion of a busrt read? Answer : If the slave drives RLAST (and RVALID) too early, t his too is a protocol violation, and just as for the WLAST signal, some masters might not be monitoring RLAST, so this illegal use could be missed anyway. 5) If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and RLAST because we are getting individual beat responses anyway? WLAST and RLAST can be used by masters and slaves that need to be told when the final data in a burst is being transferred. Most masters and slaves will count the data coming in against how many transfers were indicated on AWLEN and ARLEN, so in these designs the xLAST inputs would not be required. However to support all master and slave designs, masters must always drive WLAST when appropriate, and slaves must drive RLAST. 6 ) Whats the exact use of Exclusive Read and Write Pair transaction? Where exactly these will be used? Semaphore passing: Semaphore passing is a software requirement, whereas my background is hardware, so please forgive any vagueness in the following answer. If you have a shared area of memory used for passing control information between masters (or processes running on a master), you want to make sure that you complete the READ/WRITE sequence without another master changing the shared lo cation. If your master read the shared memory location, and it was changed by another master before your master could complete the subsequent write to that location, the interim write from the other master would be lost, which could have an impact on how your system works (control information lost)
So Exclusive Accesses are a hardware mechanism to support the software, indicating to the master when it did have uninterrupted access to the shared location, meaning that no write accesses from other masters will be accidentally overwritten. 7) Is there a possibility that A Read transaction can complete in One Cycle?
Section 3.1.4 on 3.4 says that "A default ARREADY value of LOW is possible but not recommended, because it implies that the transfer takes at least two cycles, one to assert ARVALID and another to assert ARREADY" No. It would take a minimum of 1 clock cycle to pass the address from the master to the slave (assumes ARREADY was high when ARVALID was asserted), and then a minimum of 1 clock cycle to pass the data from the slave to the master (assumes RREADY was high when RVALID was asserted).
If ARREADY is initially low when an address is signaled on AR VALID, it will take one clock cycle for the slave to sample this ARVALID and then assert ARREADY (if it can accept the address), and the address handshake then completes on the next clock rising edge (when both ARREADY and ARVALID are high). So 2 clock cycles just to pass the address from master to slave if ARREADY defaults to LOW.
It would then take at least a further clock cycle before the read data could be returned to the master. ------------------------------------------------------------------------------------------------------------------------Exclusive access in AXI protocol This mechanism enables the implementation of semaphore type of operation without requiring the bus to remain the locked to a particular master for the duration of the operation. the advantage of exclusive access is that semaphore type operation does not impact either critical bus access latency or the maximum achievable bandwidth. four Atomic access: Normal, exclusive, locked and reserved the signal name for atomic access: AWLOCK n ARLOCK
consider a system in which two AXI master devices are using shared memory and as a system designer, you always will make sure that at a time your one master does not overwrite your m emory written by another master. Consider AXI Master 1 (M1) has initiated exclusive read transaction for address location 12'h100 to 12'h10F. Now slave will start monitoring these addresses for ARID given by M1. Now till exclusive write operation is performed slave monitors that address and if that address is changed by another master M2, it will give an indication of exclusive access failure during the exclusive write transaction and memory will not get updated by M1. How it works: What happened in above scenario is that Slave has reserved some memory resource for
M1 virtually by given exclusive read request from the master. When the master comes for write transaction for that memory location slave will allow writing that memory resource only if another master device is not using that memory resource other wise data is not written to the memory resource. So we can avoid memory overwrite problem for shared memory using EXCLUSIVE Access in AXI. Two different forms of burst transfers are allowed: • incrementing bursts, which do not wrap at address boundaries • wrapping bursts, which wrap at particular address boundaries
Difference between AXI3 and AXI4?
What is AXI Lite? Name five special features of AXI? Why streaming support,it's advantages? Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high? Explain AXI read transactionWhat is the AXI capability of data interleaving? Explain out-of-order transaction support on AXI? Explain multiple outstanding address pending? Any flow control mechanism in AXI? How to ensure data integrity on A XI? What is 'last' signal? What are bursts and transfers? Maximum size of a transfer? Write response codes? What is strobing in AXI?
A HB Interview Qu es tions
1.
How AHB is pipelined architecture?
2.
What is the size of max data can be transferred in single transfer?
3.
Explain 1k boundary concept in AHB?
4. 5.
Okay response is single cycle? but error/split/retry is two cycle, why? Explain the concept of two cycle response?
6. 7. 8.
What if the slave gets the address out of range? How to connect multiple slaves to single master? Explain the round robin arbitration concept?
9.
Explain the split-retry concept?
10.
What is the difference between HREADY and HREADY_OUT signals?
11. 12. 13.
What is the slave response for BUSY transfer? What is the difference between WRAP4 and INCR4? How to terminate the INCR type transfer?
14.
What is difference between BURST and Beat?
15.
How to calculate the size of the burst?
16. 17.
Is HREADY is Input or output to/from the slave? What is align and un-align concept?
18. 19. 20.
Explain wrapping calculation? Is early burst termination is done by Slave/Arbiter? Explain the LOCKED transfer?
21.
What is default Master?
22.
What is little-endian and big-endian?
23.
How slave will detects the end of INCR type burst transfer?
A XI I nterv iew Ques tions
1.
How AXI is different from AHB?
2.
Explain the concept of AXI 4KB boundary condition?
3. 4.
Explain the valid ready handshake in AXI? Explain the channel concept?
5. 6.
Explain the out-of-order concept? What is fixed burst type?
7.
Explain the AXI response types?
